JP3226677B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to an EEPROM which performs multi-value storage in which more than one bit of information is stored in one memory cell.

[0002]

2. Description of the Related Art As one type of EEPROM, a NAND type EEPROM which can be highly integrated is known. In this method, a plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones, and are connected to bit lines as one unit. The memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cell array is integrally formed in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to a bit line via a selection gate, and the source side is also connected to a common source line via a selection gate. The control gates of the memory cells are arranged continuously in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. Data writing is performed sequentially from the memory cell located farthest from the bit line. The high voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and the intermediate voltage Vppm (= 1) is applied to the control gate and the selection gate of the memory cell on the bit line side from the high voltage Vpp.
0V) and apply 0V to the bit line according to the data.
Alternatively, an intermediate voltage Vm (= about 8 V) is applied. When 0 V is applied to the bit line, the potential is transferred to the drain of the selected memory cell, and electron injection occurs in the charge storage layer.
As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, “1”. When Vm is applied to the bit line, electron injection does not occur effectively, so that the threshold value does not change and remains negative. This state is "0" in the erase state. Data writing is performed simultaneously on the memory cells sharing the control gate.

[0004] Data erasure is performed simultaneously for all memory cells in a NAND cell. That is, all control gates are set to 0V, and the p-type well is set to 20V. At this time, the selection gate, bit line and source line are also set to 20V. As a result, in all the memory cells, electrons in the charge storage layer are emitted to the p-type well, and the threshold value shifts in the negative direction.

For data reading, the control gate of the selected memory cell is set to 0 V, and the control gates and select gates of the other memory cells are set to the power supply potential Vcc (for example, 5 V).
This is performed by detecting whether or not a current flows in the selected memory cell.

Due to the restrictions on the read operation, the threshold value after writing "1" must be controlled between 0 V and Vcc. Therefore, the write verify is performed, and "1"
Only the memory cells with insufficient writing are detected, and rewriting data is set so that rewriting is performed only on the memory cells with insufficient writing of “1” (bit-by-bit verification). A memory cell with insufficient writing of “1” is detected by setting the selected control gate to, for example, 0.5 V (verify voltage) and reading (verify read).

That is, if the threshold value of the memory cell is not 0.5 V or more with a margin with respect to 0 V, a current flows in the selected memory cell and it is detected that "1" is insufficiently written. Since a current naturally flows in the memory cell set to the "0" write state, a circuit called a verify circuit for compensating the current flowing through the memory cell is provided so that the memory cell is not mistaken for "1" write shortage. This verify circuit executes write verify at high speed.

By performing data writing while repeating the write operation and the write verify, the write time is optimized for each memory cell, and the threshold value after “1” write is controlled between 0 V and Vcc. You.

In order to realize multi-value storage in this NAND cell type EEPROM, for example, it is considered that the state after writing is set to three states "0", "1", and "2".
The "0" write state has a negative threshold value, the "1" write state has a threshold value of, for example, 0 V to 1/2 Vcc, and the "2" write state has a threshold value of 1/2 Vcc to Vcc. In the conventional verify circuit, it is possible to prevent a memory cell to be written into "0" from being erroneously recognized as a memory cell with insufficient writing of "1" or "2".

However, since the conventional verify circuit is not for multi-value storage, the threshold value of the memory cell to be set to the "2" write state is higher than the verify voltage for detecting whether the "1" write is insufficient. In the case of a write shortage of Ｖ Vcc or less, there is a problem that when detecting whether or not write “1” is insufficient, a current does not flow in the memory cell and it is erroneously recognized that write is sufficient.

In order to perform multi-level write verification while preventing misunderstanding of insufficient writing, rewriting is performed for memory cells that have been sufficiently written for “1” and for memory cells that are to be written to “2”. Then, it is sufficient to detect whether or not the state of “2” writing is insufficient and perform the verify writing. However, in this case, the "2" write state is also set for the memory cell to be set to the "2" write state after the "1" write, so that it takes a long time to write and the write speed becomes slow.

[0012]

As described above, the conventional N
When multi-value storage is performed in an AND cell type EEPROM and bit-by-bit verification is performed by a conventional verification circuit, there is a problem that erroneous verification occurs.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to store multi-valued information and to speed up the write verify operation without causing erroneous verify. An object of the present invention is to provide a programmable EEPROM.

[0014]

The present invention employs the following configuration to solve the above-mentioned problems. That is, according to the present invention (claim 1), in a nonvolatile semiconductor memory device capable of storing multi-value data, electrical rewriting is enabled and
A memory cell array in which memory cells having a plurality of storage states are arranged in a matrix, a plurality of write data circuits for temporarily storing data for controlling a write operation state of the plurality of memory cells, and a memory Write means for performing a write operation according to the contents of the write data circuits respectively corresponding to the plurality of memory cells in the cell array, and write verify means for simultaneously confirming a state of the plurality of memory cells after the write operation; Means for updating the contents of the write data circuit so that rewriting is performed only on the insufficiently written memory cells from the contents of the write data circuit and the state after the write operation of the memory cells, Write operation, write verify, and write data Updates, memory cells and performing the electrical data writing by performing repeatedly until a predetermined write state.

The present invention (claim 2) has a memory cell array in which electrically rewritable memory cells are arranged in a matrix, and one memory cell has three or more storage states. Arbitrary data "i" (i = 0,
1, .about., N-1; n.gtoreq.3) and stores multi-valued data, and the storage state corresponding to data "0" is an erased state. For simultaneously performing a write operation according to the contents of the data circuits respectively corresponding to the plurality of memory cells in the memory cell array. Writing means; and i-th write verifying means for confirming whether or not the state of the plurality of memory cells after the write operation is the storage state of the data “i” at the same time; and (i = 1, 2,. n-1) The data circuit is designed to rewrite only the insufficiently written memory cells from the contents of the data circuit and the state after the write operation of the memory cells. Contents, i-th data circuit content batch update means for collectively updating the data circuit corresponding to the memory cell to the data "i" (i = 1, ~, n-
1) and the confirmation of the storage state by the i-th write verifying means and the batch updating by the i-th data circuit content batch updating means are performed on the data "1" to the data "n-1" by n
And a data circuit content updating means for updating the contents of all of the plurality of data circuits by one time. The i-th data circuit content batch updating means changes the state of the memory cell after the write operation by the i-th write verify means. Among the output bit line potentials, the bit line potential corresponding to the memory cell to be data "i" (i ≧ 1) is sensed / stored as rewrite data, and the memory to be in a state other than data "i" The bit line potential corresponding to the cell is sensed / stored so as to retain the contents of the data circuit, and the potential of the bit line from which the state after the write operation of the memory cell is output is corrected according to the contents of the data circuit. Until the bit line potential is corrected, the data storage state of the data circuit is maintained, and the data circuit is used as a sense amplifier while maintaining the corrected bit line potential. The operation is performed, the contents of the data circuit are updated collectively with respect to the data circuit corresponding to the memory cell to be data “i”, and the write operation and the data circuit content update based on the contents of the data circuit are performed in a predetermined write state. It is characterized in that data writing is performed electrically by repeatedly performing until data writing.

Here, preferred embodiments of the present invention include the following. (1) The data circuit controls the write operation state of the memory cell according to the data stored in the data circuit at the time of the write operation, and changes the state of the memory cell to a predetermined write state, or Control whether or not to maintain the state before the write operation. (2) The i-th data circuit content batch updating means controls the data circuit corresponding to the memory cell to be written with data “i” so as to change the memory cell to be in the data “i” write state. When the memory cell corresponding to the data circuit storing the data to be written has reached the write state of the data "i", the data of the data circuit is controlled so as to hold the state of the memory cell at the state before the write operation. In the case where the memory cell corresponding to the data circuit storing data for controlling data to be changed to the data and controlling the memory cell to be in the state of writing the data “i” has not reached the state of writing the data “i”, Setting data to be controlled to change the state of the memory cell so as to be in a state of writing data “i” in the data circuit; In the case where data for controlling the state of the memory cell to be held in the state before the write operation is stored in the data circuit, the data for controlling to hold the state of the memory cell in the state before the write operation is set in the data circuit, The i-th data circuit content batch updating means does not change the data circuit corresponding to the memory cell to be in the write state other than the data “i”. (3) The memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and the memory cell can store any data “i” (i = 0, 1,.
(n-1; n ≧ 3) is stored in multi-values with the magnitude of the threshold value, and a predetermined i-th verify potential is applied to the control gate by the i-th write verify means, and the data should be in the “i” state. Verifying whether the threshold value of the memory cell is a desired threshold value; (4) The storage state corresponding to the data “0” is the erased state, and the threshold value corresponding to the data “n−1” state has the largest difference from the threshold value corresponding to the data “0” state. The threshold value corresponding to the data "1", "2", ..., "i", ..., "n-2" state changes from the threshold value corresponding to the data "0" state to the data "n-1" state. Data "1", "2",..., "I",..., "N" in the order from the threshold value corresponding to the data "0" state.
The threshold value corresponding to the -2 "state is set, and the contents of the data circuit change the state of the memory cell among the bit line potentials at which the state after writing of the memory cell is output by the i-th write verifying means. When only the potential of the bit line corresponding to the data that is controlled to be held in the state before the write operation is sensed by the data circuit, the data is controlled to hold the state of the memory cell in the state before the write operation. A first bit line potential setting circuit for setting the first corrected bit line potential to be i-th (1 ≦ i ≦
Of the bit line potentials at which the state after writing of the memory cell is output by the write verifying means of n-2),
Data for controlling the contents of the data circuit to change the state of the memory cell to the state of writing the data "j" in the bit line corresponding to the memory cell to be in the state of data "j" (i + 1.ltoreq.j). A second correction bit which becomes data for controlling the state of the memory cell to change to the state of writing data "j" when only the bit line potential corresponding to the above is sensed by the data circuit. A j-th bit line potential setting circuit for setting the line potential to the bit line potential at which the state after the write operation of the memory cell is output by the i-th write verify in order to update the data circuit content; In accordance with the first, i + 1, i + 2,..., N−1 bit line potential setting circuits. (5) The data circuit includes a first data storage unit that stores, as information, whether or not to control the state of the memory cell to be maintained in a state before the write operation, and information in the first data storage unit that is stored in the memory cell. Is not controlled to hold the state before the write operation, the second state in which the memory cell stores the information indicating the write state “i” (i = 1, 2,..., N−1) to be stored. A data storage unit;
Of the data storage unit is updated by the first, i + 1, i + 2,..., N-1 bit line potential setting circuits according to the contents of the data circuit for updating the contents of the data circuit. And a function of sensing / storing the potential of the bit line to which the state after the write operation is output. (6) If the information in the first data storage unit is information for controlling the state of the memory cell to be maintained in a state before the write operation, a write-protect bit that outputs a write-protect bit line voltage to the bit line during the write operation In the case where the line voltage output circuit and the information in the first data storage unit are not controlled to hold the state of the memory cell in the state before the write operation, the write state to be stored in the memory cell in the second data storage unit An i-th write bit line voltage output circuit for outputting a bit line voltage at the time of the i-th write operation according to information indicating “i” (i = 1, 2, to n−1). (7) The first bit line potential setting circuit and the write protection bit line voltage output circuit are a common first bit line voltage control circuit. When the data circuit content is updated, the voltage is such that its output becomes the first correction bit line potential, and the j-th (j = 2, 3,..., N−1)
The bit line potential setting circuit and the j-th write bit line voltage output circuit are a common j-th bit line voltage control circuit. And a voltage whose output becomes the second correction bit line potential when the data circuit contents are updated. (8) The memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer.
An ND cell structure is formed. (9) The memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer to form a NOR cell structure.

[0017]

The multi-value (n-value) storage type EEPROM according to the present invention
M is configured to perform a verify read operation from n-1 basic operation cycles. Erase state is “0”
Assuming that the multi-level levels are “0”, “1”,..., “I”,..., “N−1” in ascending order of the threshold value of the memory cell, whether the “i” write is sufficient in the i-th cycle It is configured to verify only whether or not. For this reason, a verify potential generating circuit for applying a predetermined i-level verify voltage in the i-th cycle so that a current flows through the memory cell if "i" writing is insufficient for the selected control gate, A sense amplifier is provided for detecting whether or not writing is sufficient by detecting the voltage of the bit line. i
In the third cycle, the bit lines of the memory cells to which "0",..., "I-1" are written are compensated for the current of the memory cells if it is already detected that the writing is sufficient, and detected that the writing is insufficient. If so, a first verify circuit is provided so that the current of the memory cell is not compensated. In the i-th cycle, the bit line of the memory cell to which "i + 1",..., "n-1" is to be written is compensated for by the first verify circuit if the write operation has already been detected. If it is detected that writing is insufficient, a second verify circuit for setting a bit line voltage as if a current of a memory cell has flown is provided.

Further, a first register for storing whether data is sufficiently written or not and a second register for storing any one of the multi-valued levels "1" to "n-1" are stored. The first register also has a function of a sense amplifier for detecting whether or not writing is sufficient. Further, if there is a memory cell that has not reached the desired write state, rewriting is performed only on that memory cell,
A bit line write voltage output circuit for outputting a bit line voltage at the time of writing according to a desired write state is provided.

In the present invention, after performing the multi-level data write, it is detected whether or not the write state of each memory cell has reached the desired multi-level level state. If there is a memory cell that does not reach a desired multi-value level, a bit line voltage at the time of writing is output according to a desired writing state so that rewriting is performed only on that memory cell. This write operation and verify read are repeated, and when it is confirmed that all the memory cells have reached the desired write state, the data write ends.

As described above, according to the present invention, one write time is shortened, and the write operation is repeated little by little while checking the progress of the write state. Decreasing the threshold value of the memory cell can be performed at high speed.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a NAND according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a schematic configuration of a cell type EEPROM.

For the memory cell array 1,
A bit line control circuit 2 for controlling a bit line at the time of writing and a word line drive circuit 7 for controlling a word line potential are provided. The bit line control circuit 2 and the word line drive circuit 7 are selected by a column decoder 3 and a row decoder 8, respectively. The bit line control circuit 2 includes an input / output data conversion circuit 5 via a data input / output line (IO line).
And read data / write data are exchanged.
The input / output data conversion circuit 5 converts the read multi-value information of the memory cell into binary information for outputting to the outside, and converts the binary information of the write data input from outside into the multi-value information of the memory cell. Convert. The input / output data conversion circuit 5 includes a data input / output buffer 6 for controlling data input / output with the outside.
Connected to. The data write end detection circuit 4 detects whether the data write has ended.

FIGS. 2 and 3 show a specific configuration of the memory cell array 1 and the bit line control circuit 2. FIG. With the memory cells M1 to M8 and the selection transistors S1 and S2, NAN
Construct a D-type cell. One end of the NAND type cell is connected to the bit line BL, and the other end is connected to the common source line Vs. Select gates SG1 and SG2, control gates CG1 to CG
G8 is shared by a plurality of NAND cells, and a memory cell sharing one control gate constitutes a page. The memory cell stores data at the threshold value Vt. When Vt is 0 V or less, "0" data, and when Vt is 0 V or more.
The data is stored as "1" data when the voltage is 5 V or less, and as "2" data when Vt is 1.5 V or more and the power supply voltage or less. One memory cell has three states, and two memory cells have 9 states.
There are different combinations. Of these, eight combinations are used to store 3-bit data in two memory cells. In this embodiment, a set of two adjacent memory cells sharing a control gate stores 3-bit data. The memory cell array 1 is formed on a dedicated p-well.

Clock synchronous inverters CI1 and CI2
, CI3 and CI4 form flip-flops, respectively, and latch write / read data. They also operate as sense amplifiers. The flip-flop constituted by the clock synchronous inverters CI1 and CI2 latches "whether to write" 0 "or" 1 "or" 2 "" as write data information, and the memory cell " Whether the information “0” is held or the information “1” or “2” is held ”is latched as read data information. The flip-flop composed of the clock synchronous inverters CI3 and CI4 latches "whether" 1 "write or" 2 "write" as write data information, and the memory cell is "2". Whether information is held or whether “0” or “1” is held ”is latched as read data information.

Q of the n-channel MOS transistors
n1 transfers the voltage VPR to the bit line when the precharge signal PRE becomes "H". Qn2 connects the bit line to the main bit line control circuit when the bit line connection signal BLC becomes "H". Qn3 to Qn6, Qn9 to Qn12
Selectively transfers the voltages VBLH, VBLM and VBLL to the bit lines according to the data latched in the flip-flop. Qn7 and Qn8 are signals SA, respectively.
When C2 and SAC1 become "H", the flip-flop is connected to the bit line. Qn13 is provided for detecting whether or not all the data for one page latched in the flip-flop are the same. Qn14, Qn15 and Q
n16 and Qn17 are column selection signals CSL1 and CS, respectively.
L2 changes to "H" to selectively connect the corresponding flip-flop to the data input / output lines IOA and IOB.

In FIG. 3, the inverter part is shown in FIG.
Although it is omitted as shown in FIG. 9A, it has the circuit configuration shown in FIG. 19B. Next, the operation of the EEPROM configured as described above will be described with reference to FIGS. 4 shows the timing of the read operation, FIG. 5 shows the timing of the write operation, and FIG. 6 shows the timing of the verify read operation. In each case, control gate C
The case where G4 is selected is shown as an example.

The read operation is performed in two basic cycles. In the first read cycle, first, the voltage VPR becomes the power supply voltage Vcc, the bit line is precharged, and the precharge signal PRE becomes "L", and the bit line is floated. Subsequently, select gates SG1, SG2
, Control gates CG1 to CG3, CG5 to CG8 are Vcc
It is said. At the same time, the control gate CG4 is set to 1.5V. Only when Vt of the selected memory cell is 1.5 V or higher, that is, only when data “2” is written, the bit line is kept at “H” level.

Thereafter, sense activation signals SEN2, SE
N2B is "L" and "H" respectively, and the latch activation signal LA
T2 and LAT2B become "L" and "H", respectively, and the flip-flop constituted by the clock synchronous inverters CI3 and CI4 is reset. The signal SAC2 becomes "H" and the clock synchronous inverters CI3, CI
4 and the bit line are connected. First, the sense activation signals SEN2 and SEN2B become "H" and "L", respectively, and the bit line potential is sensed. Then, the latch activation signals LAT2 and LAT2B becomes "H" and "L", respectively, and the clock synchronous inverter CI
3 and CI4 flip flop,
The information “whether“ 2 ”data, 1” or “0” data is latched.

The second read cycle includes the first read cycle, the fact that the voltage of the selection control gate CG4 is 0 V instead of 1.5 V, and the signals SEN2, SEN2B, LAT2,
Instead of LAT2B and SAC2, signals SEN1 and SEN1
The difference is that B, LAT1, LAT1B, and SAC1 are output. Therefore, in the second read cycle, the flip-flop composed of the clock synchronous inverters CI1 and CI2 is used.
The information “whether“ 0 ”data,“ 1 ”or“ 2 ”data” is latched in the flop.

The data written in the memory cell is read by the two read cycles described above. Prior to data writing, the data in the memory cell is erased, and the threshold value Vt of the memory cell is 0 V or less. For erasing, the p-well, the common source line Vs, and the selection gates SG1 and SG2 are set to 20 V, and
8 is set to 0V.

In the write operation, first, the precharge signal PRE becomes "L", and the bit line is floated. The selection gate SG1 is at Vcc and the control gates CG1 to CG
G8 is set to Vcc. The select gate SG2 is at 0 V during the write operation. At the same time, the signals VRFY1, VRFY2,
FIM and FIH become Vcc. In the case of writing "0", since the data is latched in the flip-flop constituted by the clock synchronous inverters CI1 and CI2 so that the output of the clock synchronous inverter CI1 becomes "H", the bit line is It is charged by Vcc. “1”
Alternatively, in the case of "2" write, the bit line is at 0V.

Subsequently, the selection gate SG1 and the control gate C
G1 to CG8, signal BLC, signal VRFY1 and voltage VS
A is 10V, voltage VBLH is 8V, and voltage VBLM is 1V. In the case of writing "1", the flip-flop constituted by the clock synchronous inverters CI3 and CI4
Since the data is latched so that the output of the clock synchronous inverter CI3 becomes "H", 1 V is applied to the bit line BL. In the case of "2" writing, the bit line is at 0V, and in the case of "0" writing, it is at 8V. After this,
The selected control gate CG4 is set to 20V.

In the case of writing "1" or "2", electrons are injected into the charge storage layer of the memory cell due to the potential difference between the bit line BL and the control gate CG4, and the threshold value of the memory cell rises. In the case of “1” write, the amount of charge to be injected into the charge storage layer of the memory cell must be reduced as compared with “2” write, so that the bit line BL is set to 1
V to reduce the potential difference from the control gate CG4 to 19V. However, the present invention can be implemented without easing the potential difference. At the time of writing "0", the threshold value of the memory cell is not effectively changed by the bit line voltage of 8V.

At the end of the write operation, first, the selection gate SG1 and the control gates CG1 to CG8 are set to 0V, and "0" is set.
The voltage 8V of the bit line BL at the time of writing is reset to 0V with a delay. This is because if this order is reversed, a state of a "2" or "1" write operation is temporarily created, and incorrect data is written when "0" is written.

After the write operation, the verify read is performed to check the write state of the memory cell and perform additional write only to the memory cell with insufficient write. During the verify read, the voltage VBLH is Vcc and VBLL is 0.
V and FIM are 0V.

The verify read is executed from two basic cycles. This basic cycle is similar to the second read cycle. The difference is that the selected control gate C
That is, the voltage of G4 and the signals VRFY1, VRFY2, and FIH are output (only VRFY1 in the first cycle of verify reading). Signals VRFY1, VRFY2
, FIH output the signal SEN after the selection gates SG1 and SG2 and the control gates CG1 to CG8 are reset to 0V.
1, SEN1B, LAT1, LAT1B are “L”,
It is output before it becomes “H”, “L”, or “H”. In other words, after the potential of the bit line is determined by the threshold value of the memory cell, the clock synchronous inverters CI1 and C1
Before the flip-flop constituted by I2 is reset. The voltages of the selected control gates CG4 are 2V (first cycle) and 0.5V (second cycle) corresponding to 1.5V (first cycle) and 0V (second cycle) at the time of reading. The height is increased to secure a threshold margin of 0.5V.

Here, the clock synchronous inverter CI
1 and CI2, the data (data1) latched in the flip-flop constituted by the clock synchronous inverters CI3 and CI4, and the data (data2) latched in the flip-flop constituted by the clock synchronous inverters CI3 and CI4. The voltage of the bit line BL determined by the threshold will be described. data1 is “0” write or “1”
Or "2" write ". In the case of" 0 "write, Qn3 is in the" ON "state, and in the case of" 1 "or" 2 "write, Qn6 is in the" ON "state. data2 controls “whether“ 1 ”write or“ 2 ”write”
In the case of "1" write, Qn10 is in "ON" state, "2"
In the case of writing, Qn11 is in the "ON" state.

In the first verify-read cycle when "0" data is written (initial write data is "0"), since the data of the memory cell is "0", when the control gate CG4 becomes 2V, the bit line is set by the memory cell. The potential becomes "L". After that, when the signal VRFY1 becomes "H", the bit line BL becomes "H".

In the first verify-read cycle when "1" data is written (initial write data is "1"), the data of the memory cell should be "1". Below, control gate C
When G4 becomes 2V, the bit line potential becomes "L" by the memory cell. After that, when the signal VRFY1 becomes "H", the bit line BL becomes "H" (FIG. 6) when "1" has already been sufficiently written and data1 indicates "0" write.
(1)), otherwise, the bit line BL is "L" ((2) in FIG. 6).
).

In the first verify-read cycle when "2" data is written (initial write data is "2"), if the data of the selected memory cell is not "2"("2" write is insufficient), the control is performed. Gate CG4 is 2
When it becomes V, the bit line potential becomes "L" by the memory cell ((5) in FIG. 6). When "2" is sufficiently written in the selected memory cell, the bit line potential remains "H" even when the control gate CG4 becomes 2V ((3) in FIG. 6).
(Four)). (3) of FIG.
This is the case where a1 indicates “0” writing. In this case, the bit line BL is recharged by the voltage VBH when the signal VRFY1 becomes "H".

In the second verify-read cycle when "0" data is written (initial write data is "0"), the data in the memory cell is "0". The bit line potential becomes "L". Thereafter, when the signal VRFY1 becomes "H", the bit line BL becomes "H".

In the second verify-read cycle at the time of writing “1” data (initial write data is “1”), if the data of the selected memory cell is not “1” (“1” write is insufficient), control is performed. When the gate CG4 becomes 0.5 V, the bit line potential becomes "L" by the memory cell ((8) in FIG. 6). Selected memory cell is "1"
When writing is sufficient, the bit line potential remains "H" even when the control gate CG4 becomes 0.5 V (FIGS. 6 (6) (7)). FIG. 6 (6) shows a case where "1" has already been sufficiently written and data1 indicates "0" write. In this case, when the signal VRFY1 becomes "H", the bit line BL is recharged by the voltage VBH.

In the second verify-read cycle when "2" data is written (the initial write data is "2"), the data of the memory cell should be "2". If this is the case, the control gate CG4 is set to 0.5
V, the bit line potential remains "H" (FIG. 6).
(9) (10)). When "2" is insufficiently written and the threshold value of the memory cell is 0.5 V or less, the bit line becomes "L" ((11) in FIG. 6).

Thereafter, the signals VRFY1, VRFY2, F
When IH is set to "H", the bit line BL is set to "H" ((9) in FIG. 6) if "2" has already been sufficiently written and data1 indicates "0", otherwise the bit line BL
Becomes "L" ((10) (11) in FIG. 6). By this verify read operation, rewrite data is set as shown in the following (Table 1) from the write data and the write state of the memory cell.

[0045]

[Table 1] As can be seen from (Table 1), "1" writing is performed again only on memory cells where "1" writing is insufficient, and "2" writing is performed again only on memory cells where "2" writing is insufficient. . When data writing is sufficient in all memory cells, Qn13 in all columns is turned "OFF", and data write end information is output by the signal PENDB.

FIGS. 7A and 7B show data input / output operation timing. FIG. 7A shows data input timing, and FIG. 7B shows data output timing. After three cycles of external data input, the input / output data conversion circuit 5 generates and inputs data to be input to the bit line control circuit 2.
3-bit data from outside (X1, X2, X3)
Are converted into data (Y1, Y2) of two memory cells, and are effectively registers R1 and C2 composed of clock synchronous inverters CI1 and CI2 of the bit line control circuit 2.
Conversion data is set in a register R2 composed of I3 and CI4 via data input / output lines IOA and IOB.
The read data latched by the registers R1 and R2 are transferred to the input / output data conversion circuit 5 via the data input / output lines IOA and IOB, converted and output. It is also possible to make the column selection signals CSL1i and CSL2i shown in FIG. 3 the same signal, and instead divide the IOA and IOB into two systems to simultaneously access two registers in the same column simultaneously, thereby shortening the access time. In order to be effective.

The following Table 2 corresponds to three bits of external data (X1, X2, X3), two data of memory cells (Y1, Y2), and Y1, Y2 at the time of data input. The relationship between the data in the registers R1 and R2 is shown.

[0048]

[Table 2]

The data of the register is represented by the voltage level of the input / output line IOA at the time of data transfer. The data input / output line IOB is omitted because it is an inverted signal of IOA. The following (Table 3) is that at the time of data output.

[0050]

[Table 3] In this embodiment, the level of the IOA at the time of input and the level of the IOA at the time of output are inverted for the same data.

Since one of the nine combinations of the two data (Y 1, Y 2) of the memory cell remains, it can be used for file management information such as pointer information. Here, the pointer information is stored in the cell data (Y1,
Y2) = (2,2).

FIG. 8 shows the concept of a page, which is a unit of data writing, as viewed from a microprocessor or the like controlling the EEPROM. Here 1
The page has N bytes, and an address (logical address) as viewed from a microprocessor or the like is displayed. For example, when write data is input only to the area 1 (logical addresses 0 to n), n = 3m + 2 (m = 3m + 2)
0, 1, 2,...), There is no problem since (X1, X2, X3) are always aligned. When n = 3 m, only X1 is input, so that X2 = 0, X3 = 0 is generated inside the EEPROM and (X1, X2, X3) is input to the input / output data conversion circuit 5.
To enter. When n = 3m + 1, X3 = 0 is generated internally. The same applies when n is equal to N.

Data was written to area 1 (area 2
In the case where data is additionally written to the area 2 after all the write data "0"), it is sufficient to read the area 1 and add the write data of the area 2 to the data. Alternatively, read the portion of area 1 and
If the start address n + 1 = 3m of the area 2, all data in the area 1 is “0”, and if n + 1 = 3m + 2, the address n
The data of -1 and n are added to the data X3 of the address n + 1 as X1 and X2, and all the data up to the address n-2 of the area 1 are "0". In the case of n + 1 = 3m + 1, the data of the address n is X1 and the address n + 1, Data X of n + 2
2 and X3, all data up to the address n-1 of the area 1 may be set to "0". These operations are based on the EEP
It is also easy to perform this automatically inside the ROM. (X1, X2, X3) and (Y1) as shown in (Table 2) and (Table 3) so that the additional data can be written.
, Y2) are established. (X1, X2, X3) and (Y1, Y2) shown in (Table 2) and (Table 3).
The relationship in parentheses) is one example and is not limited to this. Further, additional data can be written in the same manner even when the area is three or more.

FIG. 9A shows a data writing algorithm. After data loading, writing, verify reading, and writing end detection are repeatedly performed. The operation within the dotted line is performed automatically in the EEPROM.

FIG. 9B shows an additional data writing algorithm. After reading and data loading, verify reading, writing end detection, and writing operation are repeatedly performed. The operation within the dotted line is performed automatically in the EEPROM. The reason why the verify read is performed after the data load is to prevent the write from being performed where “1” or “2” has already been written.
Otherwise, overwriting may occur.

FIG. 10 shows the EEPR constructed as described above.
The write characteristics of the threshold value of the memory cell in the OM are shown. The memory cells to which "1" data is written and the memory cells to which "2" data are written are written at the same time, and the writing time is controlled independently. The following (Table 4) shows the potential of each part of the memory cell array at the time of erasing, writing, reading and verify reading.

[0057]

[Table 4]

FIG. 11 shows a specific configuration of the memory cell array 1 and the bit line control circuit 2 of the NOR cell type EEPROM according to the second embodiment of the present invention. A NOR type cell is constituted only by the memory cell M10. One end of the NOR type cell is connected to the bit line BL, and the other end is connected to a common ground line. The memory cells M sharing one control gate WL constitute a page. The memory cell M stores data at the threshold value Vt, “0” data when Vt is equal to or higher than Vcc, “1” data when Vt is equal to or lower than Vcc and 2.5 V or higher, and Vt is equal to or lower than 2.5 V and 0 V or higher. Is stored as "2" data. One memory cell has three states, and two memory cells can have nine combinations. Of these, using 8 combinations, 2
One memory cell stores data of 3 bits. In this embodiment, a set of two adjacent memory cells sharing a control gate stores 3-bit data.

Clock synchronous inverters CI5 and CI6
, CI7 and CI8 form flip-flops, respectively, and latch write / read data. They also operate as sense amplifiers. The flip-flop composed of the clock synchronous inverters CI5 and CI6 latches "whether to write" 0 "or" 1 "or" 2 "" as write data information, and the memory cell " Whether the information “0” is held or the information “1” or “2” is held ”is latched as read data information. The flip-flop composed of the clock synchronous inverters CI7 and CI8 latches "whether" 1 "write or" 2 "write" as write data information, and the memory cell is "2". Whether information is held or whether “0” or “1” is held ”is latched as read data information.

Of the n-channel MOS transistors, Qn
18 is a voltage V when the precharge signal PRE becomes “H”.
Transfer PR to bit line. Qn19 connects the bit line to the main bit line control circuit when the bit line connection signal BLC becomes "H". Qn20 to Qn23 and Qn25 to Qn28 are
The voltages VBLH, VBLM, and 0 V are selectively transferred to the bit lines according to the data latched in the flip-flop. Qn24 and Q29 are signals SAC2 and SAC, respectively.
When AC1 becomes "H", the flip-flop is connected to the bit line. Qn30 is provided for detecting whether or not all data of one page latched in the flip-flop is the same. Qn31, Qn32 and Qn33, Q
In n34, the column selection signals CSL1 and CSL2 become "H", respectively, to selectively connect the corresponding flip-flop to the data input / output lines IOA and IOB.

Next, the EEPROM constructed as described above will be described.
Will be described with reference to FIGS. 12 shows the timing of the read operation, FIG. 13 shows the timing of the write operation, and FIG. 14 shows the timing of the verify read operation.

The read operation is executed in two basic cycles. In the first read cycle, first, the voltage VPR becomes the power supply voltage Vcc, the bit line is precharged, and the precharge signal PRE becomes "L", and the bit line is floated. Subsequently, the control gate WL is set to 2.5 V
To be. Only when Vt of the selected memory cell is 2.5 V or less, that is, only when data “2” is written, the bit line goes to “L” level.

Thereafter, sense activation signals SEN2, SE
N2B is "L" and "H" respectively, and the latch activation signal LA
T2 and LAT2B become "L" and "H", respectively, and the flip-flop constituted by the clock synchronous inverters CI7 and CI8 is reset. The signal SAC2 becomes "H" and the clock synchronous inverters CI7 and CI7
8 and the bit line are connected. First, the sense activation signals SEN2 and SEN2B become "H" and "L", respectively, and the bit line potential is sensed. Then, the latch activation signals LAT2 and LAT2B becomes "H" and "L", respectively, and the clock synchronous inverter CI
7 and CI8 flip-flop,
Information “whether“ 2 ”data,“ 1 ”or“ 0 ”data” is latched.

The second read cycle is the same as the first read cycle, except that the voltage of the selection control gate WL is V instead of 2.5 V.
cc, the signals SEN2, SEN2B, LAT2, L
Instead of AT2B and SAC2, signals SEN1, SEN1B,
The difference is that LAT1, LAT1B, and SAC1 are output. Therefore, in the second read cycle, the information of "whether" 0 "data," 1 "or" 2 "data is latched in the flip-flop constituted by the clock synchronous inverters CI5 and CI6.

The data written in the memory cell is read by the two read cycles described above. Prior to data writing, the data in the memory cell is erased, and the threshold value Vt of the memory cell is higher than Vcc. Erasing is performed by setting the control gate WL to 20V and the bit line to 0V.

In the write operation, first, the precharge signal PRE becomes "L", and the bit line is floated. The signals VRFY1, VRFY2, FIM and FIL become Vcc. In the case of writing "2", since the data is latched in the flip-flop constituted by the clock synchronous inverters CI5 and CI6 so that the output of the clock synchronous inverter CI5 becomes "H", the bit line is 0V. In the case of "1" or "2" writing, the bit line is charged to Vcc.

Subsequently, the signals BLC, VRFY2, FI
M, FIL and voltage VSA are 10V, voltage VBLH is 8V, and voltage VBLM is 7V. In the case of writing "1", since the data is latched in the flip-flop constituted by the clock synchronous inverters CI7 and CI8 so that the output of the clock synchronous inverter CI7 becomes "H", the bit line BL Is applied with 7V. In the case of "2" write, the bit line is 8 V, and in the case of "0" write, 0 V
V. After this, the selected control gate WL becomes -12
V.

In the case of "1" or "2" writing, electrons are emitted from the charge storage layer of the memory cell due to the potential difference between the bit line BL and the control gate WL, and the threshold value of the memory cell decreases. In the case of "1" write, the amount of charge to be released from the charge storage layer of the memory cell must be reduced as compared with "2" write. It has eased to 19V. At the time of writing “0”, the threshold value of the memory cell is not effectively changed by the bit line voltage 0V.

After the write operation, the verify read is performed to check the write state of the memory cell and perform additional write only to the memory cell with insufficient write. During the verify read, the voltage VBLH is Vcc and FIM is 0V
It is.

The verify read is executed from two basic cycles. This basic cycle is similar to the second read cycle. The difference is that the selected control gate W
That is, the voltage of L and the signals VRFY1, VRFY2, and FIH are output (only VRFY1 in the first cycle of the verify read). The signals VRFY1, VRFY2,
FIH is output before the signals SEN1, SEN1B, LAT1, and LAT1B become "L", "H", "L", "H" after the control gate WL is reset to 0V. In other words, after the potential of the bit line is determined by the threshold value of the memory cell, but before the flip-flop constituted by the clock synchronous inverters CI5 and CI6 is reset. The voltages of the selected control gate WL are 2 V (first cycle) and 4 V corresponding to 2.5 V (first cycle) and Vcc (second cycle) at the time of reading.
(Second cycle) and lower to ensure a threshold margin.

Here, the clock synchronous inverter CI
5 and CI6, the data (data1) latched in the flip-flop comprised of the clock synchronous inverters CI7 and CI8, and the data (data2) latched in the flip-flop comprised of the inverters CI7 and CI8. The voltage of the bit line BL determined by the threshold will be described. data1 is “0” write or “1”
Or "2" write ", and in the case of" 0 "write, Qn20 is in the" ON "state, and in the case of" 1 "or" 2 "write, Qn23 is in the" ON "state. data2 controls “whether“ 1 ”write or“ 2 ”write”
In the case of "1" write, Qn26 is in "ON" state, "2"
In the case of writing, Qn27 is in the "ON" state.

In the first verify-read cycle when "0" data is written (initial write data is "0"), since the data of the memory cell is "0", even if the control gate WL becomes 2V, the bit line potential Remains "H". Thereafter, when the signal VRFY1 becomes "H", the bit line BL becomes "L".

In the first verify-read cycle when "1" data is written (initial write data is "1"), the threshold value of the memory cell is 2.5 V since the data of the memory cell should be "1". With the above, the control gate W
Even when L becomes 2V, the bit line potential remains "H". After that, the signal VRFY1 becomes "H", so that "1" has already been sufficiently written and data1 indicates "0" write, and the bit line BL becomes "L" ((2) in FIG. 14).
Otherwise, the bit line BL becomes "H" ((1) in FIG. 14).

In the first verify-read cycle when writing “2” data (initial write data is “2”), if the data of the selected memory cell is not “2” (“2” write is insufficient), control is performed. Gate WL is 2V
, The bit line potential is still "H" ((3) in FIG. 14).
). When "2" is sufficiently written in the selected memory cell, when the control gate WL becomes 2 V, the bit line potential becomes "L" by the memory cell ((4) (5) in FIG. 14).
FIG. 14 (5) shows a case where "2" has already been sufficiently written and data1 indicates "0" write. In this case, when the signal VRFY1 becomes "H", the bit line BL is grounded.

In the second verify-read cycle at the time of writing "0" data (initial write data is "0"), since the data of the memory cell is "0", even if the control gate CG4 becomes 4V, the bit line potential Is "H". Thereafter, when the signal VRFY1 goes "H", the bit line BL goes "L".

In the second verify-read cycle at the time of writing “1” data (initial write data is “1”), if the data of the selected memory cell is not “1” (“1” write is insufficient), control is performed. Gate WL is 4V
, The bit line potential is still "H" ((6) in FIG. 14).
). When "1" is sufficiently written in the selected memory cell, the bit line potential is set to "L" by the memory cell when the control gate WL becomes 4V ((7) (8) in FIG. 14). FIG. 14 (8) shows a case where "1" has already been sufficiently written and data1 indicates "0" write. In this case, when the signal VRFY1 becomes "H", the bit line BL is grounded.

In the second verify-read cycle when writing "2" data (initial write data is "2"), the data in the memory cell should be "2". If there is enough or insufficient writing of “2”, the bit line potential becomes “L” when the control gate WL becomes 4V ((10) (11) in FIG. 14).
When "2" is insufficiently written and the threshold value of the memory cell is 4 V or more, the bit line becomes "H" ((9) in FIG. 14).

Thereafter, the signals VRFY1, VRFY2, F
When IH becomes “H”, the bit line BL becomes “L” ((11) in FIG. 14) if “2” has already been sufficiently written and data1 indicates “0” write; otherwise, the bit line B
L becomes "H" ((9) (10) in FIG. 14).

By this verify read operation, the rewrite data is set as shown in Table 1 from the write data and the write state of the memory cell as in the first embodiment. Also, when data writing is sufficient in all memory cells, Qn30 in all columns is turned off,
Data write end information is output by the signal PENDB.

The data input / output operation timing, the data writing algorithm, the additional data writing algorithm, etc. are the same as those shown in FIGS. 7 to 9 and (Tables 2 to 3).
This is the same as the embodiment.

FIG. 15 shows the EEPR constructed as described above.
The write characteristics of the threshold value of the memory cell in the OM are shown. The memory cells to which "1" data is written and the memory cells to which "2" data are written are written at the same time, and the writing time is controlled independently. The following (Table 5) shows the potential of each part of the memory cell array at the time of erasing, writing, reading, and verify reading.

[0082]

[Table 5]

The circuits shown in FIGS. 3 and 11 can be modified as shown in FIGS. 16 and 17, for example. In FIG. 16, Qn3 and Qn4 shown in FIG. 3 are replaced by p-channel MOS transistors Qp1 and Qp2. FIG.
Qn22, Qn23, Qn25 to Qn28 in FIG. 1 are replaced by p-channel MOS transistors Qp3 to Qp8. By doing so, it is possible to prevent a drop in the transferable voltage due to the threshold value of the n-channel MOS transistor. In this example, it is sufficient to increase the voltage VSA to 8 V at the time of writing, thereby lowering the withstand voltage of the transistors constituting the circuit. be able to. VRFY1B in FIG. 16 is VRFY in FIGS.
The inverted signal of RFY1, VRFY2B, FILB,
FIMB is an inverted signal of each of VRFY2, FIL, and FIM in FIG.

In FIG. 8, writing of additional data has been described. For example, as shown in FIG. 18, dividing one page to facilitate writing of additional data is one effective method. In this example, one area is constituted by 22 memory cells for every 32 logical addresses. This makes it easy to write additional data in area units. That is, when additional data is written in the area 2, all the write data in the area other than the area 2 is set to “0”, and FIG.
This may be performed according to the data writing algorithm shown in FIG. The size of one area may be a size other than that shown in FIG. Further, a case where four or more write states are set in one memory cell is also possible according to the gist of the present invention.

[0085]

As described above, according to the present invention, three write states are set in one memory cell while an increase in circuit area is suppressed, and each write state of each memory cell is set. By independently performing the write verify control, the write time up to the end of the write operation can be independently optimized, and an EEPROM can be obtained in which the threshold distribution of the finally written memory cells can be quickly reduced to a small range. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an EEPROM according to first and second embodiments.

FIG. 2 is a diagram showing a specific configuration of a memory cell array in the first embodiment.

FIG. 3 is a diagram showing a specific configuration of a bit line control circuit according to the first embodiment.

FIG. 4 is a timing chart showing a read operation in the first embodiment.

FIG. 5 is a timing chart showing a write operation in the first embodiment.

FIG. 6 is a timing chart showing a verify read operation in the first embodiment.

FIG. 7 is a timing chart showing data input / output operations in the first and second embodiments.

FIG. 8 is a view showing the concept of a page of a write / read unit in the first and second embodiments.

FIG. 9 is a diagram showing a data write and additional data write algorithm in the first and second embodiments.

FIG. 10 is a diagram showing write characteristics of a memory cell in the first embodiment.

FIG. 11 is a diagram showing a configuration of a memory cell array and a bit line control circuit in a second embodiment.

FIG. 12 is a timing chart showing a read operation in the second embodiment.

FIG. 13 is a timing chart showing a write operation in the second embodiment.

FIG. 14 is a timing chart showing a verify read operation in the second embodiment.

FIG. 15 is a diagram showing write characteristics of a memory cell in the second embodiment.

FIG. 16 is a diagram showing a modification of the bit line control circuit in the first embodiment.

FIG. 17 is a diagram showing a modification of the bit line control circuit in the second embodiment.

FIG. 18 is a diagram showing units of additional data writing in the first and second embodiments.

FIG. 19 is a circuit diagram of an inverter part in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Bit line control circuit 3 ... Column decoder 4 ... Data write end detection circuit 5 ... Input / output data conversion circuit 6 ... Data input / output buffer 7 ... Word line drive circuit 8 ... Row decoder

Claims (21)

(57) [Claims] A memory cell array in which electrically rewritable memory cells are arranged in a matrix;
One memory cell is stored in a plurality of storage states of three or more and has arbitrary data “i” (i = 0, 1,..., N−1; n ≧ 3) and is multi-valued and stored as data “0”. The corresponding storage state is a nonvolatile semiconductor memory device in an erased state, in which a function of sensing data as a sense amplifier and data for controlling a write operation state of a plurality of memory cells in the memory cell array are used as sensed information. A plurality of data circuits having a function of storing; a write unit for performing a write operation according to the contents of the data circuit corresponding to each of the plurality of memory cells; and a state after the write operation of the plurality of memory cells I-th (i = 1, 2,..., N−1) write verifying means for checking whether or not the data is in a storage state of data “i”; Then, the contents of the data circuit are updated collectively for the data circuit corresponding to the memory cell to be data "i" so that rewriting is performed only for the insufficiently written memory cell from the state after the write operation of the memory cell. (I = 1, 2,..., N-1) data circuit content batch updating means, and a storage state check by the i-th write verification means and a batch update by the i-th data circuit content batch updating means With respect to data “1” to data “n−1”
And a data circuit content updating means for updating the contents of all the data circuits. The i-th data circuit content batch updating means outputs a state after the write operation of the memory cell by the i-th write verify means. Data "i" among the bit line potentials
The bit line potential corresponding to the memory cell to be set to (i ≧ 1) is sensed / stored as the rewrite data, and the bit line potential corresponding to the memory cell to be set to a state other than the data “i” indicates the content of the data circuit. The potential of the bit line from which the state after the write operation of the memory cell is output is corrected according to the contents of the data circuit so as to be sensed / stored so as to be held. The data circuit is operated as a sense amplifier while holding the storage state and the corrected bit line potential, and the contents of the data circuit are updated collectively for the memory cells corresponding to the data "i", A write operation based on the contents of the data circuit and an update of the contents of the data circuit are performed while repeating the plurality of memory cells until a predetermined write state is obtained. A nonvolatile semiconductor memory device electrically writing data. 2. The data circuit controls a write operation state of the memory cell according to data stored in the data circuit during a write operation, so that the state of the memory cell becomes a predetermined write state. Controlling whether to change the state of the memory cell or to maintain the state of the memory cell in the state before the write operation, and the i-th data circuit content batch updating means corresponds to the memory cell to be in the write state of data “i”. When the memory cell corresponding to the data circuit storing data for controlling the memory cell to change to the state of writing data "i" has reached the state of writing data "i", Changing the data in the data circuit to data for controlling the state of the memory cell to be maintained in a state before the write operation, If the memory cell corresponding to the data circuit in which the data to be controlled to change to the write state is not reached the write state of data "i", the state of the memory cell is changed to the write state of data "i". If data to be controlled to change to the state is set in the data circuit, and data to control to maintain the state of the memory cell in the state before the write operation is stored in the data circuit, the state of the memory cell is changed. Data to be controlled to be held in a state before the write operation is set in the data circuit, and the i-th data circuit content batch updating means includes a data circuit corresponding to a memory cell other than data "i" to be in a write state. 2. The non-volatile semiconductor memory device according to claim 1, wherein (i) is not changed. 3. The memory cell according to claim 1, wherein a charge storage layer and a control gate are stacked on a semiconductor layer, and an arbitrary data "i" (i = 0, 1,
, N−1; n ≧ 3) in a multi-valued manner with the magnitude of the threshold value. A predetermined i-th verify potential is applied to the control gate by the i-th write verify means, and the data “ i "
3. The non-volatile semiconductor memory device according to claim 2, wherein whether or not the threshold value of the memory cell to be brought into the state is a desired threshold value is verified. 4. A storage state corresponding to data "0" is an erased state, and a threshold value corresponding to the data "n-1" state is most different from a threshold value corresponding to the data "0" state. Are large, and data “1”, “2”, ，, “i”, ，, “n
The threshold value corresponding to the data "0" state is a value between the threshold value corresponding to the data "0" state and the threshold value corresponding to the data "n-1" state. , The threshold values corresponding to the data “1”, “2”,..., “I”,..., “N−2” states in order from the closest to the threshold value. The bit line potential at which the state after writing of the memory cell is output by
When the data circuit senses only the potential of a bit line corresponding to data whose contents are data for controlling the state of the memory cell to maintain the state of the memory cell before the write operation, the state of the memory cell is written. A first bit line potential setting circuit for setting a first correction bit line potential to be data to be controlled to maintain the previous state, wherein the i-th (1 ≦ i ≦ n−2) write verify The bit line potential corresponding to the memory cell to be in the data "j" (i + 1.ltoreq.j) state among the bit line potentials from which the state after the writing of the memory cell is output by the means is such that the content of the data circuit is the memory cell. When the data circuit senses only the bit line potential corresponding to the data which is controlled to change the state of the write data to the write state of the data “j”. A j-th bit line potential setting circuit for setting a second correction bit line potential to be data for controlling the state of the memory cell to be changed to a data “j” write state, In order to update the contents, the potential of the bit line from which the state after the write operation of the memory cell is outputted by the i-th write verify is changed according to the contents of the data circuit, by the first, i + 1, i + 2,. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the correction is performed by a line potential setting circuit. 5. A first data storage unit for storing, as information, whether or not to control to hold a state of a memory cell in a state before a write operation, and information of the first data storage unit. Is the information that is not controlled to hold the state of the memory cell in the state before the write operation, the write state “i” (i = 1, 2,.
A first data storage unit for storing information indicating 1), wherein the first data storage unit is adapted to update the data circuit contents, and the first, i + 1, i +
A function of sensing / storing the potential of the bit line output by the i-th write verify, the state after the write operation of the memory cell, corrected by the bit line potential setting circuits of 2, to n-1 The nonvolatile semiconductor memory device according to claim 4, wherein: 6. When the information in the first data storage section is information for controlling a state of a memory cell to be maintained in a state before a write operation, a write protection bit line voltage is output to a bit line during a write operation. In the case where the information in the write-prevention bit line voltage output circuit and the first data storage unit is information that is not controlled to hold the state of the memory cell in a state before the write operation,
The bit line voltage at the time of the ith write is output according to the information indicating the write state “i” (i = 1, 2,..., N−1) to be stored in the memory cell of the second data storage unit. 6. The nonvolatile semiconductor memory device according to claim 5, further comprising an i-th write bit line voltage output circuit. 7. A plurality of memory cells capable of electrically rewriting and having first, second, and third storage states,
A plurality of data circuits each provided for each of the memory cells and capable of storing first, second, and third control data for controlling a write voltage applied to each memory cell during data writing; The data circuit, when storing the first control data, does not detect a storage state of a corresponding memory cell, and stores the second control data. Only when the data is stored, it is detected whether the corresponding memory cell has reached the second storage state, and only when the third control data is stored, the corresponding memory cell is set to the third storage state. It is detected whether or not the first control data is stored, the first control data is stored, and the memory cell corresponding to the case where the second control data is stored is stored in the memory cell. In the second memory state If it is detected that the second control data is stored, the stored second control data is changed to the first control data, and the memory cell corresponding to the case where the third control data is stored is stored in the third storage state. And changing the stored third control data to the first control data when it is detected that the number has reached the maximum value. 8. A plurality of memory cells which can be electrically rewritten and have first, second, and third storage states,
A plurality of data circuits each provided for each of the memory cells and capable of storing first, second, and third control data for controlling a write voltage applied to each memory cell during data writing; The data circuit, when storing the first control data, does not detect a storage state of a corresponding memory cell, and stores the second control data. If the third control data is stored, it is detected only whether or not the corresponding memory cell has reached the second storage state. If the third control data is stored, the corresponding memory cell is in the third storage state. Only when the first control data is stored, the first control data is held, and the memory cell corresponding to the case where the second control data is stored is stored. Is the second memory state Is detected, the stored second control data is changed to the first control data, and the memory cell corresponding to the case where the third control data is stored is stored in the third storage data. The nonvolatile semiconductor memory device according to claim 1, wherein when it is detected that the state has been reached, the stored third control data is changed to the first control data. 9. write voltage applied to the memory cell corresponding to the data circuit for storing said first control data to claim 7 or 8, characterized in that to suppress writing to the memory cell 14. The nonvolatile semiconductor memory device according to claim 1. 10. A write voltage applied to a memory cell corresponding to a data circuit storing said second control data, and a write voltage applied to a memory cell corresponding to a data circuit storing said third control data. 9. The non-volatile semiconductor memory device according to claim 7 , wherein both of the applied write voltages promote writing to a memory cell. 11. A write voltage applied to a memory cell corresponding to a data circuit storing said second control data is applied to a memory cell corresponding to a data circuit storing said third control data. 9. The non-volatile semiconductor memory device according to claim 7 , wherein the applied write voltage is different from the applied write voltage. 12. Each of said data circuits comprises two C
9. The nonvolatile semiconductor memory device according to claim 7 , wherein said nonvolatile semiconductor memory device comprises a MOS flip-flop. 13. A control data detecting circuit for detecting whether or not all control data stored in said plurality of data circuits are said first control data. 9. The nonvolatile semiconductor memory device according to 7 or 8 . 14. The nonvolatile semiconductor memory device according to claim 7, wherein said memory cells store 3-bit data in pairs. 15. An electric rewriting method, comprising the steps of:
A plurality of memory cells capable of having a third storage state, and first and second storage circuits for storing data of a first logic level or a second logic level;
A data circuit provided for each of the memory cells, wherein the first storage circuit stores the data of the first logic level. When storing, suppresses writing to the corresponding memory cell, and when the first storage circuit stores data of the second logic level, facilitates writing to the corresponding memory cell; When the first storage circuit stores the data of the first logic level, the first storage circuit retains the stored first logic level, and the first storage circuit stores the data of the second logic level. And if the second storage circuit stores the data of the first logic level, it is detected whether the corresponding memory cell has reached the second storage state, and the second storage circuit Detected that state has been reached Changing the data of the second logic level stored in the first storage circuit to the data of the first logic level, wherein the first storage circuit stores the data of the second logic level When the second storage circuit stores the data of the second logic level, it is detected whether or not the corresponding memory cell has reached the third storage state, and the second storage circuit has reached the third storage state. Wherein the data of the second logic level stored in the first memory circuit is changed to the data of the first logic level. 16. The method according to claim 16, further comprising the steps of:
A plurality of memory cells capable of having a third storage state, and first and second storage circuits for storing data of a first logic level or a second logic level;
A data circuit provided for each of the memory cells, wherein the first memory circuit stores data of the first logic level. When storing, suppresses writing to the corresponding memory cell, and when the first storage circuit stores data of the second logic level, facilitates writing to the corresponding memory cell; When the first storage circuit stores the data of the first logic level, the first storage circuit holds the stored first logic level, and the first storage circuit stores the data of the second logic level. Only when the second storage circuit stores the data of the first logic level, it is detected whether or not the corresponding memory cell has reached the second storage state. Is the second theory. Detecting whether or not the corresponding memory cell has reached the third storage state only when the second memory circuit stores the data of the second logic level and stores the data of the second logic level; When the first storage circuit stores the data of the second logic level and the second storage circuit stores the data of the first logic level, a corresponding memory cell is stored in the second logic level. When it is detected that the storage state has been reached, the data of the second logic level stored in the first storage circuit is changed to the data of the first logic level, and the first storage circuit stores the data in the first storage circuit. If the second memory circuit stores the data of the second logic level and the second memory circuit stores the data of the second logic level, it is detected that the corresponding memory cell has reached the third storage state. Stored in the first storage circuit That said data of said second logic level first
A non-volatile semiconductor storage device, wherein the data is changed to data of a logic level of: 17. The method according to claim 17, further comprising the steps of:
A plurality of memory cells capable of having a third storage state, and first and second storage circuits for storing data of a first logic level or a second logic level;
A data circuit provided for each of the memory cells, wherein the first memory circuit stores data of the first logic level. When storing, suppresses writing to the corresponding memory cell, and when the first storage circuit stores data of the second logic level, facilitates writing to the corresponding memory cell; When the first storage circuit stores the data of the first logic level, the first storage circuit holds the stored first logic level, and the first storage circuit stores the data of the second logic level. And the second storage circuit stores the data of the first logic level, it detects only whether the corresponding memory cell has reached the second storage state, and Is the second theory. And when the second memory circuit stores the data of the second logic level, it detects only whether the corresponding memory cell has reached the third storage state, When the first storage circuit stores the data of the second logic level and the second storage circuit stores the data of the first logic level, a corresponding memory cell is stored in the second logic level. When it is detected that the storage state has been reached, the data of the second logic level stored in the first storage circuit is changed to the data of the first logic level, and the first storage circuit stores the data in the first storage circuit. If the second memory circuit stores the data of the second logic level and the second memory circuit stores the data of the second logic level, it is detected that the corresponding memory cell has reached the third storage state. Stored in the first storage circuit That said data of said second logic level first
A non-volatile semiconductor storage device, wherein the data is changed to data of a logic level of: 18. A write voltage applied to a memory cell corresponding to a data circuit in which the second storage circuit stores data of the first logic level, wherein the second storage circuit stores the second logic level in the second storage circuit. 18. The non-volatile semiconductor memory device according to claim 15 , wherein the write voltage is different from a write voltage applied to a memory cell corresponding to a data circuit storing data of the logical level. 19. The nonvolatile semiconductor memory according to claim 15 , wherein each of said first storage circuit and said second storage circuit comprises one CMOS flip-flop. apparatus. 20. A control data detection circuit for detecting whether or not all data stored in said first storage circuit is at said first logic level. 18. The nonvolatile semiconductor memory device according to any one of 15 to 17 . 21. The nonvolatile semiconductor memory device according to claim 15 , wherein said memory cells store 3-bit data in pairs.