JP3223402B2 - Burst signal detection circuit - Google Patents
Burst signal detection circuitInfo
- Publication number
- JP3223402B2 JP3223402B2 JP26313193A JP26313193A JP3223402B2 JP 3223402 B2 JP3223402 B2 JP 3223402B2 JP 26313193 A JP26313193 A JP 26313193A JP 26313193 A JP26313193 A JP 26313193A JP 3223402 B2 JP3223402 B2 JP 3223402B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- output
- burst
- burst signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、ディジタル無線通信に
おけるバースト信号検出回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst signal detecting circuit in digital radio communication.
【0002】[0002]
【従来の技術】図4は、従来のバースト信号検出回路を
示す図である。従来のバースト信号の検出は、一般的
に、バンドパスフィルタ等により所望の周波数帯域以外
の雑音が取り除かれた受信波中間周波数(IF)信号を
入力とする受信電界強度検出器(Recieved S
ignal Strength Indicator:
RSSI)80を用いて行われる。前記受信電界強度検
出器80は入力信号の電界強度をアナログ信号として出
力する。前記受信電界強度検出器出力を入力とする比較
回路90ではその大きさがあるスレッショルドと比較さ
れ、その値よりも大きい場合バースト信号を検出したも
のとしてバースト検出信号を出力する。2. Description of the Related Art FIG. 4 is a diagram showing a conventional burst signal detection circuit. In the conventional detection of a burst signal, generally, a reception field strength detector (Received S) receiving a reception wave intermediate frequency (IF) signal from which noise other than a desired frequency band has been removed by a band-pass filter or the like is input.
signal Strength Indicator:
(RSSI) 80. The reception field strength detector 80 outputs the field strength of the input signal as an analog signal. In the comparison circuit 90 which receives the output of the received electric field strength detector as an input, the magnitude is compared with a certain threshold. If the magnitude is larger than the threshold, a burst detection signal is output assuming that a burst signal has been detected.
【0003】[0003]
【発明が解決しようとする課題】従来技術で用いられる
受信電界強度検出器はアナログ素子であり、その他の比
較回路等もアナログ回路あるいはアナログディジタル変
換回路を用いた回路構成となり、小型化、無調整化の点
で不利である。さらに、従来の受信電界強度検出器を用
いた方法は、受信変調波の振幅情報を用いてバースト信
号を検出するため、干渉雑音等の混入信号を誤って検出
する場合がある。さらに、移動体通信用受信機でよく用
いられるリミタ等の振幅情報を欠落させる素子を通過し
た後にこの方法を用いることはできない。The receiving electric field strength detector used in the prior art is an analog element, and the other comparing circuits and the like also have a circuit configuration using an analog circuit or an analog-to-digital conversion circuit, so that they can be reduced in size and adjusted without adjustment. It is disadvantageous in terms of conversion. Further, in the conventional method using the reception electric field strength detector, since a burst signal is detected using amplitude information of a reception modulation wave, a mixed signal such as interference noise may be erroneously detected. Furthermore, this method cannot be used after passing through an element that lacks amplitude information such as a limiter often used in a mobile communication receiver.
【0004】本発明は、受信変調波の位相情報を用いて
バースト信号を検出するバースト信号検出回路を提供す
ることを目的とする。An object of the present invention is to provide a burst signal detection circuit for detecting a burst signal using phase information of a received modulated wave.
【0005】[0005]
【課題を解決するための手段】前記目的を達成するため
の本発明の特徴は、特定パターンをふくむ位相変調信号
を入力とし、その1シンボル時間遅延した信号との差分
をK回(Kは1以上の自然数)行なうK回差分回路と、
その出力を1シンボル時間遅延させる遅延回路の出力
と、前記K回差分回路の出力とを加算する加算回路と、
該加算回路の出力の絶対値をとる絶対値回路と、その出
力を一定時間累積加算する累積加算回路と、該累積加算
回路の出力が、所定の許容値より小さいときにバースト
信号検出信号を出力する比較回路とを有するバースト信
号検出回路にある。A feature of the present invention for achieving the above object is that a phase modulation signal including a specific pattern is input, and a difference from the signal delayed by one symbol time is K times (K is 1). A natural number) K-time difference circuit,
An adding circuit for adding an output of a delay circuit for delaying the output by one symbol time and an output of the K-th difference circuit;
An absolute value circuit for obtaining an absolute value of an output of the adder circuit, a cumulative adder circuit for cumulatively adding the output for a certain period of time, and outputting a burst signal detection signal when an output of the cumulative adder circuit is smaller than a predetermined allowable value. And a burst signal detection circuit having a comparison circuit.
【0006】[0006]
【作用】本発明は、従来のように振幅情報を用いるので
はなく位相情報を用いてバースト検出を行う。そのた
め、移動体通信用受信機でよく用いられるリミタ等の振
幅情報を欠落させる素子を通過した後の信号に対しても
本発明は適用でき、バースト検出回路がベースバンド帯
におけるディジタル回路により簡易に実現可能となる。
また、振幅情報を用いないので、干渉雑音等の混入信号
を誤って検出する確率は少なくなる。According to the present invention, burst detection is performed by using phase information instead of using amplitude information as in the prior art. Therefore, the present invention can be applied to a signal after passing through an element that lacks amplitude information, such as a limiter, which is often used in a mobile communication receiver, and the burst detection circuit can be simplified by a digital circuit in the baseband band. It becomes feasible.
Further, since the amplitude information is not used, the probability of erroneously detecting a mixed signal such as interference noise is reduced.
【0007】[0007]
【実施例】図1は、本発明実施例を示す図である。本発
明は受信波位相信号のK回差分信号が例えばサイン関数
のように周期信号となる場合に適用できる。ここでは、
バーストフォーマットとして図2に示したものを用い、
また、変調方式としてπ/4−シフトQPSK変調方式
が用いられた場合を例にとり説明する。FIG. 1 is a diagram showing an embodiment of the present invention. The present invention can be applied to a case where the K-time difference signal of the received wave phase signal is a periodic signal such as a sine function. here,
Using the burst format shown in FIG. 2,
Further, a case where a π / 4-shift QPSK modulation method is used as a modulation method will be described as an example.
【0008】本発明のバースト信号検出回路には受信変
調波位相信号が入力される。受信変調波位相信号は、例
えば、直交検波回路によりIチャネルおよびQチャネル
に分離されたベースバンド信号を位相情報(arcta
n(I/Q))が書き込まれたROMに入力することに
より容易に得られる。前記受信変調波位相信号はK回差
分回路(ここではK=2)に入力される。本実施例にお
いて図2に示したバーストフォーマットのプリアンブル
部における受信変調波位相信号が2回差分されて得られ
る信号を図3に示す。差分回数Kは、送信プリアンブル
パターンおよび変調方式を考慮し、図3に示すようK回
差分信号が周期信号となるように選ばれる。例えば、プ
リアンブルが「1001」のパターンをふくみ(π/
4)QPSK変調の場合はK=2が適当である。多くの
場合Kの値は2又は3以下となる。[0008] A received modulated wave phase signal is input to the burst signal detection circuit of the present invention. The received modulated wave phase signal is obtained, for example, by converting a baseband signal separated into an I channel and a Q channel by a quadrature detection circuit into phase information (arcta).
n (I / Q)) can be easily obtained by inputting it into the ROM in which it is written. The received modulated wave phase signal is input to a K-th difference circuit (here, K = 2). FIG. 3 shows a signal obtained by twice differentiating the received modulated wave phase signal in the preamble portion of the burst format shown in FIG. 2 in this embodiment. The number of times of difference K is selected in consideration of the transmission preamble pattern and the modulation scheme so that the K-time difference signal becomes a periodic signal as shown in FIG. For example, the preamble includes a pattern of “1001” (π /
4) For QPSK modulation, K = 2 is appropriate. In many cases, the value of K will be 2 or 3 or less.
【0009】つぎに、前記2回差分回路出力は加算回路
40に入力されるとともに、一方で遅延回路(1シンボ
ル時間遅延)30に入力される。加算回路40では、前
記2回差分回路出力と前記遅延回路の出力を加算し(図
3からもわかるように、前記加算回路出力値は雑音の無
い場合ゼロとなる)絶対値回路50へ入力される。絶対
値回路50では前記加算値の絶対値がとられ累積加算回
路60に入力される。前記累積加算回路60では、ある
一定時間にわたる累積加算値が求められる。前記累積加
算回路出力は比較回路70に入力されてそれが設定され
た許容値以下であればバースト検出信号を出力する。Next, the output of the two-time difference circuit is input to an adder circuit 40, while being input to a delay circuit (one symbol time delay) 30. In the adder circuit 40, the output of the two-time difference circuit and the output of the delay circuit are added (as can be seen from FIG. 3, the output value of the adder circuit becomes zero when there is no noise) and is input to the absolute value circuit 50. You. The absolute value circuit 50 takes the absolute value of the added value and inputs the absolute value to the cumulative addition circuit 60. The cumulative addition circuit 60 calculates a cumulative addition value over a certain period of time. The output of the accumulating circuit is input to a comparing circuit 70, and if it is equal to or less than a set allowable value, a burst detecting signal is output.
【0010】[0010]
【発明の効果】本発明は、従来のように振幅情報を用い
るのではなく位相情報を用いてバースト検出を行う。そ
のため、移動体通信用受信機でよく用いられるリミタ等
の振幅情報を欠落させる素子を通過した後の信号に対し
ても本発明は適用でき、バースト検出回路がベースバン
ド等におけるディジタル回路により簡易に実現可能とな
る。そのため、従来のアナログ回路を用いたバースト信
号検出器に比べ、無調整化、低消費電力化、および小型
化の点で有利である。また、干渉雑音等の混入信号を誤
って検出する確率が減少する。According to the present invention, burst detection is performed using phase information instead of using amplitude information as in the prior art. Therefore, the present invention can be applied to a signal after passing through an element that lacks amplitude information, such as a limiter, which is often used in a mobile communication receiver, and the burst detection circuit can be simplified by a digital circuit in baseband or the like. It becomes feasible. Therefore, it is advantageous in non-adjustment, low power consumption, and miniaturization as compared with a burst signal detector using a conventional analog circuit. Further, the probability of erroneously detecting a mixed signal such as interference noise is reduced.
【図1】本発明の一実施例を示す図。FIG. 1 is a diagram showing one embodiment of the present invention.
【図2】バーストフォーマット例を示す図。FIG. 2 is a diagram showing an example of a burst format.
【図3】2回差分信号を示す図。FIG. 3 is a diagram showing a differential signal twice.
【図4】従来例の示す図。FIG. 4 is a diagram showing a conventional example.
10−1,10−2 差分回路 20 減算回路 30 遅延回路(1シンボル時間) 40 加算回路 50 絶対値回路 60 累積加算回路 70,90 比較回路 80 受信電界強度検出器 10-1 and 10-2 Difference circuit 20 Subtraction circuit 30 Delay circuit (one symbol time) 40 Addition circuit 50 Absolute value circuit 60 Cumulative addition circuit 70, 90 Comparison circuit 80 Received electric field strength detector
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平5−110611(JP,A) 特開 平6−252965(JP,A) 特開 平4−68841(JP,A) 特開 平6−205062(JP,A) (58)調査した分野(Int.Cl.7,DB名) H04L 27/00 - 27/38 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-5-110611 (JP, A) JP-A-6-252965 (JP, A) JP-A-4-68841 (JP, A) 205062 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H04L 27/00-27/38
Claims (1)
力とし、その1シンボル時間遅延した信号との差分をK
回(Kは1以上の自然数)行なうK回差分回路と、 その出力を1シンボル時間遅延させる遅延回路の出力
と、前記K回差分回路の出力とを加算する加算回路と、 該加算回路の出力の絶対値をとる絶対値回路と、 その出力を一定時間累積加算する累積加算回路と、 該累積加算回路の出力が、所定の許容値より小さいとき
にバースト信号検出信号を出力する比較回路とを有する
ことを特徴とする、バースト信号検出回路。1. A phase modulation signal including a specific pattern is input, and a difference from a signal delayed by one symbol time is represented by K
A K-time difference circuit for performing the number of times (K is a natural number of 1 or more), an addition circuit for adding the output of the delay circuit for delaying its output by one symbol time, and the output of the K-time difference circuit; An absolute value circuit that takes an absolute value of the following, a cumulative addition circuit that cumulatively adds the output of the absolute value circuit for a certain period of time, and a comparison circuit that outputs a burst signal detection signal when the output of the cumulative addition circuit is smaller than a predetermined allowable value. A burst signal detection circuit, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26313193A JP3223402B2 (en) | 1993-09-28 | 1993-09-28 | Burst signal detection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26313193A JP3223402B2 (en) | 1993-09-28 | 1993-09-28 | Burst signal detection circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0799521A JPH0799521A (en) | 1995-04-11 |
JP3223402B2 true JP3223402B2 (en) | 2001-10-29 |
Family
ID=17385251
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26313193A Expired - Lifetime JP3223402B2 (en) | 1993-09-28 | 1993-09-28 | Burst signal detection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3223402B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106353591B (en) * | 2016-10-21 | 2023-05-16 | 成都前锋电子仪器有限责任公司 | Average burst power measuring circuit |
-
1993
- 1993-09-28 JP JP26313193A patent/JP3223402B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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JPH0799521A (en) | 1995-04-11 |
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