JP3216289B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bipolar transistor structure and a polysilicon structure having one or more layers and a method of manufacturing the same, and more particularly to improvement of a collector contact of a bipolar transistor.

[0002]

2. Description of the Related Art A semiconductor device having an npn transistor (80) and a p-channel MOS transistor (90) having a polysilicon emitter electrode structure and a method of manufacturing the same will be described with reference to FIG. The npn transistor (80) and the p-channel MOS transistor (90) are formed in an n-type epitaxial layer (74) formed on a p-type silicon substrate (70). It is formed in a p-well formed therein.

An n-type buried layer (72) is a p-type silicon substrate (7).
The antimony (Sb) is formed by selectively diffusing antimony (Sb) in a predetermined region of (0). Thereafter, an epitaxial layer (74) is formed on the entire surface, and boron (B) is selectively ion-implanted into a predetermined region to form a p-well. npn transistor (80)
Of the epitaxial layer (74) and the n-type buried layer (7
2), composed of a collector contact (82). In order to obtain a shallow emitter junction, the first polysilicon layer or the second polysilicon layer is used as an emitter electrode (86), and the base electrode (8
An emitter (88) is formed in 4).

The collector contact (82) is formed by masking a region other than the upper portion of the collector contact (82) with a resist, and implanting phosphorus with high energy and high dose.
Further, an npn transistor (80) formation region and a p-channel M
An isolation region that insulates and isolates the OS transistor (90) formation region
The pattern (98) is formed by masking a region except the upper part of the isolation region (98) with a resist and implanting boron ions with high energy and high dose. Since these collector contacts (82) and isolation regions (98) require high temperature treatment for annealing, they are formed relatively early in the manufacturing process so that the high temperature treatment does not alter the impurity distribution in other regions. Is done.

The gate (92) of the p-channel MOS transistor (90) is formed by patterning the first polysilicon layer formed on the entire surface, and the drain (94) and the source (96) are formed by n.
It is formed in a self-aligned manner by ion implantation of boron using a resist for masking a region for forming a pn transistor (80) and a region for forming a p-channel MOS transistor, a gate (92) and a field oxide film (76) as a mask.

A PSG is formed above the region where the npn transistor (80) and the p-channel MOS transistor (90) are formed.
(Phosphorus silicate glass) (88) is formed on the entire surface, a predetermined area is contact-opened, and an aluminum electrode (10) is formed.
Connected to 2). Bipolar transistor described above (80)
And the structure including the MOS transistor (90) is BiCM
Since it is called an OS and can operate at high speed, it is applied to a large-scale gate array and an SRAM.

[0007]

In the conventional semiconductor device, high-energy, high-dose ion implantation of 500 KeV to 1 MeV is required to obtain a low-resistance collector contact (82) reaching the buried layer (72). Therefore, it takes a long time for ion implantation of the collector contact (82), restrictions of ion implantation equipment, problems of silicon substrate damage, high temperature,
There are various problems such as a problem that requires a long-time annealing and an obstacle to miniaturization due to lateral diffusion of the collector contact (82). These problems also exist in the separation region.

In order to solve the above problem, it is possible to propose a method of forming a collector contact by applying a U-groove isolation region forming technique. However, according to this method, a new etching process is required. New problems, such as the problem of requiring a mask margin for an etching mask, and the like. Therefore, the object of the present invention is to achieve high precision,
It is an object of the present invention to provide a semiconductor device having a low-resistance collector contact, and to provide a semiconductor device manufacturing method capable of forming a collector contact with high accuracy without adding an etching process.

[0009]

According to a first aspect of the present invention, in a semiconductor device having a bipolar transistor structure and at least one polysilicon structure, the semiconductor device is formed above a buried layer by utilizing the patterning of the polysilicon layer. The main feature is that a collector contact is formed in the trench.
The invention of claim 3 is characterized in that a trench for a collector contact and a trench for an isolation region are formed simultaneously by utilizing patterning of a polysilicon layer.

The invention of claim 4 is characterized in that after forming an etching stopper for polysilicon etching at least in a region excluding the upper portion of the collector contact, the polysilicon layer is patterned to form a trench above the collector contact. And

[0011]

The collector contact is formed in the trench formed above the buried layer by utilizing the patterning of the polysilicon layer. The structure of claim 1 enables a low-resistance collector by low-energy, low-dose ion implantation. Along with
Thereby, the mask margin between the collector contact and the base region is reduced. According to the third aspect of the present invention, the trench for the collector contact and the trench for the isolation region are formed at the same time by using the patterning of the polysilicon layer, the mask margin of the collector contact and the isolation region is reduced.

The method according to claim 4, wherein after forming an etching stopper for polysilicon etching at least in a region excluding the upper portion of the collector contact, the polysilicon layer is patterned to form a trench above the collector contact. It can be controlled with high accuracy, and an etching process for forming a trench is not required. Further, a low-resistance collector can be realized by ion implantation with low energy and low dose.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention forms a trench above a buried layer by using patterning of a polysilicon gate of a MOS transistor, a polysilicon emitter electrode of a bipolar transistor, or polysilicon forming a load resistance of a memory cell. The main feature is that a collector contact of a bipolar transistor is formed in this trench. Accordingly, the semiconductor device of the present invention has a bipolar transistor structure and one or more polysilicon structures.

The present invention and one embodiment will be described below with reference to FIGS. In order to avoid complication, the n-type will be described as a first conductivity type and the p-type will be described as a second conductivity type.
FIG. 1 shows an npn transistor (30) and a p-channel MOS transistor (40) having a polysilicon emitter electrode structure.
The npn transistor (30) and the p-channel MOS transistor (40) are formed in an n-type epitaxial layer (14) formed on a p-type silicon substrate (10). It is formed in a P well formed therein. With such a BiCMOS structure, a high-speed gate array and SRAM can be obtained.

The collector of the npn transistor (30) comprises an epitaxial layer (14), an n-type buried layer (12), and a collector contact (38). For speeding up, the base (32) adopts a graft base structure as shown. Further, in order to obtain a shallow emitter junction, the first polysilicon layer or the second polysilicon layer is used as an emitter electrode (34), and the emitter (36) is formed by a low-temperature treatment in which the emitter electrode (34) is diffused and sourced. You.

The trenches (22) and (24) are a first polysilicon layer constituting the gate (42) of the p-channel MOS transistor (40), a polysilicon layer constituting the emitter electrode (34), and a memory. It is formed in a predetermined region of the silicon substrate (10) by using patterning of a polysilicon layer or the like constituting a load resistance of the cell. Although the embodiment uses the patterning of the polysilicon layer, the trenches (22) and (24) are formed by using a material having an etching rate equivalent to that of the silicon substrate (10), for example, patterning of silicide, polycide, or the like. Can also. Also, in consideration of the etchant and the etching stopper, it is possible to use the patterning of an element made of another material.

A collector contact (38) is formed by implanting phosphorus (P) ions or the like into a trench (22) formed above the buried layer (12), and an isolation region (52) is formed in the trench (24) by boron (P). B) It is formed by implanting ions. p-channel MOS
The source / drain (44) / (46) of the transistor (40) is formed of a resist for masking a region for forming an npn transistor (30) and a region for forming an n-channel MOS transistor, a gate (42), and boron for masking a field oxide film (18). It is formed in a self-aligned manner by ion implantation.

First, the semiconductor device of the present invention having the above-described structure has an advantage that a new etching process is not required because the trenches (22) and (24) are formed by using patterning of a polysilicon layer or the like. Have. Second, since the collector contact (38) is formed in the trench (22), there is an advantage that a low-resistance collector can be formed by ion implantation with low energy and low dose. Third, the annealing of the collector contact (38) can be performed in a relatively short time and at a low temperature, and the lateral diffusion of the collector contact (38) is small. This has the advantage that the mask margin and the mask margin between the collector contact (38) and the isolation region (52) are reduced.

Next, an example of the manufacturing method of the present invention will be described with reference to FIGS. (1) The surface of the p-type silicon substrate (10) is thermally oxidized to about 0.
A silicon oxide film having a thickness of 5 μm is formed, and a predetermined region (upper portion of the buried layer (12)) of the silicon oxide film is selectively removed by photolithography and silicon oxide film etching. Then, using this silicon oxide film as a mask, antimony (Sb) is diffused into the silicon substrate (10) to form an n-type buried layer (12).

An epitaxial layer (1) having a thickness of 1 μm to 2 μm is formed on a silicon substrate (10), and a p-well (not shown) is formed in a predetermined region of the epitaxial layer (14). A silicon nitride film (16) having a thickness of about 100 nm is entirely formed by the CVD method, and the silicon nitride film (16) on the field region is removed by photolithography and silicon nitride film etching. Then, this silicon nitride film (1
Using p) as a mask, boron ions are implanted to form a p-channel stopper (17). This p-channel may be formed by high energy ion implantation after forming the field oxide film. (See FIG. 2).

(2) Using the silicon nitride film (16) as a mask,
A silicon substrate (10) is thermally oxidized to form a field oxide film (18) having a thickness of about 400 nm. Then, the silicon nitride film (1
6) is peeled off to form a silicon oxide film (20) having a thickness of about 10 nm on the active region. The active region is masked with a first resist (26), and the silicon oxide film (20) in the region (22) for forming a collector contact and the region (24) for forming an isolation region is removed (see FIG. 3).

According to the present invention, the process of the first resist (26) and the silicon oxide film (20) in the region (22) where the collector contact is formed and the region (24) where the isolation region is formed
However, since the field oxide film (18) exists on both sides of the collector contact (38) and the isolation region (52), the mask alignment of the first resist (26) can be performed with low accuracy. Even if it is performed, the trenches (22) and (24) are formed with high precision. Further, since the silicon oxide film (20) is thin, the process is completed quickly. If this step is performed at the same time as the step of contacting the gate of the MOS transistor formation portion with the substrate (belid contact), no additional process is required.

(3) After removing the first resist (26), C
A first polysilicon layer having a thickness of about 100 nm is entirely formed by the VD method, and a gate (42) is formed by photolithography and polysilicon etching. At this time, the silicon oxide film (20) functions as an etching stopper, and the regions (22) and (2) where the silicon oxide film (20) has been removed in the previous process.
A trench having a depth of about 0.2 μm is formed in the silicon substrate (10) of (4) (hereinafter, the symbols used for those regions are used for the trench) (see FIG. 4).

(4) A portion other than the trench (22) is masked with a resist (50), and phosphorus is ion-implanted to form a collector contact (38).
Is formed (see FIG. 5). (5) The area other than the trench (24) is masked with a resist (52), and boron is ion-implanted to form an isolation region (54) (see FIG. 6). (6) After ion implantation of boron to form the base (32) of the npn transistor (30), the region where the npn transistor (30) is formed is masked with a resist (56), boron ions are implanted, and the p-channel MOS The drain (44) of the transistor (40)
Then, a source (46) is formed (see FIG. 7).

By this process, boron ions are implanted again into the isolation region (52), and the surface of the isolation region (52) is reduced in resistance. Thereafter, a predetermined region is masked with a resist, and arsenic ions are implanted to form an n-channel MOS (not shown).
Form the drain and source of the transistor.

(7) After forming a silicon oxide film (58) in the region where the p-channel MOS transistor (40) is formed, a predetermined region of the silicon oxide film (20) (on the emitter (36) of the npn transistor (30)) The hole is opened. About 100n by CVD method
A second polysilicon layer having a thickness of m is formed on the entire surface, and a polysilicon emitter electrode (34) is formed by photolithography in which arsenic is ion-implanted on the entire surface and polysilicon etching. By this polysilicon etching, the trench (22)
(24) is formed deeper. The emitter 36 of the npn transistor 30 is formed using the polysilicon emitter electrode 34 as a diffusion source (see FIG. 8).

(8) After this, PSG (phosphorus silicate
A glass (60) is formed on the entire surface, contacts are opened, and then an aluminum electrode (62) is formed to complete the semiconductor device having the structure shown in FIG. The example of the manufacturing method of the present invention has been described above. In addition, the first polysilicon layer and the silicon substrate
Trench (22) utilizing buried contact formation with (10)
(24) can be formed, and ion implantation for forming the collector contact (38) can be performed at any time.

Further, the polysilicon emitter electrode (34) of the npn transistor (30) can be formed simultaneously with the gate of the MOS transistor, or the emitter (36) can be formed by an n-channel MOS transistor.
It can also be formed by ion implantation for forming the drain and source of the S transistor. Furthermore, npn
Silicon oxide film (20) on base (32) of transistor (30)
Can be separately formed. Furthermore, a polycide structure can be employed for the gate of the MOS transistor. Furthermore, when the trenches (22) and (24) are formed at a high depth, the surface of the silicon substrate (10) can be planarized by burying polysilicon in the trenches (22) and (24).

[0029]

According to the present invention, a trench is formed above a buried layer using patterning of a polysilicon gate of a MOS transistor, a polysilicon emitter electrode of a bipolar transistor, or polysilicon forming a load resistance of a memory cell. According to the present invention in which a collector contact of a bipolar transistor is formed, a trench having an arbitrary depth can be formed without adding an etching process, and a collector having a low resistance can be formed by ion implantation with a low energy and a low dose. It has the advantage that it can be formed. In addition, the collector contact can be annealed in a relatively short time at a low temperature, and the lateral diffusion of the collector contact becomes small. Therefore, the mask margin between the collector contact and the base and the mask margin between the collector contact and the isolation region are reduced. It has the advantage of being reduced. Furthermore, since the trench is formed at the designed position with high precision, there is an advantage that the mask margin is further reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device for explaining a manufacturing process according to the embodiment.

FIG. 3 is a cross-sectional view of the semiconductor device for explaining a manufacturing process according to the embodiment.

FIG. 4 is a cross-sectional view of the semiconductor device for explaining the manufacturing process of the embodiment.

FIG. 5 is a cross-sectional view of the semiconductor device for describing a manufacturing process according to the embodiment.

FIG. 6 is a cross-sectional view of the semiconductor device for explaining a manufacturing process according to the embodiment.

FIG. 7 is a sectional view of the semiconductor device for illustrating the manufacturing process of the embodiment.

FIG. 8 is a cross-sectional view of the semiconductor device for explaining the manufacturing process of the example.

FIG. 9 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 12 buried layer 14 epitaxial layer 18 field oxide film 20 silicon oxide film 30 bipolar transistor 32 base 34 polysilicon emitter electrode 36 emitter 38 collector contact 40 MOS transistor 42 gate 44 drain 46 source 60 PSG 62 aluminum electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/06 H01L 21/8249 H01L 21/8222 H01L 29/732 H01L 21/331

Claims (5)

(57) [Claims] A second conductive type silicon substrate; a first conductive type buried layer formed in a predetermined region of the silicon substrate; a first conductive type epitaxial layer; A semiconductor device comprising: a bipolar transistor formed as described above; one or more polysilicon layers; a trench formed above a buried layer by using patterning of the polysilicon layer; and a collector contact formed in the trench. 2. The MOS transistor according to claim 1, wherein the gate of the MOS transistor is formed by the first polysilicon layer.
Semiconductor device. 3. The semiconductor device according to claim 1, wherein a trench for an isolation region is formed by utilizing patterning of a polysilicon layer. 4. A process of forming a buried layer of a first conductivity type in a predetermined region of a silicon substrate of a second conductivity type; a process of forming an epitaxial layer of a first conductivity type; A process of selectively forming an etching stopper for polysilicon etching on the surface of the epitaxial layer excluding the upper portion, one or more processes of forming a polysilicon layer on the entire surface, patterning the same, and forming a trench in the silicon substrate on the collector contact; A method for manufacturing a semiconductor device, comprising at least a process of implanting ions of a first conductivity type into a trench to form a collector contact. 5. The method of manufacturing a semiconductor device according to claim 4, wherein ions are simultaneously implanted into a collector contact when forming a drain and a source of an n-channel MOS transistor or an emitter of a bipolar transistor.