JP3216269B2 - Method for manufacturing thin film transistor array - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used for an active matrix type liquid crystal display or the like, and more particularly, to a polycrystalline Si layer laminated on a glass substrate which is doped with an impurity by an ion doping method. The present invention relates to a method for manufacturing a thin film transistor array which can prevent deterioration of characteristics of the thin film transistor and improve reliability when forming a plurality of thin film transistors.

[0002]

2. Description of the Related Art Conventionally, the formation of a C-MOS thin film transistor as shown in FIG. 4 has been performed by, for example, a manufacturing method including the following steps. An amorphous silicon (a-Si) film is deposited on a large-area glass substrate 51, and the a-Si film is crystallized.
A poly-Si film is formed. The poly-Si film is patterned to form a pair of poly-Si film islands 52. A gate insulating film 53 is deposited so as to cover the poly-Si film island 52. A metal film or a semiconductor film is deposited, and the metal film or the semiconductor film is patterned to form a gate electrode 54 on each poly-Si film island 52. An implantation mask made of a photoresist is formed so as to cover the poly-Si film island serving as the NMOS portion, and phosphorus ions are implanted from above. An implantation mask made of a photoresist is formed so as to cover the poly-Si film island serving as the PMOS portion, and boron ions are implanted from above. The dopant is activated by annealing. An insulating film 55 is deposited, and contact holes 56 are formed at source and drain electrode positions. After depositing an aluminum film and patterning it,
An l-electrode 57 is formed, a protective film 58 is further deposited, and a pad hole 59 is formed.

In the source / drain electrode forming step (and) according to the above-described manufacturing method, ion implantation is performed by scanning the substrate with an ion beam used in the LSI process, that is, an ion beam. It has been difficult to apply the method to an ion implantation method) for a glass substrate having a large area, for example, a square glass substrate having a side of 30 cm or more because the scanning area is small. Therefore, shower doping apparatuses have been developed in which ion implantation of dopants is performed without mass separation. The shower doping method can be applied to a glass substrate having a large area because it is sufficient to extract and accelerate ions from an ion source capable of irradiating the entire surface of the substrate. However, according to the shower doping method, a doping gas containing desired impurity ions is subjected to plasma discharge, and all the ion species generated by the discharge are accelerated at a high voltage and implanted into a substrate. Since the light is incident on the substrate, the incident energy on the substrate is increased as compared with the above-described ion implantation method. When a glass substrate is used in the shower doping method, the substrate cannot be sufficiently cooled due to the low thermal conductivity of the glass,
The substrate temperature at the time of implantation becomes high. Therefore, if photoresist is used as a mask material during doping,
In some cases, the film is deteriorated due to heat and cannot be peeled off.

[0004]

In order to perform doping without using a photoresist, as shown in FIG. 5, ions are directly implanted into the surface of the poly-Si film island 52 without passing through the gate insulating film 53. Accordingly, it is conceivable to perform doping with low acceleration energy such that the substrate temperature does not rise. In this case, since it is necessary to dope after removing the gate insulating film located on the source portion 52a and the drain portion 52b by etching, the side wall portion 53a of the gate insulating film 53 is formed at the end of the source portion 52a and the drain portion 52b. Will exist. Since the side wall portion 53a generated by the etching is rough, a leak current easily flows, which causes a problem that the breakdown voltage between the gate electrode 54 and the source portion 52a and the drain portion 52b is reduced.

On the other hand, in order to perform doping through an insulating film with high energy, as an example of using a material having heat resistance as a mask material instead of a photoresist, as shown in FIG. 6, a metal such as chromium (Cr) is used. It has been proposed that the film 55 be used as a mask material. However, when the metal film 55 is used as a mask material, the metal mask material itself has a masking effect on doping ions, but the metal mask material itself collides with the doping ions to form the gate insulating film 53 serving as a base material.
There is a problem that the impurities are implanted into the inside and become impurities, which deteriorates the transistor characteristics due to a long-time bias stress or the like and leads to a decrease in reliability.

Therefore, as a mask material which does not become an impurity of the gate insulating film as a base material and has heat resistance, FIG.
As shown in FIG. 5, a Si-based inorganic film 5 such as Si ₃ N ₄ or SiO ₂
It is possible to use 6 as a mask material. However, when the Si-based inorganic film 56 is used as a mask material, when the film is removed by etching after doping, the gate insulating film (SiO ₂ ) 53 as a base material and the poly-Si Melting point metal (W, Mo, Ti, Ta
And their alloys), it was difficult to selectively etch poly-Si and silicide with these metals.

For example, when a Si ₃ N ₄ film 56 is used as a mask material, when this film is dry-etched with an F-based gas such as SF ₆ or CF ₄ , the po
The ly-Si film, silicide or refractory metal is also etched. When wet etching is performed using an HF system, SiO ₂ that is the gate insulating film 53 is simultaneously removed by etching. The same applies to the case where an SiO ₂ film is used as a mask material.

As described above, when an impurity is doped into a polycrystalline Si layer laminated on a glass substrate by an ion doping method, there is no problem in reliability and characteristic deterioration by using a mask material having heat resistance, and There was no method with sufficient workability. The present invention has been made in view of the above circumstances, and can prevent deterioration of characteristics of a thin film transistor and improve reliability when a plurality of thin film transistors are formed on a substrate by doping impurities by an ion doping method. An object of the present invention is to provide a method for manufacturing a thin film transistor array.

[0009]

[MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
The method of the present invention comprises the step of adding a p-type dopant to an island-shaped polycrystalline Si layer.
Impurity by ion doping method
P-channel type thin film transistor as source and drain
And an island-shaped polycrystalline Si layer different from the polycrystalline Si layer
Doping with impurities as n-type dopants
N-channel which is doped with
A method of manufacturing a thin film transistor array having a tunnel type thin film transistor includes the following steps. As a first step, each thin film transistor is placed on a substrate .
After stacking a polycrystalline Si layer corresponding to the transistor , a gate insulating film, and a gate electrode, an etching stopper layer covering the entire surface of the substrate is formed. As the second step, p channel
The etching stopper layer and the etching rate differs form the first mask layer to prevent doping of ions in the etching stopper layer on the portion to be the Le-type thin film transistor. As a third step, the polycrystalline Si layer that is not covered with the first mask layer is ion-doped with an impurity that gives an n-channel type. As a fourth step, the first mask layer is removed. As the fifth step, n channels
The etching stopper layer and the etching rate varies to form a second mask layer to prevent doping of ions in the etching stopper layer on the portion to be the Le-type thin film transistor. In a sixth step, a p-channel type is given to the polycrystalline Si layer not covered with the second mask layer.
The impurities are ion-doped . In a seventh step, the second mask layer is removed. In addition, a p-channel thin film transistor
The order of manufacturing transistors and n-channel thin film transistors
It may be reversed. That is, the method of the present invention
Doping impurities as p-type dopants into the crystalline Si layer
Doping by ping method to form source and drain
P-channel thin film transistor and the polycrystalline Si layer
In addition to the island-shaped polycrystalline Si layer,
Source portion by doping impurities in the ion doping method
And an n-channel thin film transistor as a drain portion
In the method for manufacturing a thin film transistor array having
A polycrystalline Si layer corresponding to each thin film transistor on a substrate,
After laminating gate insulating film and gate electrode, the entire substrate
Forming an etching stopper layer covering the substrate;
Etching of a portion to be a channel type thin film transistor
Etching stopper layer and etchant on stopper layer
The first of the different grades to prevent ion doping
Forming a mask layer; and covering the first mask layer with the mask layer.
Impurity that gives a p-channel type to a polycrystalline Si layer
A first ion doping step of doping;
A first removing step of removing the one mask layer, and a p-channel
Type etching thin film
The etching stopper layer and the etching layer
A second mask for preventing doping of ions which is different from the first mask
Forming a layer and not covering with the second mask layer.
Ions that give the n-channel type to the polycrystalline Si layer
A second ion doping step of doping;
And a second removing step of removing the mask layer.
It is characterized by.

[0010]

According to the method of the present invention, when the polycrystalline Si layer is doped with an impurity by the ion doping method, there are a portion covered with the etching stopper layer and a portion covered with the etching stopper layer and the mask layer. Will be.
Therefore, ion implantation into the polycrystalline Si layer located below the portion covered by the etching stopper layer and the mask layer is prevented by the mask layer. Further, ions are implanted into the polycrystalline Si layer located below the portion covered only by the etching stopper layer through the etching stopper layer. Since the etching rate of the mask layer is different from that of the etching stopper layer, the gate electrode and the gate insulating film located below the etching stopper layer can be protected when the mask layer is removed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method of manufacturing a C-MOS thin film transistor according to the present invention will be described with reference to FIGS. As a structure of the TFT, an insular polysilicon layer corresponding to each TFT is patterned by depositing poly-Si on an insulating substrate 1 made of glass or quartz or the like using the most common planar structure. 2
Is formed (FIG. 1A). The poly-Si film is formed by, for example, amorphous Si (hereinafter a-Si) by LPCVD.
Is deposited and then annealed with an excimer laser to crystallize. The deposition and annealing conditions are SiH
₄ Gas flow rate: 100 sccm, gas pressure: 0.5 Torr
r, substrate temperature: 500 ° C., film thickness: 1000 Å, laser power: 450 mJ / cm ² . As an annealing method, furnace annealing may be used, or poly-Si may be directly deposited.

Next, a gate insulating film 3 is formed by depositing SiO ₂ by ECRCVD. The deposition condition is SiH
₄ / N ₂ O gas flow rate: 10 sccm / 200 sccm, gas pressure: 5 × 10 ⁻³ Torr, discharge power: 100 W,
Film thickness: 1000 angstroms. LPCVD, plasma CV, besides ECRCVD
D, may be performed by a sputtering method or the like.

Subsequently, poly-Si is deposited by the LPCVD method and then patterned to form a gate electrode 4 at a position corresponding to each island-shaped polysilicon layer 2 (FIG. 1).
(B)). The deposition conditions are as follows: SiH ₄ gas flow rate: 200 sc
cm, gas pressure: O.C. 5 Torr, substrate temperature: 500
° C, film thickness: 3000 angstroms. As the gate electrode material, in addition to poly-Si, W, which is a refractory metal,
Mo, Ti, Ta and their alloys, and these metals
Poly-Si silicide or the like may be used.

Thereafter, ion doping is performed in order to form a source portion and a drain portion in each island-shaped polysilicon layer 2. In the case of a C-MOS, n-type and p-type are used.
Both types of ions need to be doped. In this embodiment, after doping P (phosphorus) ions as an n-type dopant, B (boron) ions are doped as a p-type dopant. The doping order of both the n-type and p-type ions may be reversed. When performing doping, first, SiO ₂ is deposited by a plasma CVD method to form an etching stopper layer 5 covering the entire surface of the insulating substrate 1. The deposition conditions were as follows: SiH ₄ / N ₂ O gas flow rate: 25 sccm / 250 sccm, gas pressure: O.D. 2
Torr, substrate temperature: 350 ° C., discharge power: 100
W, film thickness: 200 angstroms. This etching stopper layer 5 is a layer formed on the etching stopper layer 5 (a mask layer 6 or a mask layer 7 described later).
It is necessary to secure a film thickness and a film quality enough to function as an etching stopper when etching the film. In addition, when doping P ions or B ions in a later step, ions are implanted into the underlying island-shaped polysilicon layer 2 through the etching stopper layer 5, so that from this point, the thinner is preferable. To satisfy both of these conditions, the thickness of the etching stopper layer 5 is set to 100 to
Around 200 Å is considered appropriate.

Next, a mask layer 6 covering the etching stopper layer 5 is formed by depositing Si ₃ N ₄ by a plasma CVD method (FIG. 1C). The deposition conditions were as follows: SiH ₄ gas flow rate: 50 sccm / 300 sccm, gas pressure:
O. 3 Torr, substrate temperature: 350 ° C., discharge power: 1
00 W, film thickness: 3000 angstroms. At this time, the total film thickness of the two layers of the mask layer 6 and the etching stopper layer 5 needs to be sufficient to function as a mask when implanting P ions in the next step. The thickness of the mask layer 6 depends on the thickness of the gate insulating film 3 and the ion implantation depth.
It is preferable that the film thickness be 2000 Å or more so that the film can be sufficiently prevented even when accelerated at about 0 kV. When removing the mask layer 6 by etching, it is not preferable to increase the thickness of the mask layer 6 more than necessary so as not to scrape the lower etching stopper layer 5 formed of SiO _2. . Therefore, it is considered that the appropriate thickness of the mask layer 6 is 2000 to 4000 angstroms. As a material of the mask layer 6, other than the above-mentioned Si ₃ N ₄ , a material having a high etching selectivity with respect to the etching stopper layer (SiO ₂ ) 5, for example, SiON may be used. As a method of depositing the mask layer 6, a sputtering method or an ECRCVD method may be used instead of the plasma CVD method.

Next, the mask layer (Si ₃ N ₄ ) 6a corresponding to the n-channel portion for doping with P ions is removed by patterning by etching (FIG. 1D).
The pattern formation of the mask layer 6b is performed using ordinary photolithography, and the etching is performed by a dry etching method using an F-based gas. The etching conditions are SF ₆ / C ₂
ClF ₅ gas flow rate: 50 sccm / 100 sccm, gas pressure: 50 mTorr, discharge power: 400 W. Under the above conditions, the mask layer 6 and the etching stopper layer 5
Is 100 or more, and the problem of a decrease in the etching stopper layer 5 does not occur.

Subsequently, P ions are implanted into the island-shaped polysilicon layer 2 corresponding to the n-channel portion by an ion doping method to form a source portion 11 and a drain portion 12 (FIG. 2A). Since the implantation of P ions results in doping through the gate insulating film 3 and the etching stopper layer 5, it is necessary to set a higher acceleration voltage during doping. The doping conditions are PH ₃ / H ₂ gas flow rate:
5 sccm / 100 sccm, gas pressure: 5 mTorr
r, discharge power: 100 W, acceleration voltage: 100 kV, and dose: 5 × 10 ¹⁵ ions / cm ² . When doping is performed under these conditions, the substrate temperature rises to about 300 degrees due to the energy of P ions and H ions, but the mask layer 6
Since Si ₃ N ₄ , which is not an inorganic masking material, is used as the material b, the mask layer 6 b is prevented from being deteriorated at high temperatures. Further, ion implantation into the island-shaped polysilicon layer 2 located below the portion covered with the mask layer 6b is prevented by the mask layer 6b. After the doping, the mask layer 6b is removed by etching. The etching method is the same as the condition described above.

Next, as a masking material at the time of B ion doping, Si ₃ N ₄ is deposited by a plasma CVD method, and a mask layer 7 covering the etching stopper layer 5 is formed again (FIG. 2B). The deposition conditions are the same as those for forming the mask layer 6. However, since the B ions are lighter ions than the P ions, the acceleration voltage at the time of doping can be reduced, so that the thickness of the mask layer 7 can be reduced. In this embodiment, the thickness is set to 1000 Å. . Next, a mask layer (Si ₃
N ₄ ) 7a is removed by patterning by etching (FIG. 2C). The pattern formation of the mask layer 7b is performed by ordinary photolithography, and the etching is performed by a dry etching method using an F-based gas under the same etching conditions as described above.

Subsequently, B ions are implanted into the island-shaped polysilicon layer 2 corresponding to the p-channel portion by the ion doping method to form the source portion 11 and the drain portion 12 (FIG. 3A). The doping conditions are as follows: B ₂ H ₆ / H ₂ gas flow rate: 5 sccm / 100 sccm, gas pressure: 5 mT
orr, discharge power: 100 W, acceleration voltage: 70 kV,
Dose amount: 5 × 10 ¹⁵ ions / cm ² . In this doping, the mask layer 7b does not deteriorate as in the above-described doping. Further, ion implantation is prevented by the mask layer 7b into the island-shaped polysilicon layer 2 located below the portion covered by the mask layer 7b. After the doping, the mask layer 7b is removed by etching (FIG. 3B). The etching method is the same as the condition described above. Through the above steps, doping of the source portion and the drain portion when forming n-channel and p-channel TFTs on the same insulating substrate 1 can be performed. continue,
Activation of the doped ions is performed by furnace annealing or laser annealing. For example, 500 degrees, 3
Activation of ions is performed by furnace annealing for a long time.

Next, by a normal transistor fabrication process, a SiO 2 film is deposited as an interlayer insulating film, a contact hole is formed, an Al film is deposited and patterned as an electrode material, and a Si ₃ N ₄ film is formed as a passivation film. A C-MOS thin film transistor is completed by depositing and patterning (not shown) and, if necessary, hydrogen plasma treatment for improving characteristics such as hydrogenation.

According to the present embodiment, the island-shaped polysilicon layer 2, the gate insulating film 3, and the gate electrode 4 laminated on the insulating substrate 1 are formed by the etching stopper layer 5 and the mask layer 6.
(7), the mask layer 6 (7) is formed of a Si-based inorganic film, so that sufficient heat resistance is ensured when the island-shaped polysilicon layer 2 is doped with impurities by ion doping. Since the etching rate of the mask layer 6 (7) is different from that of the etching stopper layer 5,
When the mask layer 6 (7) is removed, the gate electrode 4 and the gate insulating film 3 located below the etching stopper layer 5 are protected, TFT characteristics are prevented from deteriorating, and reliability can be improved. .

[0022]

According to the method of the present invention, the mask material covering the island-shaped polysilicon layer, the gate insulating film and the gate electrode laminated on the substrate is provided with an etching stopper layer and an etching rate different from that of the etching stopper layer. Since the island-shaped polysilicon layer is doped with impurities by the ion doping method, it is possible to secure sufficient heat resistance to the mask layer because the mask layer is formed by the mask layer that prevents ion doping. At the time of removal, the gate electrode and the gate insulating film located below the etching stopper layer are protected, and deterioration of TFT characteristics can be prevented to improve reliability.

[Brief description of the drawings]

1 (a) to 1 (d) show C by the method of the present invention.
FIG. 4 is a manufacturing process diagram showing a method for manufacturing a MOS thin film transistor.

FIGS. 2 (a) to 2 (c) show C by the method of the present invention.
FIG. 4 is a manufacturing process diagram showing a method for manufacturing a MOS thin film transistor.

FIG. 3 (a) and (b) show C-
It is a manufacturing process figure showing the manufacturing method of the MOS thin film transistor.

FIG. 4 is an explanatory sectional view showing a structure of a conventional C-MOS thin film transistor.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing a conventional C-MOS thin film transistor.

FIG. 6 is a cross-sectional view illustrating a method for manufacturing a conventional C-MOS thin film transistor.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a conventional C-MOS thin film transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Island-like polysilicon layer, 3 ... Insulating film, 4 ... Gate electrode, 5 ... Etching stopper layer, 6, 7 ... Mask layer, 11 ... Source part, 12 ... Drain part

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/08 331 H01L 21/265 F 27/092 27/08 321E (58) Investigated field (Int.Cl. ⁷ , DB name ) H01L 29/786 H01L 21/265 H01L 21/266 H01L 21/336 H01L 21/8238 H01L 27/08 331 H01L 27/092

Claims (2)

(57) [Claims] A p-type dopant is added to an island-like polycrystalline Si layer.
All impurities by ion doping
P-channel type thin film transistor as source and drain
And an island-shaped polycrystalline Si layer separate from the polycrystalline Si layer.
Impurity as n-type dopant by ion doping method
N channel doped as source and drain
A method of manufacturing a thin film transistor array having a thin film transistor , comprising: a polycrystalline Si layer corresponding to each thin film transistor on a substrate;
A step of forming an etching stopper layer covering the entire surface of the substrate after laminating a gate insulating film and a gate electrode; and doping ions on the etching stopper layer in a portion to be a p-channel thin film transistor with a different etching rate from the etching stopper layer. forming a first mask layer to prevent, n Ji polycrystalline Si layer that is not covered by the first mask layer
A first ion doping step of doping an impurity giving a channel type; a first removing step of removing the first mask layer; and an etching stopper layer on a portion of the etching stopper layer to be an n-channel thin film transistor Forming a second mask layer having different etching rates and preventing ion doping, and forming a p-type layer on the polycrystalline Si layer not covered with the second mask layer.
A method for manufacturing a thin film transistor array, comprising: a second ion doping step of ion doping an impurity giving a channel type; and a second removing step of removing the second mask layer. 2. The method according to claim 1, wherein the p-type dopant is added to the island-like polycrystalline Si layer.
All impurities by ion doping
P-channel type thin film transistor as source and drain
And an island-shaped polycrystalline Si layer separate from the polycrystalline Si layer.
Impurity as n-type dopant by ion doping method
N channel doped as source and drain
Thin film transistor array having
In the manufacturing method of b, A polycrystalline Si layer corresponding to each thin film transistor on a substrate,
After laminating gate insulating film and gate electrode, the entire substrate
Forming an etching stopper layer covering The etch of a portion to be an n-channel thin film transistor
The etching stopper layer and the etching stopper layer.
Ching rate is different to prevent ion doping
Forming a first mask layer; The polycrystalline Si layer not covered with the first mask layer
First ion for doping an impurity giving a channel type
A doping process; A first removing step of removing the first mask layer; The etch of a portion to be a p-channel thin film transistor
The etching stopper layer and the etching stopper layer.
Ching rate is different to prevent ion doping
Forming a second mask layer; The polycrystalline Si layer not covered with the second mask layer
Second ion for ion doping an impurity giving a channel type
Doping process; A second removing step of removing the second mask layer; Of a thin film transistor array characterized by comprising:
Production method.