JP3211882B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a means for relieving a memory cell defect.

[0002]

2. Description of the Related Art In a semiconductor memory device such as a DRAM, a memory cell is provided at each intersection of a plurality of bit line pairs and a plurality of word lines. A word line is selected by a row address, and a bit line pair is selected by a column address. Is selected, the storage information of the target memory cell can be read.

In a conventional semiconductor memory device such as a DRAM, a method of dividing a storage area into a plurality of blocks due to an increase in storage capacity and a limitation on the length of a bit line pair is used.

In order to read storage information stored in a memory cell of a semiconductor memory device having a plurality of blocks, it is necessary to specify a row address, a column address, and a block address. There is. Then, after an address is specified, various operations such as writing and reading of data are performed by receiving a command from the outside.

However, even if the semiconductor memory device is composed of a plurality of blocks as described above, if the processing of another block cannot be performed while the processing of a certain block is being performed, the storage capacity increases. As the number of blocks increases, it takes a long time to read stored contents.

In order to solve this problem, a synchronous DRAM or the like is used in which memory cells are not divided into a plurality of blocks but are divided into banks which can operate independently of each other. .

In each bank, a memory cell group designated by an externally input address signal is activated. At this time, each bank can be in the activated state at the same time, and the addresses of the activated memory cells are independent between the banks.

FIG. 22 shows a configuration of a conventional semiconductor memory device including such a plurality of banks.

FIG. 22 is a block diagram showing the configuration of a conventional semiconductor memory device having such a bank configuration, and FIGS. 23A and 23B are timing charts showing the operation. FIG. 23A shows a case where a redundant memory cell is selected, and FIG. 23B shows a case where a redundant memory cell is not selected.

Here, the number of banks is represented by bank A (ARRA).
Y0), 2 of bank B (ARRAY1), and 4 subarrays constituting each bank (SA00 to SA0, respectively)
3, SA10 to SA13), and the description will be made assuming that 512 subword lines are included in each subarray, not shown. Also,
Here, description will be made using a hierarchical word line structure. At this time, there are eight sub-word lines for one main word line MWL. Therefore, the row address of each bank is 11 bits (X0 to X10), of which the subarrays are X9 and X10, the main word lines in the subarray are X3 to X8, and eight subwords for one main word line. They are distinguished by lines X0 to X2.

Replacement of a defective memory cell with a redundant memory cell is performed for two row addresses identified by X0. Each sub-array has one redundant main word line R
It has MWL and eight sub-word lines connected to it.

The operation will be described below with reference to a circuit diagram and a timing diagram. AC of FIGS. 23 (a) and 23 (b)
T is a signal indicating that the bank is in an activated state, and operates in response to an external command input by a command decoder or the like not explicitly shown in the figure.

In FIG. 22, an XAD consisting of 11 bits
D is a row address signal, which is taken in from the outside according to the ACT signal by an address buffer or the like not explicitly shown in the figure. XABF is a row address signal buffer circuit.
According to X10, complementary signals X1N to X10N, X1
Generate T to X10T. Each redundant decoder XRED is
This circuit stores defective addresses to be replaced, and stores / compares defective addresses.

FIG. 24 shows such a redundant decoder XRED.
FIG. 3 is a circuit diagram showing an example of the embodiment. The redundancy decoder XRED compares the row address signal XADD with a defective address stored therein.

In this conventional semiconductor memory device, the row address signal XAD
X1 to X10 constituting D are stored. The sub-word lines distinguished by X0, for example, row address 0 and row address 1 are not distinguished in the redundancy decoder XRED, and it is understood that whichever is input is a defective address.

In this circuit, the replacement address is stored by cutting fuses F1N to F10N and F1T to F10T. The method of cutting the fuse is not particularly limited, but is generally blown by a laser beam.
One of FnN and FnT is disconnected, and one bit of the replacement address is stored. For example, if the replacement addresses are 0 and 1, F1N to F10N are disconnected, and F1T to F10T are not disconnected.

Hereinafter, the operation of the redundant decoder XRED will be described. First, the row address signals XADD all go low, the redundant precharge signal PXR goes low, and the node 100 goes high. Subsequently, based on an externally input address signal, a row address signal XA
X1N to X1 of the 11-bit complementary signals constituting the DD
0N and X1T to X10T are set. At this time, since XnN and XnT (n = 1 to 10) are complementary signals, one becomes high level and the other becomes low level. For example, if the row address is 0 or 1, X1N to X1
0N is at a high level, and X1T to X10T are at a low level. Therefore, the nodes 100 and 101 are conductive except when the replacement address stored in the fuses FnN and FnT matches the row address signal XADD.

Here, the redundant precharge signal PXR goes high, and the replacement address and the row address signal XAD
If D does not match, node 100 goes low,
When they match, the high level is held. This is held at the node 102 by the latch signal XLAT and is output as the defective address match signal XREBL. When the ACT signal becomes low level, all the defective address match signals XREBL are deselected by the XPRE signal, and as a result, the selected redundant memory cell is also deselected.

FIG. 25 is a circuit diagram showing an example of a redundant memory cell selection circuit XRDN. The redundant memory cell selection circuit XRDN includes a redundant row decoder R
There is a one-to-one relationship with XDC. Redundant decoder XRE
Since one D exists for two sub-word lines, one redundant memory cell selection circuit XRDN exists for four redundant decoders XRED. This ratio is the ratio between the number of main word lines and the number of sub word lines. The redundant memory cell selection circuit XRDN is connected to the four defective address match signals X
When one of the REBLs goes to a high level, the redundant replacement selection signal XRDNS, which is at a high level by a precharge circuit not specifically shown in the figure, is pulled down to a low level. The redundant replacement selection signal XRDNS is a signal indicating that a redundant memory cell has been selected. Further, the redundancy decoder selection signal RXDS is set to high level,
To activate the redundant row decoder RXDC connected to.

Further, redundant sub-word line selection signals RRAIS1 and RRAIS2, which are at a high level by a precharge circuit not explicitly shown in the figure, are selectively dropped to a low level by a defective address match signal XREBL. Four connected defective address match signals XRE
When the XREBL0 of the BLs goes to the high level, it is not dropped to the low level, but the XREBL1
Becomes high level, only RRAIS1 and XRE
When BL2 goes high, only RRAIS2,
When XREBL1 becomes high level, both redundant sub third line selection signals RRAIS1 and RRAIS2 are dropped. Therefore, the redundant decoder XRED
And the state of the redundant sub third line selection signal RRAIS signal when the comparison result matches is fixed.

The redundancy decoder XRED and the redundancy memory cell selection circuit XRDN have fixed banks to which they belong, and operate only when the bank is selected. Further, the redundant precharge signal PXR and the latch signal XLA
The signals T, XPRE, the redundant row decoder selection signal RXDS, and the redundancy replacement selection signal XRDNS also exist independently for each bank and operate independently.

XPR in FIG. 22 is a row address predecoder, and generates a row address predecode signal PXADD from the row address signal XADD. Here, the row address predecode signal PXADD is 8 of X3N, 4N, 5N to X3T, 4T, and 5T obtained by predecoding X3 to X5.
Book signal and X6N, 7 obtained by pre-decoding X6 to X8
8 signals of N, 8N to X6T, 7T, 8T and X9, X
X9N, 10N to X9T, 10
It is composed of four signals of T. Eight signals such as X3T, 4T, 5T, and eight signals such as X6T, 7T, 8T,
The row decoder XDEC selection in each subarray includes X9T,
The four signals such as 10T are used for selecting a sub-array in the SXC circuit. Row predecode address signal PXADD
Are delayed in the row address decode circuit XPR to wait for the decision of selection or non-selection of the redundant memory cell, and the latch signal X
Latched by LAT. When the ACT signal becomes low level, all the row predecode address signals PXADD are deselected by the XPRE signal, and as a result, the selected memory cells are also deselected.

FIG. 26 is a circuit diagram showing an example of the sub-array selection circuit SXC. When the row address signal XADD does not match all of the defective replacement addresses stored in all the redundant decoders XRED and the redundant decoder selection signal RXDS remains at the high level, the sub-array selection circuit SXC outputs the row predecode address signal PXADD. (X9,
X10), the sense amplifier array not explicitly shown in the drawing included in the corresponding subarray is activated, and the subarray selection signal BSEL is activated.

When the row address signal XADD matches the defective replacement address stored in any one of the redundancy decoders XRED and the redundancy decoder selection signal RXDS goes low, the sense amplifier is set based on the redundancy replacement selection signal XRDNS. Activate the column and use the sub-array selection signal BSEL
Activate. At this time, if the sub-array designated by row predecode address signal PXADD does not match the sub-array designated by redundant replacement selection signal XRDNS, the redundant main word line in the sub-array designated by row predecode address signal PXADD and Activation of the sense amplifier row is suppressed. In any case, the activated sense amplifier row is included in the sub-array including the activated word line.

FIG. 27 is a circuit diagram showing an example of the row decoder XDEC. Row decoder XDE activates main word line MWL based on row predecode address signals PXADD (X3 to X8) and sub differential selection signal BSEL. However, when the row address signal XADD matches the replacement address stored in any one of the redundant decoders XRED and the redundant row decoder selection signal goes low, the activation is stopped.

FIG. 28 is a circuit diagram showing an example of the redundant row decoder RXDC. When the row address signal XADD matches the replacement address stored in one of the redundancy decoders XRED, the redundant row decoder RXDC activates the corresponding redundant main word line RMWL based on the redundancy replacement selection signal XRDNS. I do. As a result, the main word line including the defective address is replaced with a redundant main word line.

FIG. 29 is a circuit diagram showing an example of the sub third line selection circuit RAIS. Sub third line selection circuit RAI
S indicates which of the redundant decoders XR is the row address signal XADD.
When the redundant row decoder selection signal RXDS is not at the same level as the defective replacement address of the ED, and only one of the sub third line selection signals RAI0 to RAI7 is activated in accordance with the row address signal XADD (X0 to X2). I do. On the other hand, when row address signal XADD matches the defective replacement address of one of redundant decoders XREDD and redundant row decoder select signal RXDS is at a low level, redundant sub third line select signal RRAIS1, instead of X1 of row address signal XADD, X2 instead of redundant sub third line select signal RRAIS2 and row address signal XADD
X0, one of the sub-word line selection signals RAI0 to RAI7 is selected. The main word line MWL and the sub-word line selection signal RAI are input to a sub-word driver circuit (not shown), and select the sub-word line SWL by AND logic. Sub-word line SWL is directly connected to a memory cell to activate it.

As described above, in this conventional example, the relationship between the redundancy decoder XRED and the main word line and the sub-word line selection signal RAI activated thereby is fixed, and as a result, each of the redundancy decoder XRED and the sub-word The relationship between the lines is fixed. Also, the number of subword lines that one redundant decoder XRED is responsible for replacing (two in this case) is fixed.

Here, there are four redundant main word lines per bank and 32 corresponding sub word lines. There are 16 redundant decoders XRED in one bank, and replacement by one redundant decoder XRED is performed in units of two sub-word lines sharing an address other than X0. If it has only a row address or is within two addresses sharing other than X0, up to 16 locations can be rescued per bank.

However, when each defective portion cannot be accommodated by two addresses sharing other than X0, for example, when a main word line (corresponding to eight sub-word lines sharing other than X0 to X2) becomes defective. Are four redundant decoders X
Replacement of eight sub-word lines is performed using RED. In this case, 16 redundant decoders XRE per bank
D can be used to rescue four main word lines. In any case, the redundant decoder XR used for defective replacement
The ED and redundant sub-word lines are used only in each bank, and do not depend on the defective replacement status of multiple banks.

However, in the semiconductor memory device described above, for example, when a defective memory cell physically existing in bank B is to be replaced with a redundant memory cell physically existing in bank A, If it is attempted to activate the redundant memory cell of bank A, which has replaced the defective memory cell in bank B, at the timing of activating bank A, two memory cells in bank A are activated simultaneously. May occur. If these memory cells share a sense amplifier, a data line, etc., a malfunction will occur. Since the addresses of two memory cell groups in different banks can be specified independently and arbitrarily from outside, this problem cannot be avoided for all combinations of addresses.

Therefore, in a semiconductor memory device having a configuration as shown in FIG. 22, it is impossible to perform relief by sharing a redundant memory cell between different banks, and a defective memory cell in each bank is Can be replaced only by the redundant memory cell of As a result, in a chip in which a defect exists in a part of the banks, when any one of the banks cannot replace the defective memory cell with the redundant memory cell, the whole chip is rescued. Becomes impossible, which causes a decrease in yield.

Further, since the fuse is cut by a laser, there is a limit in miniaturization, so that the area of the redundant decoder is larger than that of other circuits. for that reason,
The number of redundant memory cells that can be provided is determined by the number of redundant decoders that can be provided.

In the semiconductor memory device, there are several different patterns for the address configuration of the defective bit due to its structure and manufacturing method. For example, a single bit defect caused by an element such as a transistor constituting a memory cell, a single line defect caused by a disconnection of a wiring in a memory cell array, a defect that can be remedied by replacing one row address, and a defect of a row decoder circuit The memory cells are classified as those which can be repaired by replacing a plurality of row addresses, such as defective adjacent lines due to short-circuiting between wirings in the memory cell array.

Also, in the case where a plurality of rows need to be replaced, the number of adjacent row addresses that need to be replaced is indefinite due to the size of dust adhering during the process which is the main cause of short-circuiting between wirings. Therefore, in the conventional example, since a fixed number of defective replacements are performed by one redundant decoder, when the number of adjacent defective row addresses exceeds the replacement unit, replacement must be performed using a plurality of redundant decoders. . Conversely, when the number of adjacent defective row addresses is smaller than the replacement unit, replacement is performed including the non-defective row address adjacent to the defective row address, and the use efficiency of the redundant memory cell is reduced.

[0036]

In the conventional semiconductor memory device described above, the redundancy decoder provided for a certain bank can only replace a defective memory cell generated in the bank with a redundancy. However, defective memory cells in different banks cannot be replaced. For this reason, there is a problem that a redundant decoder is required for each bank, the replacement efficiency is reduced, and the yield is deteriorated.

An object of the present invention is to provide a semiconductor memory device in which a defective memory cell generated in a different bank is replaced by a redundant decoder commonly provided between the banks, thereby improving the replacement efficiency and improving the yield. That is.

[0038]

In order to achieve the above object, in a semiconductor memory device according to the present invention, in each redundancy decoder, a means for programming which bank of the redundancy decoder replaces a defective cell, The redundancy decoder has means for programming how many addresses are to be replaced. That is, the semiconductor memory includes a plurality of normal memory cells, means for activating the normal memory cells in response to an externally applied address, a plurality of redundant memory cells, and a plurality of normal memory cells. First storage means for storing an address of a defective memory cell to be executed, an address externally applied,
Means for comparing the address of the defective memory cell with the address, means for activating the redundant memory cell in response to the output of the comparing means, or means for suppressing the activation of the normal memory cell, or both means. Then, the comparing means compares all or a part of the bits constituting the address applied from the outside with the stored address of the defective memory cell.

The number of bits to be compared by the comparing means is variable, and the second storing means for storing the number of bits to be compared by the comparing means or the number of bits not to be compared, and the output of the comparing means. And a first transmitting means for transmitting the contents of the second storing means to the activating means of the redundant memory cell based on the address signal applied from the outside. It has an operating divided memory cell array structure, and each of the divided memory cell arrays can have a plurality of the redundant memory cells.

Further, there is provided a third storage means for storing which of the divided memory cell arrays a defective memory cell in which memory cell array is to be replaced, wherein the comparison means comprises: a third storage means; A plurality of memory cell array selection signals applied from the outside are compared, and a plurality of second memory cells corresponding to the respective comparing means and storing which redundant memory cell in the divided memory cell array is used to replace the defective memory cell are stored. And a second transmitting means for transmitting the contents of the fourth storing means to the redundant memory cell activating means based on an output of the comparing means.

Further, the fourth storage means stores N
The second transmission means is constituted by a storage means for storing a binary number of digits, and can store a combination of 2 to the Nth power.
And a wired-or node that transmits N-digit binary numbers.

The activation means for activating the redundant memory cell includes: means for decoding a signal from the second transmission means;
Means for latching the value of the second transmitting means or the decoded value, wherein the activating means for the redundant memory cell determines, from the outside, the number of bits not to be compared indicated by the first transmitting means. It is possible to have a selection means which adopts from the bits constituting the applied address and adopts the remaining bits constituting the second transmission means.

Further, another semiconductor memory device of the present invention comprises a normal memory cell block comprising a plurality of memory cells,
A plurality of banks each having a plurality of redundant memory cells for replacing defective memory cells existing in the normal memory cell block and capable of independently performing read / write, and A plurality of redundant decoders which are provided in common and store an address of the defective memory cell, and compare an address indicated by an input address signal with an address of the stored defective memory cell; The address of the redundant memory cell for replacing the cell is stored, and when the address indicated by the address signal matches the address of the stored defective memory cell in each of the redundant decoders, Replacement memory cell storage means for activating a redundant memory cell set to replace a memory cell In the storage device, the redundancy decoder compares the address indicated by the address signal with the address of the stored defective memory cell without referring to a bank selection signal included in the address signal during a refresh operation. The replacement memory cell storage means outputs a redundancy replacement selection signal for indicating a bank to be replaced with a redundant memory cell for each of the banks.

According to the present invention, during the refresh operation, each redundant decoder compares the address indicated by the address signal with the address of the stored defective memory cell without referring to the bank selection signal included in the address signal. The replacement memory cell storage means outputs a redundancy replacement selection signal for indicating a bank to be replaced with a redundant memory cell for each bank.

Therefore, even at the time of refresh in which a plurality of banks are activated at the same time, whether or not to perform replacement is selected for each bank. Therefore, replacement of simultaneously activated memory cells belonging to a plurality of banks is performed. Since a common redundant decoder can be used, the yield can be improved by improving the replacement efficiency.

Further, another semiconductor memory device of the present invention comprises a normal memory cell block comprising a plurality of memory cells,
A plurality of banks each having a plurality of redundant memory cells for replacing defective memory cells existing in the normal memory cell block and capable of independently performing read / write, and The address of the defective memory cell is provided in common, and the address of the defective memory cell is stored, and the address indicated by the input address signal is compared with the stored address of the defective memory cell, and the signals match. In such a case, a plurality of redundant decoders that output a defective address match signal, and the address of a redundant memory cell for replacing the defective memory cell are stored, and when a defective address match signal from each of the redundant decoders is input, Replacement memory cell storage means for activating a redundant memory cell set to replace the defective memory cell. In the body memory device, when a command to activate a certain bank is input, a latch signal for latching the defective address match signal is output, and after a predetermined time from the output of the latch signal, the defective address match signal is output. And a timing control circuit for outputting a signal for resetting the timing.

According to the present invention, when a common defective address coincidence signal is activated between banks and then inactivated for a certain period of time, even if the periods in which different banks are in the active state overlap, redundancy with defective memory cells can be achieved. Replacement with a memory cell can be performed normally.

Further, another semiconductor memory device of the present invention comprises a normal memory cell block comprising a plurality of memory cells,
A plurality of banks each having a plurality of redundant memory cells for replacing defective memory cells existing in the normal memory cell block and capable of independently performing read / write, and The address of the defective memory cell is provided in common, and the address of the defective memory cell is stored, and the address indicated by the input address signal is compared with the stored address of the defective memory cell, and the signals match. In such a case, a plurality of redundant decoders that output a defective address match signal, and the address of a redundant memory cell for replacing the defective memory cell are stored, and when a defective address match signal from each of the redundant decoders is input, Replacement memory cell storage means for activating a redundant memory cell set to replace the defective memory cell. In the body memory device, when a command is provided for each of the banks and activates the corresponding bank, a latch signal for latching the defective address coincidence signal is output. A plurality of timing control circuits for outputting a redundant circuit precharge signal for resetting the defective address coincidence signal when a command for precharging a bank is input; provided for each bank; When the latch signal for a bank is output, the defective address match signal is latched, latched and output. When the redundant circuit precharge for the corresponding bank is output, the defective address match signal latched is output. A plurality of defective address coincidence signal latch circuits for resetting.

According to the present invention, the defective address match detection signal is latched by each latch signal provided for each bank, and the latched signal is reset by the redundant circuit precharge signal. Therefore, different banks can be activated independently and separately.

[0050]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.
2A and 2B are timing charts showing the operation. FIG. 2A shows a case where a redundant memory cell is selected.
FIG. 2B shows a case where a redundant memory cell is not selected. The operation of a signal not particularly specified is the same as that of the conventional semiconductor memory device of FIG.

The operation will be described below with reference to a circuit diagram and a timing chart. The row address signal XADD in the conventional semiconductor memory device includes a bank selection signal CBS for designating a bank in addition to the row address.

The row address signal buffer circuit XABF supplies complementary signals X0N to X0N in accordance with the row address signal XADD.
X10N, X0T to X10T are transmitted to the bank selection signal CBS.
To generate complementary signals CBST and CBSN.

FIG. 3 is a circuit diagram showing an example of the redundant decoder XRED. In the conventional redundant decoder XRED of FIG. 24, a fuse F for storing a bank to be replaced is stored.
BSN and FBST are provided.

The redundancy decoder XRED shown in FIG.
Then, the replacement address stored in the fuses FnN and FnT matches the row address signal XADD, and the selected bank selection signal CBS and the fuses FCBN and FCB are selected.
Except when the banks to be replaced stored in T match, the nodes 100 and 101 are conductive.

FIG. 4 is a circuit diagram showing an example of the redundant memory cell selection circuit XRDN. The redundant memory cell selection circuit
There is one redundant memory cell selection circuit XRDN for four redundant decoders XRED circuits.

When one of the four defective address match signals XREBL connected to the memory cell select circuit XRDN goes to a high level, the redundant memory cell select circuit XRDN goes to a high level by a precharge circuit (not shown). The replacement selection signal XRDNS is pulled down to a low level. The redundant replacement selection signal XRDNS is a signal indicating that a redundant memory cell has been selected.

FIG. 4 is a circuit diagram showing an example of the XRDN. XRDN is a redundant memory cell selection circuit. Here, one XRDN exists for four XREDs. However, these numbers themselves do not depend on the essence of the present invention.

FIG. 4 is a circuit diagram showing an example of XRDN in FIG. When one of the four connected XREBL signals goes to a high level, the XRDN outputs the XRDNS0 and XRDNS1 signals that have been brought to a high level by a precharge circuit not specifically shown in the figure to a fuse FS.
The signal is selectively dropped according to 00 to FS13.
The XRDNS signal is a signal indicating that a redundant memory cell has been selected. Also, the number of replacements is shown, and XRDNS0
When XRDNS1 is at a high level / high level, no redundant memory cell is selected and no replacement is performed. When it is at a low level / high level, one sub-word line is replaced. Replaces two sub-word lines, and replaces four sub-word lines in the case of low level / low level.

Further, the RXDS0 and RXDS1 signals which are at a high level by a precharge circuit not explicitly shown in the figure are selectively pulled down in accordance with the fuses FX00 to FX13. RXDS0 and RXDS1
Is a signal for selecting a redundant main word line to be activated and a sub-array including the same.

Further, RRAIS1 which is at a high level by a precharge circuit not explicitly shown in the figure
And the RRAIS2 signal is selectively pulled down in accordance with the fuses FR0 and FR1. RRAIS1 and RRA
The IS2 signal is a signal for selecting the sub-word selection signal RAI.

For any signal, any XR
The high level is maintained unless the comparison in the ED circuit matches.

The banks to which the XRED circuit and the XRDN circuit belong are not fixed, and operate regardless of the selected bank. Therefore, PXR, XLAT,
The signals XPRE, RXDS, XRDNS, and RRAIS are also shared between banks, and operate regardless of the activated bank.

FIG. 5 is a circuit diagram showing an example of the sub-array selection circuit SXC. When the row address signal XADD does not match all of the defective replacement addresses stored in all the redundant decoders XRED and the redundant row decoder selection signals RXDS0 and RXDS1 remain at the high level, the sub-array selection circuit SXC performs row predecoding. The address signal PXADD (X9, X10) is decoded, latched by a row decoder address latch signal XDLA, and based on this, a sense amplifier column not explicitly shown in the drawing included in the corresponding subarray is activated and a subarray selection signal is activated. Activate BSEL.

When the row address signal XADD matches the replacement address stored in one of the redundancy decoders XRED and the redundancy row decoder selection signals RXDS0 and RXDS1 go low, each subarray selection circuit S
XC decodes redundant replacement selection signal XRDNS, latches it with row decoder address latch signal XDLA, and activates a sense amplifier column designated by redundant replacement selection signal XRDNS based on this. At this time, if the sub-array designated by row predecode address signal PXADD does not match the sub-array designated by redundant replacement selection signal XRDNS, the redundant main word line in the sub-array designated by row predecode address signal PXADD and Activation of the sense amplifier row is suppressed.

In any case, the activated sense amplifier row is included in the subarray including the activated word line.

FIG. 6 is a circuit diagram showing an example of the row decoder XDEC. Row decoder XDEC converts row predecode address signal PXADD (X3-X8) and subarray select signal BSEL to row decoder address latch signal XD.
Latched at LA, and the main word line is activated based on this. However, when the row address signal XADD matches the replacement address stored in one of the redundant decoders XRED and the redundant row decoder select signal RXDS becomes low level, the activation is canceled. Also. ACT
When the signal goes low, all the main word lines MWL are deselected by the row decoder precharge signal XDPR signal.

FIG. 7 is a circuit diagram showing an example of the redundant row decoder RXDC. When the row address signal XADD matches the replacement address stored in one of the redundancy decoders XRED, and the redundancy row decoder selection signal RXDS goes low, the redundant row decoder RXDC is based on the redundancy replacement selection signal XRDNS. Then, the redundant main word line is activated. When the ACT signal goes low, all the redundant main word lines RMWL are deselected by the row decoder precharge signal XDPR. FIG. 8 is a circuit diagram showing an example of the row decoder XDEC circuit. The sub-word line selection circuit RAIS selects the sub-word line selection signal RAI according to the row address predecode signals PXADD, RRAIS and the redundant row decoder selection signal. The row address signal XADD is set to any of the redundant decoders X.
When the redundant row decoder selection signal RXDS is at a high level and does not match the defective replacement address of RED, only one of the sub-word line selection signals RAI0 to RAI7 is activated in accordance with the row address signal XADD (X0 to X2). I do. On the other hand, when the row address signal XADD matches the defective replacement address of one of the redundant decoders XRED and at least one of the redundant row decoder select signals RXDS0 and RXDS1 is at a low level, the redundant subword line select signal RRAIS is followed.

When only XRDNS0 is at low level (1
In this case, the RRAIS0 signal and the X of the row address signal XADD are replaced with the X0 of the row address signal XADD.
1 instead of RRAIS1 signal and row address signal XADD
RAI0 to RAI7 with the RRAIS2 signal instead of X2
One of them is selected.

When only the signal XRDNS1 is at the low level (in the case of two replacements), the X of the row address signal XADD is
1 instead of RRAIS1 signal and row address signal XADD
Of RAI0 to RAI7 is selected by the RRAIS2 signal and X0 of the row address signal XADD instead of X2.

When both signals XRDNS0 and XRDNS1 are at the low level (in the case of four replacements), RRAIS2 signal is used instead of X2 of row address signal XADD, and RAI0-RA1 is used with X0 and X1 of row address signal XADD.
One of I7 is selected. These results indicate that XDLA
Latched by a signal. When the ACT signal goes low, all the RAI signals are deselected by the XDPR signal.

The main word line MWL and the sub-word line selection signal RAI are input to a sub-word driver circuit not shown in the figure, and select the sub-word line SWL by AND logic. Sub-word line SWL is directly connected to a memory cell to activate it.

When the ACT signal goes low,
All main word lines MWL or redundant main word lines RMWL are
Since sub word line selection signal RAI is not selected, sub word line SWL is also inactivated.

In the semiconductor memory device of this embodiment, which bank the replacement address of each redundant decoder XRED stores and compares is determined by a program by fuse cutting.

Here, as in the conventional example of FIG. 22, there are four redundant main word lines per bank and 32 corresponding sub word lines. Also, the redundant decoder XRE
There are 32 Ds for two banks (the same number in the chip as in the conventional example of FIG. 22).

Therefore, all redundant decoders XRED
Is used for the bank A, and when each replacement is limited to one address (corresponding to a defect such as a single bit defect or a broken sub word line), a maximum of 32 defects can be relieved in the bank. Therefore, when there is a bias in the occurrence of defects among the banks, the defect relief efficiency is improved.

On the other hand, a subword line having four addresses sharing an address other than X0 and X1 can be replaced with only one redundant decoder XRED. Therefore, for example, when a main word line (corresponding to eight sub-word lines sharing other than X0 to X2) becomes defective,
Replacement of eight sub-word lines is performed using two redundant decoders XRED. In this case, if eight redundant decoders XRED are used, four main word lines (32 sub word lines) can be repaired per bank. Since there are only four redundant main word lines per bank, no further repair can be performed for bank A, but at this time, for bank B, the remaining 24 redundant decoders XR
By using the ED, defect remedy can be performed at a maximum of 24 points. Therefore, even when one defect is constituted by a plurality of consecutive defective addresses, the defect relief efficiency is improved.

As described above, the semiconductor memory device of the present embodiment uses the redundant decoder XRED for replacing any of the defective cells in the banks A and B as compared with the conventional semiconductor memory device shown in FIG. Therefore, the redundant memory cells existing in each bank can be used efficiently, and even when the defective memory cells are unevenly distributed in a defective bank, the same number of redundant decoders XRED and redundant memory Despite the number of cells, there is a high probability of relief, and the yield can be improved without significantly increasing the chip area.

(Second Embodiment) FIG. 9 is a circuit diagram showing an XRDN circuit in a semiconductor memory device according to a second embodiment of the present invention, and FIG. 10 is a circuit diagram showing an RXDC circuit according to the second embodiment of the present invention. FIG. 11 shows the RAI according to the second embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an S circuit.

In the first embodiment, signals XRDNS0 and XRDNS indicating that a redundant memory cell has been selected are set.
The DNS1 signal also serves as the replacement number instruction. In the present embodiment, these two functions are separated, and the XRDNS signal indicates that the redundant memory cell has been selected, and the XR
The LEN0 and XRLEN1 signals indicate the number of replacements. At this time, when XRLEN0 and XRLEN1 are at low level / low level, one sub-word line is replaced. When XRLEN0 and XRLEN1 are at high level / low level, two sub-word lines are replaced.
Perform this replacement. In the present embodiment, XR is used to determine that a redundant memory cell is selected in RXDC.
Since it is only necessary to refer to the DNS signal, there is an effect that the circuit is simplified in addition to the effect of the first embodiment.

(Third Embodiment) Synchronous DRAM
In this example, at the time of reading / writing, only the bank to which the memory to be read / written belongs is activated, but at the time of refreshing, a plurality of banks are activated simultaneously. At the time of reading / writing, the sense amplifier is operated after activating the corresponding word line, but at the time of refreshing, only the sense amplifier is operated.

However, in the first and second semiconductor memory devices, the redundancy decoder XRED is shared between the banks A and B to improve the replacement efficiency. However, both the banks A and B are used. A problem occurs at the time of refresh which is simultaneously activated. For example, when a defective memory cell in the bank A is replaced, if both the banks A and B are simultaneously activated, the redundant replacement selection signal XRDNS is also output to the bank B. Even if it is not necessary to perform the replacement, the replacement is forcibly performed.

As described above, in the semiconductor memory device according to the first embodiment shown in FIG. 1, when defects are present in different banks, refresh cannot be performed by simultaneously activating both banks. If refreshing is performed by simultaneously activating both banks, it is necessary to provide a redundant decoder for each bank.

As described above, in the semiconductor memory devices of the first and second embodiments, a redundant decoder is provided in common for a plurality of banks, and when a defect exists in a different bank, the difference is different at the time of refreshing. Since a plurality of banks cannot be activated at the same time, there is a problem that a redundancy decoder is required for each bank, the replacement efficiency is reduced, and the yield is deteriorated.

In the semiconductor memory device of this embodiment, even when a defect is present in different banks, refresh can be performed to improve the replacement efficiency and improve the yield.

FIG. 12 is a block diagram showing a configuration of a semiconductor memory device according to the third embodiment of the present invention, and FIG. 13 is a circuit diagram of a redundant memory cell selection circuit XRDN in this embodiment. 1 denote the same components.

The redundant memory cell selection circuit XRDN in the semiconductor memory device of the first embodiment shown in FIG. 1 is a signal which indicates that a redundant memory cell has been selected when replacement by a redundant memory cell is performed. Select signal XRDN
Only S was output. However, the redundant memory cell selection circuit XRDN in the semiconductor memory device of the present embodiment
As shown in FIG. 2, a redundant replacement selection signal XRDNS which is a signal indicating that a redundant memory cell of bank A is selected.
(A) and a redundant replacement selection signal XRDNS (B) which is a signal indicating that the redundant memory cell of the bank B has been selected. The redundant replacement selection signal XRDNS (A) is input to the redundant row decoder RXDC, the sub-array selection circuit SXC, and the sub-word line selection circuit RAIS provided in the bank A, and the redundancy replacement selection signal X
RDNS (B) is input to the redundant row decoder RXDC, the sub-array selection circuit SXC, and the sub-word line selection circuit RAIS provided in the bank B.

As shown in FIG. 13, in the redundant memory cell selection circuit XRDN, when the defective address coincidence signals XREBL0 to XREBL become high level, the corresponding one of the fuses FS00 to FS03 is blown. If not, the redundant replacement selection signal XRDNS (A) goes low. Similarly, the defective address match signal XR
When EBL0 to EBL3 become high level, the fuse FS
When the corresponding fuse among 10 to FS13 is not blown, the redundant replacement selection signal XRDNS (B) becomes low level.

The row address signal buffer XABF in the semiconductor memory device of the present embodiment determines that it is the time of refreshing if the bank selection signal CBS of the upper bit of the row address signal XADD is not input, and determines the complementary signal. Both CBST and CBSN are output as low level.

Therefore, at the time of refreshing, a defective address match signal XREBL is output if only the row address matches regardless of which of the banks A and B the redundant decoder XRED is set to. Then, in the redundant memory cell selection circuit XRDN, the redundant decoder XR that outputs the input defective address match signal XREBL is output.
The fuse is set so that the redundant replacement selection signal XRDNS is output to the same bank as the bank to which ED is set.

For example, the defective address match signal XR output from the redundancy decoder XRED set in the bank A
When EBL is input, the redundant replacement selection signal XRDNS
(A) is output, and the redundant replacement selection signal XRDNS is output.
(B) is not output. As a result, the replacement with the redundant memory cell is performed in the bank A, while the replacement in the bank B is performed.
Is not replaced.

As described above, in the semiconductor memory device of the present embodiment, the bank selection signal CS in the row address signal XADD is used.
Even at the time of refresh without A, it is possible to replace only the bank to be replaced.

Next, FIGS. 14 to 17 are timing charts showing the operation of the present embodiment.

FIG. 14 is a timing chart showing the operation at the time of refresh when replacement is performed in both banks A and B.

In this case, redundant replacement selection signal XRDN
S (A) and XRDNS (B) are both once precharged to a high level, and then the defective address match signal X is
It becomes active low level by REBL. Therefore, in both banks A and B, the main word line M
The redundant main word line RMWL is activated instead of WL.

FIG. 15 is a timing chart showing an operation at the time of refresh when replacement is not performed in either of banks A and B.

In this case, redundant replacement selection signal XRDN
Both S (A) and XRDNS (B) are once precharged to a high level, and then directly to an inactive high level. Therefore, the main word line MWL is activated in both the banks A and B, and the redundant main word line RMWL is not activated.

FIG. 16 is a timing chart showing an operation at the time of refresh when replacement is performed only in bank A.

In this case, redundant replacement selection signal XRDN
S (A) is once precharged and goes to a high level, and then goes to a low level which is active by the defective address match signal XREBL. However, the redundant replacement selection signal X
RDNS (B) temporarily becomes inactive high level after it is precharged and becomes high level once. Therefore, in bank A, redundant main word line RM
WL is activated, and the main word line MWL
Is activated.

FIG. 17 is a timing chart showing the operation at the time of reading / writing when the replacement is performed only in bank A.

In this case, redundant replacement selection signal XRDN
S (A) is once precharged and goes to a high level, and then goes to a low level which is active by the defective address match signal XREBL. However, the redundant replacement selection signal X
RDNS (B) temporarily becomes inactive high level after it is precharged and becomes high level once. Therefore, in bank A, redundant main word line RM
WL is activated. However, in this case, since the bank B itself is not activated, all signals related to the bank B are in an inactive state. In the semiconductor memory device of the present embodiment, even when both banks are simultaneously activated and refreshed, the redundancy replacement selection signal XRDNS (A),
Since (B) is provided for each bank, the bank to be replaced can be selected, so that there is no problem that unnecessary memory cells are replaced. Therefore,
At the time of writing / reading and refreshing, replacement of memory cells belonging to different banks and activated simultaneously can be performed by a common redundant decoder between banks. Thus, the replacement efficiency by the redundant memory cells is improved, and the yield of the semiconductor memory device can be improved.

(Fourth Embodiment) Next, a semiconductor memory device according to a fourth embodiment of the present invention will be described.

FIG. 18 is a circuit diagram of the timing control circuit 10 according to the fourth embodiment of the present invention, and FIG. 19 is a timing chart showing the operation of the semiconductor memory device according to the fourth embodiment of the present invention.

Each bank constituting the semiconductor memory device becomes active when an active command is input, and becomes inactive when a precharge command is input.

The active commands include an active command ACT A for bank A and a bank B
There is an active command ACT B. Also,
The precharge commands include a precharge command PREA for bank A and a precharge command PREB for bank B.

In the synchronous DRAM, bank A and
Since control such as data reading / writing is performed at the timing when the bank B becomes active at the same time, these commands are input regardless of the state of a different bank.

However, the last cycle t _rc , which is the interval at which active commands are input to the same bank, is about 90 ns, and the _last to las delay t _rrd , which is the interval at which active commands are input to different banks, is about 20 ns. Has become.

Here, each defective address coincidence signal XREB
Since L is shared by the banks A and B, while the active command is active and the defective address match signal XREBL is once in the active state, the active command of another bank cannot be validated.

For example, the defective address coincidence signal XREBL is in an active state from the input of the active command ACT A to the input of the precharge command PRE A. During this period, the active command ACT B is input. In this case, the active command ACT B is not accepted and the bank B cannot be activated.

The semiconductor memory device according to the present embodiment is provided to solve such a problem. Even if the active periods between the banks A and B overlap, the defective memory cell and the redundant memory cell are not connected. The replacement is performed normally.

The semiconductor memory device of this embodiment is different from the semiconductor memory devices of the first to third embodiments in FIG.
8, a timing control circuit 10 is provided.

The timing control circuit 10 comprises a delay circuit 11, inverter circuits 12, 14, 16, 17 and a NAND circuit 13. When ACT (A) becomes active (high level), the timing control circuit 10 outputs a one-shot pulse signal having a width determined by the delay circuit 11 to the redundant circuit latch signal XLAT.
, And outputs a one-shot pulse signal delayed by a time determined by the delay circuit 15 after outputting XLAT as PRR.

Then, the defective address match signal XREBL
Becomes active by XLAT and becomes inactive by PRR.

The timing control circuit 10 includes:
AC which is a signal indicating that bank B is active
T (B) is similarly input.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. This FIG.
9 is a timing chart showing an operation when the bank B becomes active before the bank A becomes inactive after the bank A becomes active.

First, when an active command ACT A is input, ACT (A) becomes active, and the timing control circuit 10 outputs XLAT. Then, XREBL becomes active due to the output of XLAT. Then, the PRR is output from the timing control circuit 10 a fixed time after the output of XLAT, so that XREBL becomes inactive.

Then, next, the active command ACT
When B is input, ACT (B) becomes active, and XLAT and P
RR is output, and XREBL becomes inactive after being active for a certain period of time.

In this embodiment, as described above, the XREBL common between the banks is activated and then inactivated for a certain period of time. The replacement of the cell with the redundant memory cell can be performed normally.

(Fifth Embodiment) Next, a semiconductor memory device according to a fifth embodiment of the present embodiment will be described.

In the semiconductor memory device of this embodiment, similarly to the fourth embodiment, the replacement of a defective memory cell with a redundant memory cell is normally performed even when the active states of the banks A and B overlap each other. It is intended to be performed.

The semiconductor memory device according to the present embodiment includes the first
In the semiconductor memory device according to the third embodiment, defective address coincidence signal latch circuits 20a and 20b are provided.

The defective address coincidence signal latch circuit 20a,
20b latches the defective address coincidence signal XREBL and outputs it as XRBNKa and XRBNKb.

Then, the active command ACT A,
When B is input, XREBL is activated for a certain period thereafter. Further, when an active command ACT A is input, XDLAa is output, and when a precharge command PRE A is input, XDLAa is output.
DPRa is output. And active command A
When CT B is input, a latch signal XDLab is output, and when a precharge command PRE B is input, X
DPRb is output.

Bad address match signal latch circuit 20a
Is composed of n-channel MOS transistors 21 and 22 and inverter circuits 23 to 25.

The n-channel MOS transistor 22 turns on when the row decoder address latch signal XDLa becomes active, and outputs XREBL to the input of the inverter circuit 23.

The n-channel MOS transistor 21 is turned on when the row decoder precharge signal XPDPRa becomes active, and the input of the inverter circuit 23 is set to low level. Here, the reason why the input of the inverter circuit 23 is set to the low level is to set the output state of the XRBNKa to the inactive low level.

Further, defective address match signal latch circuit 2
0b has the same structure and operation as those of the defective address coincidence signal latch circuit 20a, and therefore the description thereof is omitted.

Next, the operation of the semiconductor memory device of this embodiment will be described with reference to the timing chart of FIG. FIG. 21 is a timing chart showing the operation when bank B becomes active before bank A becomes inactive after bank A becomes active, as in FIG.

First, when the active command ACT A is input, XREBL becomes active and XDLAa is output. Therefore, XREBL is latched in the defective address match signal latch circuit 20a, and XRBNKa becomes active.

Then, next, the active command ACT
When B is input, a latch signal XDLAb is output, XREBL is latched in the defective address coincidence signal latch circuit 20b, and XRBNKb becomes active.

Then, the precharge command PRE A
Is input, the redundant circuit precharge signal XPDPRa
Is output, and the XRBNKa becomes inactive in the defective address match signal latch circuit 20a.

Finally, the precharge command PRE B
Is input, the redundant circuit precharge signal XPRb
Is output, and XRBNKb becomes inactive in the defective address match signal latch circuit 20b.

In the semiconductor memory device of this embodiment, the defective address coincidence detection signal XREBL is latched by XDLAa and XDLA provided for each bank, respectively, and the latched signal is reset by PRE A and PRE B respectively. I have. Therefore, the banks A and B can be activated independently and separately. In the first to fifth embodiments, examples of replacement of a defective memory cell at a row address have been described. A circuit can be configured.

In the first to fifth embodiments,
The redundant decoder XRED stores the address of the defective memory cell to be replaced depending on whether the fuse is cut or not.
The present invention is not limited to this, and the present invention can be applied to any non-volatile storage means that can store addresses even when the power is turned off. You can do it.

[0135]

As described above, according to the present invention, even at the time of writing / reading and at the time of refreshing, memory cells belonging to different banks that are simultaneously activated can be replaced by one redundant decoder. This has the effect that the yield can be improved by the improvement of the yield.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation when a defective address is selected in the semiconductor memory device in FIG. 1 (FIG. 2A)
3 is a timing chart (FIG. 2B) showing an operation when a defective address is not selected.

FIG. 3 is a circuit diagram illustrating an example of a redundant decoder XRED in FIG. 1;

FIG. 4 is a circuit diagram showing an example of a redundant memory cell selection circuit XRDN in FIG. 1;

FIG. 5 is a circuit diagram showing an example of a sub-array selection circuit SXC in FIG.

FIG. 6 is a circuit diagram showing an example of a row decoder XDEC in FIG. 1;

FIG. 7 is a circuit diagram showing an example of a redundant row decoder RXDC in FIG. 1;

FIG. 8 is a circuit diagram showing an example of a sub-word line selection circuit RAIS in FIG. 1;

FIG. 9 is a circuit diagram illustrating an example of a redundant memory cell selection circuit XRDN in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating an example of a redundant row decoder RXDC in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a circuit diagram showing an example of a sub-word line selection circuit RAIS in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 13 shows a redundant memory cell selection circuit XRDN in FIG.
FIG.

FIG. 14 is a timing chart showing an operation at the time of refresh when replacement is performed in both banks A and B.

FIG. 15 is a timing chart showing an operation at the time of refresh when replacement is not performed in either of banks A and B.

FIG. 16 is a timing chart showing an operation at the time of refresh when replacement is performed only in bank A;

FIG. 17 is a timing chart showing an operation at the time of reading / writing when replacement is performed only in bank A;

FIG. 18 is a circuit diagram of a timing control circuit 10 in a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 19 is a timing chart showing the operation of the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 20 is a circuit diagram of a defective address coincidence signal latch circuit in a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 21 is a timing chart showing the operation of the semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 22 is a block diagram showing a configuration of a conventional semiconductor memory device.

FIG. 23 is a timing chart showing an operation when a defective address is selected in the conventional example (FIG. 23A) and a timing chart showing an operation when a defective address is not selected (FIG. 2).
3 (b)).

FIG. 24 is a circuit diagram showing an example of a redundant decoder XRED in FIG. 22;

25 is a redundant memory cell selection circuit XRDN in FIG.
FIG. 3 is a circuit diagram showing an example of the embodiment.

FIG. 26 is a circuit diagram illustrating an example of an SXC circuit in FIG. 22;

FIG. 27 is a circuit diagram showing an example of a row decoder XDEC in FIG.

FIG. 28 is a circuit diagram showing an example of a redundant row decoder RXDC in FIG.

FIG. 29 is a circuit diagram showing an example of a sub-word line selection circuit RAIS in FIG. 22;

[Explanation of symbols]

XADD row address signal PXADD row predecode address signal PXR redundancy precharge signal XLAT row predecode address and redundancy circuit latch signal XPRE row predecode address and redundancy circuit precharge signal XDLA row decoder address latch signal XDPR row decoder precharge signal XREBL defective address match signals XRDNS, XRDNS (A), XRDNS (B)
Redundant replacement select signal RXDS Redundant row decoder select signal XRED Redundant decoder XRDN Redundant memory cell select circuit RRAIS1,2 Redundant sub word line select signal BSEL Sub array select signal MWL Main word line RMWL Redundant main word line RAI Sub word line select signal F0N-F10N, F0T ~ F10T, FBSN, FB
ST, FS00-FS13, FR00-FR23, FX
00 to FX13, FL00 to FL13 Fuse XPR Row address decode circuit XDEC Row decoder RXDC Redundant row decoder RAIS Subword line select circuit SXC Subarray select circuit ARRAY0 Bank A ARRAY1 Bank B SUBA00 to SABA13 Subarray XABF Row address signal buffer CBS Bank select signal 10 Control circuit 11 delay circuit 12 inverter circuit 13 NAND circuit 14 inverter circuit 15 delay circuit 16, 17 inverter circuit 20a, 20b defective address coincidence signal latch circuit 21, 22 n-channel MOS transistor 23-25 inverter circuit 100-102 nodes

────────────────────────────────────────────────── ─── Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 29/00 G11C 11/401-11/4099 WPI (DIALOG)

Claims (16)

(57) [Claims] A plurality of normal memory cells; means for activating the normal memory cells in response to an externally applied address; a plurality of redundant memory cells; and a plurality of normal memory cells. First storage means for storing an address of a defective memory cell; comparing means for comparing the externally applied address with the address of the defective memory cell; and storing the redundant memory cell in response to an output of the comparing means. Means for activating, or means for suppressing activation of the normal memory cell, or both means, wherein the comparing means comprises only all or some of bits constituting an address applied from the outside. For
The number of bits to be compared by the comparing means is variable when compared with the stored address of the defective memory cell, and the number of bits to be compared by the comparing means or the comparison target is
A second storage unit for storing the number of bits not required, and the second storage unit based on an output of the comparison unit.
A first method of transmitting the contents to the activation means of the redundant memory cell;
The semiconductor memory device which is characterized in that have a transmission means. 2. The memory cell array according to claim 2, wherein said memory cell array has a divided memory cell array structure which operates independently in accordance with said externally applied address signal, and each of said divided memory cell arrays has a plurality of said redundant memory cells.
2. The semiconductor memory device according to 1 . 3. The memory cell array of claim 1, wherein:
3. The storage device according to claim 1, further comprising: a third storage unit configured to store a defective memory cell in which memory cell array is to be replaced, wherein the comparison unit compares the third storage unit with a memory cell array selection signal applied from outside. 3. The semiconductor memory device according to 2 . 4. A plurality of fourth storage means corresponding to each of said comparison means and storing which redundant memory cell in said divided memory cell array is to be replaced with a defective memory cell; Means for transmitting the contents of the fourth memory means to the redundant memory cell activating means based on the output of the second means.
4. The semiconductor memory device according to claim 3, further comprising: Wherein said fourth memory means is composed of a binary storage means N digits, the semiconductor memory device according to claim 4, wherein capable of storing a combination of 2 N. 6. The second transmission means includes a plurality of fourth transmission means.
6. The semiconductor memory device according to claim 5 , wherein said semiconductor memory device is connected to said storage means and comprises a wired-OR node transmitting in N-digit binary numbers. 7. The redundant memory cell activating means includes means for decoding a signal from the second transmitting means, and means for latching a value of the second transmitting means or a decoded value. Item 7. The semiconductor memory device according to any one of Items 4 to 6 . 8. The activating means of the redundant memory cell adopts the number of non-comparable bits indicated by the first transmitting means from the bits constituting the address applied from the outside, and the rest as the the semiconductor memory device according to any one of claims 4-6 having a selection means for employing the bits constituting the second transmission means. 9. An ordinary memory cell block including a plurality of memory cells, and a plurality of redundant memory cells for replacing defective memory cells existing in the ordinary memory cell block, each of which is independently provided. A plurality of banks that can perform read / write; and a memory that is provided in common with the plurality of banks, stores an address of the defective memory cell, and stores an address indicated by an input address signal. A plurality of redundant decoders for comparing with the addresses of the memory cells; storing the addresses of the redundant memory cells for replacing the defective memory cells; and storing the addresses indicated by the address signals in each of the redundant decoders. Is set to replace the defective memory cell when the address of the defective memory cell matches. In the semiconductor memory device having a replacement memory cell storage means for activating the redundant memory cell that, said redundancy decoder, the refresh operation, without referring to the bank selection signal are included in the address signal,
Comparing the address indicated by the address signal with the address of the defective memory cell stored, the replacement memory cell storage means outputs a redundant replacement selection signal for indicating a bank in which replacement with a redundant memory cell is performed. The semiconductor memory device outputs the data for each bank. 10. The redundancy decoder refers to the bank select signal by changing the number of bits of an address to be compared between when reading / writing data to / from the memory cell and when performing a refresh operation on the memory cell. 10. The semiconductor memory device according to claim 9 , wherein the address indicated by the address signal is compared with the address of the defective memory cell stored. 11. A redundant row activating unit for activating a word line connected to each of the redundant memory cells, wherein the replacement memory cell storing unit is for selecting a redundant memory cell to be activated. outputting a plurality of redundant row decoder selection signal, said redundant row activation means, according to claim 9 or 10 to determine the activation and deactivation of the word line connected according to the plurality of redundant row decoder selection signal 13. The semiconductor memory device according to claim 1. 12. The method of claim 11, wherein each redundancy decoder, any one of the normal address of the defective memory cells existing in the memory cell array, claim 9 which stores the presence or absence of cleavage of the plurality of fuses 11 13. The semiconductor memory device according to claim 1. Wherein said replacement memory cell storage means, an address of the redundant memory cell for replacing the defective memory cell, any one of claims 9 12, which is stored by the presence or absence of the plurality of fuse cutting 1 13. The semiconductor memory device according to claim 1. 14. The method of claim 13, wherein each memory cell and each redundant memory cell 1 claim 9, which is connected to the sub word lines are provided in plural for one main word line
The semiconductor memory device according to any one of 3. 15. An ordinary memory cell block comprising a plurality of memory cells, and a plurality of redundant memory cells for replacing defective memory cells existing in the ordinary memory cell block, each of which is independently provided. A plurality of banks capable of performing read / write; a plurality of banks provided in common with the plurality of banks; storing an address of the defective memory cell; and storing an address indicated by an input address signal A plurality of redundant decoders that compare the address of the defective memory cell and output a defective address match signal when those signals match, and store the address of the redundant memory cell for replacing the defective memory cell When a defective address match signal is input from each of the redundant decoders, a setting is made to replace the defective memory cell. A replacement memory cell storage means for activating a redundant memory cell, wherein when a command to activate a certain bank is input, a latch signal for latching the defective address coincidence signal is output. And a timing control circuit for outputting a signal for resetting the defective address coincidence signal a fixed time after outputting the latch signal. 16. An ordinary memory cell block comprising a plurality of memory cells, and a plurality of redundant memory cells for replacing defective memory cells existing in the ordinary memory cell block, each of which is independently provided. A plurality of banks capable of performing read / write; a plurality of banks provided in common with the plurality of banks; storing an address of the defective memory cell; and storing an address indicated by an input address signal A plurality of redundant decoders that compare the address of the defective memory cell and output a defective address match signal when those signals match, and store the address of the redundant memory cell for replacing the defective memory cell When a defective address match signal is input from each of the redundant decoders, a setting is made to replace the defective memory cell. And a replacement memory cell storage means for activating a redundant memory cell, wherein when a command is provided for each bank and activates the corresponding bank, the failure occurs. A plurality of latch circuits for outputting a latch signal for latching an address match signal and outputting a redundant circuit precharge signal for resetting the defective address match signal when a command for precharging a corresponding bank is input. A timing control circuit, provided for each bank, wherein when the latch signal for the corresponding bank is output, the defective address coincidence signal is latched, latched and output, and the redundancy circuit for the corresponding bank is provided. A plurality of resetting the defective address match signals latched when a precharge is output And a defective address coincidence signal latch circuit.