JP3211829B2 - Audio signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio signal processing device that performs audio input and output processing, and more particularly to a read / write storage unit for audio storage under program control of a microcomputer. The present invention relates to a technique for executing input and output of a digital audio signal.

[Background of the Invention]

In recent years, memories that can read and write audio signals, for example,
Various techniques have been developed for digitally recording in RAM and reproducing it.

For example, in the field of electronic musical instruments, a model called a sampler employs such technology. Specifically, Japanese Patent Application Laid-Open No. 61-45297 filed by the applicant of the present patent application
And JP-A-62-127898.

In addition, various kinds of so-called solid-state recording, that is, storing voice messages using a semiconductor memory (particularly, RAM) have been performed. Furthermore, music recorders for recording music performances of several minutes to several tens of minutes by increasing the capacity of the RAM and developing them have been developed.

However, these techniques require dedicated hardware for inputting (writing) and outputting (reading) sound to the read / write storage means for storing sound.

In other words, the microcomputer processes control input of these devices (input from the keyboard and console panel, MI
DI and other external inputs, processing from the performance memory, etc.), and the parts that require a large amount of high-speed calculations are, for example, sound source circuits and DMAs.
This was performed using hardware with a special structure such as a controller.

However, the system configuration as described above has several problems.

First, the dedicated hardware has a storage device for temporarily storing data and an arithmetic circuit for performing calculations in order to process various data and parameters, so that the circuit scale is inevitably large.

Second, there is a natural limitation in controlling dedicated hardware with a microcomputer. For example, since the number of voice inputs and outputs (the number of polyphonics or tracks) is fixed in hardware, it cannot be changed by a command from a microcomputer. If such a change is to be made, a large-scale design must be performed, which requires a great deal of development effort and time. Further, the interface and communication protocol between the microcomputer and the dedicated hardware need to be re-developed for each dedicated hardware.

[Object of the invention]

Accordingly, it is an object of the present invention to provide an audio signal processing apparatus having a new structure which enables processing of audio input and output by program control of a microcomputer and does not require dedicated hardware.

[Structure and operation of the invention]

The present invention provides an A / D converter for converting an audio signal into audio data at a constant sampling period and outputting the audio data, an audio data storage unit for storing the audio data, and a D / A for converting the audio data into an audio signal and outputting the same. An apparatus comprising: a microcomputer having conversion means in the same chip; and an interrupt signal generating means for generating an interrupt signal corresponding to the sampling cycle, wherein the microcomputer is set at regular intervals. Execution instruction means for judging the operation mode being executed, and instructing execution of the program means corresponding to the judged operation mode; and executing in accordance with an instruction from the execution instruction means when set to the sampler input mode, A first program memory for storing voice data input via the A / D conversion means in synchronization with a signal in the voice data storage means; And when the sampler output mode is set, the sampler is executed according to an instruction from the execution instruction means,
According to an instruction from the execution instructing unit, the audio data stored in the audio data storage unit is read in accordance with a pitch to be sounded, and the read audio data is synchronized with the interrupt signal and the D / A conversion unit is used. And a second program means for outputting from the execution instruction means when the multi-track recorder input / output mode is set, and is executed through the A / D conversion means in synchronization with the interrupt signal. The input voice data is stored in the voice data storage means, and the voice data stored in the voice data storage means is read in response to an instruction from the execution instructing means. And a third program means for outputting the data from the D / A conversion means in synchronization with the third program.

According to the above configuration, a so-called one-chip microcomputer provided with A / D conversion means, audio data storage means and D / A conversion means in the same chip, if the sampler input mode is set, a sampling recording device, a sampler If it is set to output mode, it functions as a sampling and playback device, and if it is set to multi-track recorder input / output mode, it functions as a recorder for recording and playback. Becomes possible.

Furthermore, when set to either the sampler output mode or the multi-track recorder input / output mode,
Reading audio data from the audio data storage means in response to an instruction from the execution instruction means for issuing an execution instruction at regular intervals,
The audio data read out is output from the D / A converter in synchronization with the interrupt signal corresponding to the sampling period. It is possible to realize audio signal processing with little distortion without having dedicated hardware.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Overall Configuration> FIG. 1 shows the overall configuration of the audio signal processing apparatus according to the present embodiment. Control of the entire apparatus is performed by a one-chip microcomputer 1. That is, the microcomputer 1 executes not only the processing of the control input from the switch unit 2 to the audio signal processing device but also the processing of the read / write control to the audio storage RAM 3 by the program control.
No special hardware is required. The switch unit 2 includes a keyboard of an electronic musical instrument in addition to various function keys. That is, as will be described later, the audio signal processing apparatus has a function of a sampler (sampling electronic musical instrument) and a function of a multi-track recorder, and particularly, the keyboard of the switch unit 2 is used when performing with the sampler. You. The input information of the switch unit 2 is processed by the microcomputer 1.

The audio storage RAM 3 can record a plurality of types of audio signals, and is directly accessed by the microcomputer 1. Therefore, transfer lines for address, data, and read / write control are provided between the microcomputer 1. This audio recording RAM3,
The internal RAM of the microcomputer 1 can also be used. Depending on the RAM capacity, it is possible to select whether to use the internal memory or the external memory.

The microcomputer 1 sends audio signals of a plurality of channels (CH1 to CHn) to the amplifiers 4-1 to 4-n.
After being amplified through the low pass filters 5-1 to 5-
n after filtering through the internal A / D
The data is converted into a digital audio signal by a converter group (described later) and recorded in a designated area of the audio storage RAM 3.

Also, the microcomputer 1 outputs a voice storage RA.
The audio signals of a plurality of channels (CH1 to CHn) read from M3 are output after being converted into digital / analog by an internal D / A converter group (described later), and are output by low-pass filters 6-1 to 6
The signal is filtered by -n, amplified by the amplifiers 7-1 to 7-n, supplied to the speakers 8-1 to 8-n, and emitted.

Of course, the read audio signal may be appropriately mixed in the digital domain or the analog domain and output in stereo from, for example, two speakers, or may be output to a speaker system of four channels or the like.

The microcomputer 1 can edit various parameters in both the sampler mode and the multi-track recorder mode. When an operation for that is performed by the switch unit 2, the corresponding display liquid crystal is displayed as necessary. This can be performed on the display 9.

<Structure of Microcomputer> FIG. 2 is a block diagram showing the internal structure of the microcomputer 1. The illustrated elements are mounted on one chip.

The control ROM 31 stores a program for processing various control inputs of the audio signal processing device and a program for inputting / outputting audio signals.
The program word (instruction) of the designated address is sequentially output via the OM address decoder 33. Necessary data is also stored in the program word, and is used selectively. For example, parameters such as pitch data and envelope data (rate, level) are also included. This program word length is fixed, and the next word system is used in which a part of the program word is input to the ROM address control unit 32 as a lower part (intra-page address) of an address to be read next. A program counter method may be used. The RAM address control unit 34 specifies the address of the corresponding register in the RAM 35 when the operand of the instruction from the control ROM 31 specifies a register. The RAM 35 is a group of registers, and is used for general-purpose operation, flag operation, operation of voice input / output address, operation of musical sound, and the like. The arithmetic circuit 36 includes an adder / subtractor, a logical operator, and a multiplier.
It is selectively used when the instruction from the ROM 31 is an arithmetic instruction. In particular, the multiplier is used for the interpolation operation of the waveform and the calculation of the envelope. As an optimization for that, the first and second data inputs (for example, 16-bit data) are multiplied and the same length (16 bits) as the input is used. Is output. An operation analysis unit (instruction decoder) 37 decodes an operation code of an instruction from the control ROM 31 and sends a control signal to each unit of the circuit in order to execute a designated operation.

In order to execute the audio signal input / output program of the control ROM 31 every predetermined time, this embodiment employs a timer interrupt. That is, the interrupt control unit 38 having a timer (hardware counter)
A control signal (interrupt request signal) is sent to the ROM address control unit 32 at regular intervals, and the ROM address control unit 32 saves (holds) the address of the next main program instruction by this signal, and Instead, the start address of the interrupt processing program (subroutine) to be input / output is set. Thereby, the interrupt processing program is started. At the end of the interrupt processing program, when the return instruction is decoded by the operation analysis unit 37, the ROM address control unit 32 sets the saved address again and returns to the main program. Although the interrupt control unit 38 is illustrated as an internal element of the microcomputer 1 (CPU) in the figure, the interrupt control unit 38 stops the work currently being performed on the microcomputer 1 and requests special processing. Logically, it is an external element (peripheral device) of the microcomputer 1.

The input port 41 and the output port 42 are used for key scanning of the switch unit 2.

A display command for the liquid crystal display 9 is output from the microcomputer 1. For driving the liquid crystal display 9, a dedicated driver is used as necessary (not shown).

The analog audio signal captured through the low-pass filters 5-1 to 5-n in the interrupt processing program is converted into a digital audio signal by the A / D converter group 44, and then input and stored in the audio storage RAM 3. Is done. The digital audio signal read from the audio storage RAM 3 by the interrupt processing program is converted into an analog audio signal by the D / A converter group 45, and then converted to the low-pass filters 6-1 to 6-1.
-N.

<Configuration of A / D Converter Group and D / A Converter Group> FIG. 3 shows a specific configuration of the A / D converter group 44. An audio signal of n channels (where n is 2, a stereo input can be obtained, and n can be increased to be a multi-track input) is sampled by an interrupt signal from the interrupt control unit 38. A / D via sample and hold circuits 441-1 to 441-n
It is provided to converters 442-1 to 442-n. Therefore, in the A / D converters 442-1 to 442-n, the input analog audio signal is A / D-converted completely in synchronization with the interrupt signal output in the sampling cycle. The digital audio signal is transmitted through gates 433-1 to 443-n (CH1 gate to CHn gate) that are controlled to open and close by a gate control signal output from the operation analysis unit 37 after data is determined by A / D conversion. It is sent to the voice storage RAM3.

FIG. 4 shows a specific configuration of the D / A converter group 45. The audio signal output for each channel is first latched by latches 451-1 to 451-n (CH1 latch to CHn latch) that perform a latch operation by a latch signal from the operation analysis unit 37.

These latched audio signals are completely synchronized with the interrupt signal output at the sampling period from the interrupt control unit 38, and are latched in the next stage.
Latched at -n (CH1 latch to CHn latch). The outputs of the latches 452-1 to 452-n are output from the corresponding D / A
The signals are supplied to converters 453-1 to 453-n, and are converted from digital signals to analog signals. Therefore, each D / A converter 453
The D / A conversion operations of −1 to 453-n completely match the sampling period (interrupt signal output period).

The A / D converter group 44 and the D / A converter group in FIGS.
45 can be an external circuit when it is difficult to integrate it into one chip on the microcomputer 1.
A / D converters and D / A converters use time-division multiplexing technology, even if they are not independent of the number of input / output channels or the number of tracks. Is 1 each
A / D converters and D / A converters
D conversion and D / A conversion can be performed. Alternatively, a converter that performs switching between one A / D conversion and a D / A conversion can be used. In this case, it is important that an analog signal is taken in synchronism with the generation of the interrupt signal and converted into a digital signal, or an analog signal corresponding to the digital signal is transmitted in synchronism with the generation of the interrupt signal. When the multiplexing technique is employed, the same function can be achieved for multiple channels by adding a latch circuit and a sample hold circuit.

<Overall operation of A / D conversion and D / A conversion> FIG. 5 schematically shows the overall operation of A / D conversion and D / A conversion of the present embodiment. In synchronization with the output of the interrupt signal every sampling time (every T time in the figure), the processing of the microcomputer 1 switches from the main processing to the interrupt processing as described later. By the way, as emphasized in FIG. 5, the timing at which the interrupt processing actually starts can generally vary. This is because the microcomputer 1 cannot immediately interrupt the operation being executed even if an external interrupt occurs,
After the execution is completed, an interrupt process is started. It is also possible to mask an interrupt while in a process that is not desired to be interrupted so that no interrupt processing is performed until a series of operations for the process is completed. The transition to interrupt processing thus depends on the currently running process.
Therefore, as will be described later, the audio signal read out from the audio storage RAM 3 by the interrupt processing in a time-division manner for each channel is first written into the latches 451-1 to 451-n in FIG. / A converter timing to output), latch with the next interrupt signal
452-1 to 452 -n to perform D / A conversion. Conversely, in the A / D converters 442-1 to 442-n in FIG.
Digital signals that have been A / D converted in synchronization with the arrival of the interrupt signal are captured in a time-division manner for each channel during the interrupt processing (see the timing in the column of input from the A / D converter to the microcomputer) Will be. Therefore, both the D / A conversion and the A / D conversion are performed completely in synchronization with the sampling period T.

Hereinafter, the main process (flow) and the interrupt process (flow) will be specifically described.

<Main Processing> FIG. 6 shows a flow of a main processing program of the microcomputer 1 of this embodiment, where A1 is an initial processing when the power is turned on.
Various initial settings such as clearing of the RAM (register group) 35 are performed. At A2, the microcomputer 1 outputs a signal for key scanning from the output port 42 and captures the state of the switch unit 2 from the input port 41, thereby storing the state of the function keys in the key buffer area of the RAM 35. A
In step 3, the mode set by the function key is determined. In this embodiment, the mode can be roughly divided into a sampler mode and a multi-track recorder mode.

If the sampler mode has been selected, the process proceeds to A4, and it is determined whether any of the statuses (sub mode) of record, edit, and play is currently set.

If the record status has been set, the process proceeds to A5, and the record condition is determined or changed. More specifically, the designation of the switch unit 2 sets which area (designated by the start address and the end address) of the audio memory RAM 3 to sample the audio signal or the sampling rate. Is done. According to this setting, the inside of the sampler input processing RAM table (see FIG. 9) of the RAM 35 is rewritten. The change of the sampling rate is realized by changing the generation cycle of the interrupt signal to the interrupt control unit 38. In the main flow, only the setting of these record conditions is performed, and the actual audio sampling operation is performed by an interrupt process. Therefore, if there is no change in the setting of this condition, in the main flow processing from the next time, there is no operation in A5, and the process immediately returns to A2. And sampling (record)
When the processing is completed, this mode is released.
As will be apparent from the following description, in this embodiment, a plurality of input channels (CH1 to CHn) can be used.
Not only stereo sampling can be performed, but also multi-sampling can be performed in parallel.

In the sampler mode, if the edit status is determined to be A4, the process proceeds to A6, where various editing processes are performed. The contents of the editing processing include setting a loop section of the sampled sound in advance, cutting unnecessary portions, setting parameters of an envelope (described later) to be added to the sampled sound, various types of processing, and the like. Or to determine pronunciation conditions. These various setting values are stored in a predetermined area of the RAM 35, and are read out and used as needed during play.

When set to play status in the sampler mode, proceed from A4 to A7, identify the function key whose state has changed from the new state of the function key obtained in A2 and the previous state, and execute the specified function. Do. For example, selection of an audio signal to be used for performance, selection of an envelope to be used, and the like. In A8, the operation of the keyboard included in the switch unit 2 is scanned, and the state of the keyboard keys is stored in the RAM 35.
To the keyboard buffer area. In A9, a key (key pressed, key released) changed from the latest state of the keyboard and the previous state is identified, and key assignment processing is performed.

One example of this key assignment is shown in FIG. As will be described later, there are N sound source channels,
One of the desired voices (musical sounds) from each of these for voice storage
It is possible to read from RAM 3 at a desired pitch. In the example of FIG. 10, two sound source channels are used for one key, and the outputs of one of the sound source channels (1, 3, 5, 7,...) Are added and synthesized, and the output channel CH1 to the speaker 8 are output. -1, and the outputs of the other sound source channels (2, 4, 6, 8,...) Are added and synthesized, and the sound is emitted from the output channel CH2 via the speaker 8-2. In this case, for example, for an odd number of sound source channels,
It is responsible for reading out the audio signal on the right side of the stereo sampled audio, and the speaker 8-1 functions as a right speaker. In addition, in the even-numbered sound source channels, reading of an audio signal on the left side of the stereo-sampled audio is performed, and the speaker 8-2 functions as a left speaker.

In addition to being able to take a play state as such a stereo type sampler, this embodiment has extremely high flexibility and can take various types of reproduction states depending on the key assignment method under condition setting.

In the following A10, various operations for actually generating a musical tone are performed according to the data set in the processing so far,
The result is stored in the sampler output processing RAM table (No.
12). The actual waveform signal read processing is executed in the interrupt flow.
At A10, various conditions are set. Further, in A10, in order to know the timing of an event required in the main flow, one round of the flow (this is obtained by counting the number of timer interrupts executed during one round of the flow. Is performed in an interrupt timer process B13 described later) to obtain a reference value of an envelope timer (envelope calculation cycle). Also, in A10, preparation processing for the next main flow pass is performed. Specifically, the NEW ON state indicating the change to the key pressed state obtained in this pass is set to ON,
This is processing such as changing the NEW OFF state indicating a change to the key release state to OFF.

Further, when the multi-track recorder mode is selected in the mode determination A3, the process proceeds to A11 to determine the status. In the multi-track recorder mode, input and output of audio signals of a plurality of tracks can be simultaneously executed in parallel. When the record / play status is determined, the process proceeds to A12, and the record / play condition is determined or changed. Specifically, the start and end addresses of the audio storage RAM 3 are determined for each track (input / output channel), the read (play) / write (record) state is determined for each track (input / output channel), Further, a sampling rate is determined (see FIG. 18). Such conditions are written in a multi-track recorder processing RAM table in the RAM 35 (see FIG. 17). Also in this case, the actual record / play operation is performed by an interrupt process.

When the edit status is determined by the status determination A11, the process proceeds to A13, where various editing processes are performed. Specifically, this A13 is used to cut a certain part of the selected track, connect audio data of a specific length after certain audio data, or synthesize a plurality of audio contents. Do.

When these processes are completed, the process returns to A2. Therefore, the main flow is repeated whether in the sampler mode or the multi-track recorder mode.

<Interrupt Processing> FIG. 7 shows a flow of an interrupt processing program that operates according to an interrupt signal output from the interrupt control unit 38 corresponding to a preset sampling period.

In B1, a mode judge is performed. If it is in the state of the sampler input (record), the process proceeds to B2 and samples the sound supplied from the outside. B2 to B5 are processes for input channels CH1 to CHn (input side in FIG. 1).
(Corresponding to CH1 to CHn), and each channel process
It is executed according to a specific program of the sampler input channel processing shown in the figure. The data used at that time is managed in a sampler input processing RAM table of the RAM 35 (FIG. 9). As is clear from FIG. 9, the use area (determined by the start address and the end address) of the audio storage RAM 3 is determined independently for each of the n channels.

At C1 in FIG. 8, the current address of the channel (the current address at the time of writing to the audio storage RAM 3) is incremented. At C2, the size of the incremented current address is compared with the end address of the channel. If the storage capacity still remains (when the current address is smaller than the end address), proceed to C3, and gate the audio data for one sample that has already been sampled and held and A / D converted when an interrupt signal is generated. The corresponding gates of 443-1 to 443-n are opened (see FIG. 3), fetched, written to the address of the voice storage RAM 3 specified by the current address in C 4, and processed for the next channel Move on. If the current address matches the end address in C2, the sampling operation of the channel is set to be stopped in C5, and the process proceeds to the next channel.

As described above, the cycle of the A / D conversion is performed completely in synchronization with the interrupt signal. Therefore, an analog signal having an audio frequency can be faithfully converted into a digital signal without distortion. Then, the digital signal is transferred and stored in the audio storage RAM 3 by the software processing of the microcomputer 1 as described above. Thus, the sampling processing of each of the channels CH1 to CHn is repeated and the processing is completed for all the channels. To return to the main flow. For input channels that are not sampling audio,
As a non-operation, processing for the next input channel is performed. This series of operation timings will become more apparent with reference to the overall operation in FIG.

Next, if the sampler is in the state of sampler output (play) during the interrupt processing, the process proceeds from B1 to B6, and an audio signal previously sampled in the audio storage RAM 3 is output as a musical sound signal. FIG. 12 shows the contents of a sampler output processing RAM table provided in the RAM 35, and is used for waveform addition in an area common to each of the N sound source channels (common use data for each sound source channel). The contents of the area outputs CH1 to CHn are cleared by B6. Each of the waveform addition areas corresponds to the output channels CH1 to CHn in FIG.
Corresponding to the content.

Subsequent B7 to B9 are the waveform generation processes of the N sound source channels, and the specific program flow is the eleventh channel.
This is shown in the figure as sampler output channel processing.
This channel processing is roughly divided into envelope processing (D1 to D7) and waveform processing (D8 to D21).

FIG. 13 shows an envelope generated by the envelope processing. The envelope of one musical tone consists of several steps (segments). In the figure, it is shown by four segments. In the figure, Δx is the sampling period of the envelope, and Δy is the change width of the envelope value. Channel envelope processing (D1 to D7)
In, the calculation of the envelope for each sampling time and the check of whether the target level of the step has been reached are performed. When the values match, the target value is set in the current envelope register (see FIG. 12). Therefore, the target value is detected in the sound generation processing A10 of the main program, and data (Δx, Δy, target (Envelope value) is set in each register.

More specifically, the timer register for comparing with the operation period Δx of the envelope is incremented in D1 for each interrupt, and when the value matches Δx in D2, the addition / subtraction flag (sign bit) of the data Δy corresponding to the envelope displacement is tested in D3. Then, it is determined whether the envelope is rising or falling, and the current envelope is subtracted or added at D4 and D5, respectively. At D6, check whether the current envelope has reached the target envelope value, and if so, set the target level to the current envelope. As a result, the data of the next envelope step is set in the sound generation processing A9 of the main program. In addition, pronunciation processing
When the current envelope of zero is read in A9, it is treated as the end of sound generation.

Next, the waveform processing D8 to D21 will be described. In the waveform processing, the waveform data of two adjacent addresses is read from the voice storage RAM 3 using the integer part of the current address, and the waveform value assumed for the current address represented by (integer part + decimal part) is interpolated. Seeking in. The reason why interpolation is necessary is that the waveform sampling period due to the interrupt is constant (using the fixed sampling method), and the added value of the address (pitch data) covers a certain range for musical instrument application (only the scale sound is output). If waveform data is prepared for each chromatic note with a musical instrument that does not need to be used, interpolation is not necessary, but an unacceptable increase in storage capacity occurs). Degradation of tone by interpolation,
Since the distortion is more remarkable in the high frequency range, the original sound is usually reproduced at a period faster than the recording sampling period of the original sound. 14th
In the example of the figure, the period of the original sound (A4) reproduction is doubled. Therefore, when the address addition value is 0.5, a sound of A4 can be obtained. In this case, the address addition value is 0.529 in A # 4, and is 1 in A3. These address addition values are stored as pitch data in the control ROM 31, and when the key is pressed, the pitch data corresponding to the key and the waveform start address, waveform end address, and waveform loop address of the selected tone are generated in the tone generation control A10. The corresponding registers of the RAM 35 are set in the address addition value register, the start address / current address register, the end address register, and the loop address register.

For reference, FIG. 15 shows the interpolated waveform data with respect to time. In the figure, white circles indicate waveform data values at the address of the audio storage RAM 3, and black circles indicate interpolation values.

Although there are various interpolation methods, linear interpolation is employed here. The waveform generation processing D8 to D21 in FIG. 11 will be described in detail. First, at D8, an address addition value is added to the current address to obtain a new current address. D9 compares the current address with the end address. If the current address is greater than the end address, then according to D10 and D11, and if the current address is less than the end address, according to D12. , And the voice storage RAM 3 is accessed by the integer part at D14 to obtain the next waveform data. The loop address (loop start address) is the address following the ed address in operation. That is,
In the case of FIG. 14, the illustrated waveform is repeatedly read. Of course, the loop address can be an arbitrary point (address at the center level). Therefore, when the current address is equal to the end address, the waveform data of the loop address is read as the next address (D13). According to D15 and D16, the audio storage RAM 3 is accessed with the integer part of the current address to read the current waveform data. Next, the current waveform value is subtracted from the next waveform value in D17, the difference is multiplied by the decimal part of the current address in D18, and the result is added to the current waveform value in D19, thereby obtaining a linear interpolation value for the waveform. Ask. This linearly interpolated data is multiplied by the current envelope value to obtain a tone data value of the channel (D20), which is then added to a waveform addition register (CH1 to CHn) corresponding to the output channel number.
(D21), in addition to the content of the selected one).

At the end of processing B7 to B9 for each sound source channel. B1
Output processing is performed for output channels CH1 to CHn of 0 to B12.

That is, since the waveform data generated by B7 to B9 are accumulated in the waveform addition areas CH1 to CHn according to the output numbers, respectively, the D / A converter group 4
5 are sequentially latched by the corresponding latches 451-1 to 451-n. The latch operation to the latches 451-1 to 451-n is switched at an unstable cycle due to program control. If the conversion cycle (sampling cycle) of the D / A converters 453-1 to 453-n is not very stable, a large distortion occurs in the conversion. For example, assuming that the machine cycle of the microcomputer 1 is tens of nanoseconds or hundreds of nanoseconds, the D / A converters 453-1 to 453-n output digital signals of audible frequencies even with the delay of one machine cycle. It is too far from the precision of the conversion period required to faithfully convert to an analog signal. In other words, even a shift on the order of nanoseconds causes distortion that can be perceived by human hearing.

Therefore, as shown in FIG. 4, a software control latch 451-1 to 451-n controlled by a program control signal from the operation analysis unit 37, and a D / A for converting a digital tone signal into an analog tone signal. Converter 453-1
To 453-n, there are provided interrupt control latches 452-1 to 452-n controlled by an interrupt signal which is a precise timing signal from the interrupt control unit 38. The generation period of the interrupt signal is extremely stable because it follows the stability of the clock oscillator. The outputs of the latches 452-1 to 452-n switch in synchronization with the timing of the interrupt signal. That is, the generation cycle of the interrupt signal is the conversion (sampling) cycle of the D / A converters 453-1 to 453-n. As shown in FIG. 5, the timing at which the outputs of the latches 451-1 to 451-n are switched varies according to the timing shift of the interrupt processing, but since there are latches 452-1 to 452-n which operate with the interrupt signal, the D / A is performed. Converter 453-1 to 45
The switching timing of the 3-n input data is synchronized with the interrupt signal. Due to the latches 452-1 to 452-n, the digital tone signals input to the D / A converters 453-1 to 453-n are delayed on average by one period of the interrupt signal, but this delay is a serious problem. Does not. For example, the period of an interrupt signal is 47 microseconds, and such a short delay is hardly perceptible to human hearing (usually, a few milliseconds is a perceptible limit).

In B13, an interrupt timer process is performed.
In other words, taking advantage of the fact that an interrupt is taken at regular intervals, the timer register for counting one cycle of the flow (RAM35
) Is increased by 1 each time it passes.

Next, a description will be given below of a case where the input / output operation mode of the multi-track recorder is set when an interrupt occurs. In this case, the processing of each channel (track) from B1 to B14 to B17 is executed.

The specific contents of each of the processes B14 to B17 are shown in FIG. 16, and the input and output of the audio signal can be controlled for each track. At the same time, it may be possible to input audio from another track. In the case of this embodiment, the track and the audio storage
Although the read / write channels of the RAM 3 are the same, they can be made different or programmable as necessary.

A multi-track recorder processing RAM table is formed in the internal RAM 35 of the microcomputer 1 as shown in FIG. As can be understood from FIG. 17, control data is set for each channel. Specifically, as shown in FIG. 18, in addition to parameters (start address, end address, current address) for determining the divided use state for each channel of the audio storage RAM 3, the corresponding channel is operated as a play (read) state. Or a read / write flag for determining whether to operate as a record (write) state. Where each channel CH
1 to CHn correspond to the input / output channels CH1 to CHn in FIG.

First, in E1 in FIG. 16, the audio recording
Increment the current address of RAM3. At E2, the current address is compared with the end address. If the current address has not reached the end address, the process proceeds to E3 to judge whether the channel is in a read state or a write state. If the channel is in the read state, the process proceeds to E4, where the content of the current address (one sample of audio data) of the channel in the audio storage RAM 3 is read, and the D / A
It is set to the latch of the corresponding channel among the latches 451-1 to 451-n of the converter group 45. The timing at which the set audio data is D / A converted is the same as the timing described in the operation in the sampler mode (see FIG. 5).

If it is judged in E3 that the corresponding channel is in the write state, the process proceeds to E6 and the gate 4 of the A / D converter group 44 is determined.
The gate of the channel is opened among 43-1 to 443-n to take in the audio signal which has already been A / D converted (see FIG. 5). To set the input.

If the current address matches the end address in E2, the operation of the channel is stopped in E7 assuming that the recording / reproduction of audio has stopped for the channel (track).

When the series of processes shown in FIG. 16 is completed, similar processes are performed for the next channel. here,
When the record / play operation is stopped for a specific track (channel), processing is performed for the next channel as a non-operation. When the processing of CH1 to CHn is completed, the interrupt processing ends, and the process returns to the main flow.

<Other Embodiments and Modifications> The description of the present embodiment is completed above, but various embodiments can be taken without departing from the scope of the invention. For example, in the above-described embodiment, the audio processing in the microcomputer 1 is performed by executing an interrupt processing program activated by an interrupt signal. However, by incorporating a dummy instruction (NOP instruction) into the program, the audio processing is performed at regular intervals. A process (a fixed time process) instead of the above-described interrupt process may be executed. That is, since the execution time of each instruction of each program is determined by the master clock, it can be executed by inserting a processing program as a subroutine for a fixed time for performing audio processing between a main program for a certain time.

At this time, if the processing time differs due to branching even within the processing for a fixed time, the time until the next jump to the processing for a certain time is not constant. For this reason, it is necessary to insert a dummy instruction for keeping the processing time required for the routes of all branches even within the processing for a fixed time. When such programming is performed, audio input / output processing can be performed for a fixed processing time, that is, for each sampling cycle.

Further, in the above embodiment, the sampler mode and
Although the multi-track recorder mode can be selectively used, it can be implemented as one of the dedicated devices, and furthermore, can be realized as a solid-state recording / reproducing device. At this time, the number of channels (the number of tracks) and the number of sound source channels (the number of polyphonics) can be set depending on the capability of the microcomputer.

Various types of microcomputers can be selected. In addition to the ROM / RAM / next address method shown in the embodiment, a general or general-purpose microcomputer such as a program counter (PC) method is adopted. obtain. In short, the present invention is applicable to all configurations in which the microcomputer itself performs the audio input / output processing under program control.

The read / write storage means for recording / reproducing the audio is RA
Various storage media other than M can be adopted. If necessary, replace RAM with external memory (magnetic tape, magnetic disk,
Input / output control can be performed on data on a readable / writable compact disc). Alternatively, the RAM itself may be a removable RAM card.

〔The invention's effect〕

According to the present invention, a so-called one-chip microcomputer having A / D conversion means, audio data storage means, and D / A conversion means in the same chip, a sampling recording device, a sampler output, if the sampler input mode is set. If it is set to the mode, it functions as a sampling and playback device, and if it is set to the multi-track recorder input / output mode, it functions as a recorder for recording and playback, so it is possible to change the device configuration in various ways even with the same hardware configuration it can.

Further, in the invention, when set to either the sampler output mode or the multi-track recorder input / output mode, the audio data is read from the audio data storage means in response to an instruction from the execution instruction means for issuing an execution instruction at regular intervals. The D / A converter outputs the read audio data in synchronism with the interrupt signal corresponding to the sampling period and outputs the audio signal through a two-stage latch. Thus, audio signal processing with less distortion can be realized without providing dedicated hardware.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention. FIG. 1 is an overall configuration diagram of an audio signal processing apparatus according to an embodiment of the present invention. FIG. 2 is an internal configuration diagram of the microcomputer of FIG.
FIG. 4 is a block diagram of the A / D converter group shown in FIG. 2, and FIG.
FIG. 5 is a configuration diagram of the D / A converter group shown in FIG. 5, FIG. 5 is a diagram showing the overall operation of D / A conversion and A / D conversion in a time chart, and FIG. FIG. 7 is a flowchart showing a program flow, FIG. 7 is a flowchart showing an interrupt processing program for performing voice input / output processing, and FIG. 8 is one processing channel at the time of sampler input in FIG. FIG. 9 is a flowchart showing the program of FIG. 9, FIG. 9 is a diagram showing the contents of a table configured in the internal RAM of the microcomputer when the sampler is input, and FIG. 10 is a diagram showing the relationship between the key and the sound source channel when the sampler is output. FIG. 11 is a diagram showing an assignment state and a relationship between a sound source channel and an output channel. FIG. 11 is a flowchart showing a specific program of one sound source channel process at the time of sampler output in FIG. FIG. 12, FIG. 12 is a diagram showing the contents of a table configured in the internal RAM of the microcomputer at the time of sampler output, FIG. 13 is a diagram showing the state of the envelope used at the time of sampler output, FIG. FIG. 1 is a diagram showing a waveform and a read state when stored in the audio storage RAM of FIG. 1, FIG. 15 is a diagram showing an interpolation state of the audio waveform, and FIG. 16 is a multi-track recorder mode of FIG. FIG. 17 is a flowchart showing one channel processing program for input / output of the microcomputer, FIG. 17 is a diagram showing the contents of a table configured in the internal RAM of the microcomputer in the multi-track recorder mode, and FIG. 18 is a multi-track recorder FIG. 7 is a diagram showing a divided use state for each channel of the audio storage RAM in the mode of FIG. DESCRIPTION OF SYMBOLS 1 ... Microcomputer, 2 ... Switch part, 3 ... RAM for voice storage, 31 ... ROM for control, 32 ... ROM address control part, 3
5 RAM (register group), 36 arithmetic circuit, 37 operation analysis unit, 38 interrupt control unit, 41 input port, 42 output port, 44 A / D converter group, 45 D / A conversion Instrument group, 441-1 to 441-n ... sample and hold circuit, 442-
1-442-n A / D converter, 443-1 to 443-n Gate circuit, 451-1 to 451-n Latch, 452-1 to 452-n Latch, 453-1 to 453-n ... D / A converter.

Claims (1)

(57) [Claims] A / D conversion means for converting an audio signal into audio data at a fixed sampling period and outputting the audio data, audio data storage means for storing the audio data, and a D / D converter for converting the audio data into an audio signal and outputting the audio signal. An apparatus comprising: a microcomputer having A conversion means in the same chip; and an interrupt signal generating means for generating an interrupt signal corresponding to the sampling period, wherein the microcomputer has a current setting for each predetermined period. Execution instruction means for discriminating the operation mode being executed, and instructing execution of the program means corresponding to the discriminated operation mode; and executing in accordance with an instruction from the execution instruction means when set to the sampler input mode, A first program for storing audio data input through the A / D conversion means in synchronization with the input signal in the audio data storage means; Means, which is executed in accordance with an instruction from the execution instruction means when the sampler output mode is set, and in accordance with an instruction from the execution instruction means, a voice stored in the audio data storage means in accordance with a pitch to be generated. Data reading, second program means for outputting the read audio data from the D / A conversion means in synchronization with the interrupt signal, and a second program means for outputting the read audio data from the execution instruction means when the multi-track recorder input / output mode is set. Executed in accordance with the instruction, the audio data input via the A / D conversion means in synchronization with the interrupt signal, is stored in the audio data storage means, and in response to an instruction from the execution instruction means, Reading the audio data stored in the audio data storage means,
Synchronize the read audio data with the interrupt signal and
And a third program means for outputting from the D / A conversion means.