JP3211696B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus having an image output unit for forming an image by scanning a plurality of beams at the same time. The present invention also relates to a device for converting the resolution of an input image to obtain output images of different resolutions.

[0002]

2. Description of the Related Art As a conventional image processing method for converting resolution, for example, Japanese Patent Publication No. 6-18433 discloses performing two-dimensional resolution conversion in real time. In this method, two adjacent pixels in a certain main scanning direction are held in a shift register, and two
The resolution in the main scanning direction is converted and stored in the first line memory by performing an interpolation operation between pixels, and the same resolution in the main scanning direction is converted for the next one main scanning line. 2 is stored in the line memory.
By performing an interpolation operation while reading the first line memory and the second line memory, image information of a new line generated by interpolation is sequentially output in series. By repeating such operations, two-dimensional resolution conversion is performed in real time.

Further, a multi-beam scanning method for performing high-speed operation using a plurality of light beams when scanning a light beam in an image forming apparatus has been conventionally known. For example, JP
Japanese Patent Application Laid-Open No. 8-145914 discloses an image processing method for converting data transferred in units of one line into a plurality of beams (two beams) for output. The method includes first and second two control units, the first control unit includes first and second two line memories, and the second control unit includes third and fourth control units.
, And the first and second control units alternately perform writing and reading to and from the line memory. That is, the signals of two adjacent scanning lines of the image signal are written into the first and second line memories of the first control unit during the first period, and the third and fourth signals of the second control unit are simultaneously written. Information is read out in parallel from the line memories. Conversely, during the second period, the storage information is read out in parallel from the first and second line memories of the first control unit and output, and continues to the third and fourth memories of the second control unit. Write signals for two scan lines. In this way, by outputting information for two scanning lines to the line memory while buffer-linking, conversion for outputting a plurality of beams is performed.

[0004]

In the field of image processing apparatuses, there is a case where resolution conversion of image information is performed and a plurality of lines of the converted output are simultaneously output for a multi-beam operation type output apparatus. Can be In that case, it can be easily realized by combining the above two conventional techniques. That is, after performing the conventional resolution conversion, the conventional conversion for multiple beam output may be performed. However, according to such a method, since the resolution conversion processing and the conversion processing for outputting a plurality of beams must be performed in series, the configuration becomes complicated, the manufacturing cost increases, and the data transfer rate increases. The problem that it cannot be done arises. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has a relatively simple configuration of an image processing apparatus that performs resolution conversion of image data and conversion of the number of transfer lines. Is the subject.

[0005]

The present invention provides means (11) for inputting first image data in units of n lines.
Means (12 to 16) for performing high resolution processing on the first image data and converting n-line transfer to m (where m> n) line transfer to generate second image data;
Means (17) for forming a second image by scanning the second image data sent by the line transfer with m beams. The means for generating the second image data performs a high-resolution processing such that the output of the high-resolution processing is m lines. It has a line memory for holding lines. Specifically, the high resolution processing includes resolution conversion in the main scanning direction and resolution conversion in the sub scanning direction. After performing resolution conversion in the main scanning direction, resolution conversion in the sub scanning direction and line transfer are performed. Conversion may be performed, or resolution conversion in the main scanning direction may be performed after resolution conversion and line transfer conversion in the sub-scanning direction. In the present invention, the second
Means for generating the image data of (a), the line memory used for the high-resolution processing is set to have a capacity of a plurality of lines required for the high-resolution processing of m-line output, and the output of the high-resolution processing is m lines. Since the configuration is such that high resolution processing is performed, high resolution processing and conversion from n-line transfer to m-line transfer can be performed at a time. Therefore, the present invention can reduce the circuit configuration and increase the data transfer rate as compared with the case where the resolution conversion is performed and then the number of transfer lines is converted as in the prior art. Can be.

According to another aspect of the present invention, there is provided an image processing apparatus comprising:
Image input means (11) for inputting first image data in units of n lines, first conversion means (12) for performing high-resolution conversion processing in the main scanning direction, and output in m lines in the sub scanning direction. A line memory (13 to 15) having a capacity required for resolution conversion and holding a plurality of lines of image data after the main scanning resolution conversion by the first conversion means; and a plurality of lines of image data stored in the line memory. By generating an m-line image data by performing an interpolation operation using
A second conversion unit (16) for simultaneously performing the sub-scanning resolution conversion and the transfer line number conversion;
An image output means (17) for forming a second image by scanning the second image data sent by the line transfer with m beams is provided. The present invention relates to the first
After the resolution conversion in the main scanning direction is performed by the conversion device, the converted output is held in the line memory. The second conversion device performs resolution conversion in the sub-scanning direction using the image data of a plurality of lines stored in the line memory. The conversion is configured so that output in m lines is possible, and m is stored in the line memory.
The image data of the number of lines necessary to convert the resolution of the line output is held. According to the present invention, as described above, the line memory used for the high-resolution processing is secured with a capacity of a plurality of lines required for the high-resolution processing for m-line output,
Since the high-resolution processing is performed such that the output of the high-resolution processing is m lines, the high-resolution processing and the conversion from n-line transfer to m-line transfer can be performed at a time. Therefore, the present invention can reduce the circuit configuration and increase the data transfer rate as compared with the case where the resolution conversion is performed and then the number of transfer lines is converted as in the prior art. Can be.

In the above-mentioned image processing apparatus of the present invention, in one specific mode, the first conversion means performs an odd-numbered pixel conversion after resolution conversion by an interpolation operation of adjacent S pixels (S ≧ 1). And even-numbered pixels at the same time,
These are output in parallel. According to the present invention, the image data can be transferred in parallel for every two pixels, so that the transfer speed of the image data can be substantially increased.

[0008] In one embodiment of the image processing apparatus of the present invention, the second conversion means outputs m lines corresponding to the number m of output lines in order to output by m-line transfer.
Conversion operation units (an operation unit including 741 to 743, 751, 761 and an operation unit including 744 to 746, 752, 762).

An image processing apparatus according to still another aspect of the present invention comprises an image input means (101) for inputting first image data in n-line units, and a capacity required for sub-scanning resolution conversion for outputting in m-line units. And a line memory (103 to 103) for storing a plurality of lines of image data from the image input means.
105), and performing an interpolation operation using a plurality of lines of image data stored in the line memory to generate m-line image data, thereby simultaneously performing sub-scanning resolution conversion and transfer line number conversion. Conversion means (106)
And second conversion means (102) for performing high-resolution conversion processing in the main scanning direction for each line of the m-line image data output from the first conversion means to generate second image data.
And an image output means (107) for forming a second image by scanning the second image data sent from the second conversion means by m-line transfer with m beams. Features. In the present invention, the order of main-scanning resolution conversion and sub-scanning resolution conversion is reversed from that of the above-described invention, but the overall operation and effect are the same, and the circuit configuration can be reduced in scale. In addition to that, it is possible to increase the data transfer rate.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(First Embodiment) FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to a first embodiment of the present invention. The image processing apparatus includes an image input unit 11 for inputting an image obtained by scanning a document image in units of n lines (in the embodiment, one line), and a main scanning resolution converter for converting a resolution of the input image in a main scanning direction. Unit 12, a FIFO (first-in first-out memory) for holding image data of a scanning line referred to in a resolution conversion process of a sub-scanning resolution conversion unit 16 described later
And a write control unit 1 for controlling writing of the line memory 13 to the FIFO.
4. a FIFO read control unit 15 for controlling reading from the FIFO of the line memory 13; a sub-scanning resolution conversion unit 16 for converting the resolution in the sub-scanning direction and performing line conversion;
And an image output unit 17 configured to output an image using a plurality of beams. Sub-scanning resolution converter 1
Reference numeral 6 denotes m beams (2 in this example) at the image output unit 17.
This is configured so that it can be output in m-line units to match the output.

FIG. 2 is a block diagram showing details of the main scanning resolution converter 12. The main scanning resolution conversion unit 12 extracts calculation target pixels for simultaneously extracting a plurality of adjacent pixels (three pixels in this example) necessary for the main scanning resolution calculation of the image information of the main scanning line from the image input unit 11. A first circuit for calculating an odd-numbered pixel after resolution conversion by an interpolation operation based on a circuit and an operation target pixel extracted by the operation target pixel extraction circuit;
And a second calculation unit 23 that calculates an even-numbered pixel after resolution conversion by interpolation based on the calculation target pixel extracted by the calculation target pixel extraction circuit 21. The calculation target pixel extraction circuit 21 includes a latch circuit 211 that delays an input pixel by one pixel, and a latch circuit 212 that delays the output of the latch circuit 211 by one pixel. The first arithmetic unit 22 includes multipliers 221 and 222 that multiply the pixel output from the arithmetic target pixel extraction circuit 21 by an interpolation coefficient.
223, a coefficient switching unit 224, and multipliers 221-2.
An adder 225 for adding the outputs of the 23 is provided. or,
The second operation unit 23 is a multiplier 23 that multiplies the pixel output from the operation target pixel extraction circuit 21 by an interpolation coefficient.
2, 233, a coefficient switching unit 234 for even-numbered pixels, and an addition unit 235 that adds the outputs of the multipliers 232 and 233.

Latch circuit 2 of operation target pixel extraction circuit 21
11 and the latch 212 each delay one pixel, so that the latch circuit 212
11, three consecutive pixels are obtained in which the (r-1) -th pixel and the pixels from the image input unit 11 that do not pass through the latch circuit are the (r-2) -th pixels. That is, the calculation target pixel extraction circuit 2
1 can simultaneously obtain three consecutive pixels on one line (scanning line) and supply it to the multiplier group. In FIG. 3A, the first row is a pixel column of the input image to the multipliers 223 and 233, and the second row is from the latch circuit 211 to the multiplier 22.
2 and 232, the pixel columns input to the third and third rows are latch circuits 2
12 shows a pixel column input to the multiplier 221 from 12. At timing t2, pixel 2 is obtained on the input side of multipliers 223 and 233, and pixel 1 is obtained on the input side of multipliers 222 and 232. After the timing t3, the multiplier 2
Three pixels adjacent in the main scanning direction to 21, 222, 223 and multipliers 232, 233 are obtained at the same time.

Multipliers 221 to 223, coefficient switching unit 2
., P-1, P before conversion, the odd-numbered output pixels 1 ′, 3 ′ whose resolution has been converted by an arithmetic circuit including the pixel 24, and an adder 225. .., Q-1. Multipliers 209 and 210, coefficient switching unit 211 for even pixels,
And an arithmetic circuit including the adder 212,
.., P-1, P before conversion, an output image consisting of even-numbered output pixels 2 ′, pixels 4 ′. An example of resolution conversion by a two-point interpolation operation when the resolution is multiplied by 1.5 will be described below. Note that the resolution conversion method is known, and any other interpolation method such as interpolation between four points can be adopted.

Pixel value of pixel 1 '= (5/6) × pixel value of pixel 1+ (1/6) × pixel value of pixel 2. Pixel value of pixel 2 '= (1/6) × pixel value of pixel 1+ (5
/ 6) × pixel value of pixel 2. Pixel value of pixel 3 ′ = (（) × pixel value of pixel 2+ (1
/ 2) × pixel value of pixel 3. Pixel value of pixel 4 ′ = (5/6) × pixel value of pixel 3+ (1
/ 6) × pixel value of pixel 4. Pixel value of pixel 5 ′ = (（) × pixel value of pixel 3+ (5
/ 6) × pixel value of pixel 4. Pixel value of pixel 6 ′ = (１ ／) × pixel value of pixel 4+ (1
/ 2) × pixel value of pixel 5. Pixel value of pixel 7 ′ = (5/6) × pixel value of pixel 5+ (1
/ 6) × pixel value of pixel 6. Pixel value of pixel 8 '= (1/6) × pixel value of pixel 5+ (5
/ 6) × pixel value of pixel 6. Pixel value of pixel 9 ′ = (１ ／) × pixel value of pixel 6+ (1
/ 2) × pixel value of pixel 7. ............

In the multiplier 221 for odd output pixels, FIG.
As shown in (b), the input pixel is multiplied by a coefficient 0 at the timing of obtaining the pixels 1 ′, 7 ′, 13 ′..., And the input pixel is multiplied by the coefficient at the timing of obtaining the pixel pixels 3 ′, 9 ′, 15 ′. Multiply by 1/2, pixels 3 ', 9', 1
At the timing of obtaining 5 ′...
Multiply by 6. In the multiplier 222, the pixels 1 ′, 5 ′,
The input pixel is multiplied by 5/6 at the timing of obtaining 7 ', 11', 13 '..., And the input pixel is multiplied by the coefficient 1/6 at the timing of obtaining the pixels 3', 9 ', 15'. The multiplier 223 multiplies the input pixel by 1/6 at the timing of obtaining the pixels 1 ′, 7 ′, 13 ′,.
The input pixel is multiplied by a coefficient 0 at the timing of obtaining the pixels 3 ′, 5 ′, 9 ′, 11 ′. The coefficients to be multiplied by the multipliers 221, 222, and 223 for odd output pixels as described above are sequentially switched by the coefficient switching unit 224.

In the multiplier 209 for an even output pixel, FIG.
As shown in (c), the input pixel is multiplied by a coefficient 1/6 at the timing of obtaining the pixels 2 ′, 8 ′, 14 ′,.
The input pixel is multiplied by a coefficient 5/6 at the timing of obtaining the pixels 4 ′, 10 ′, 16 ′,.
At the timing of obtaining 2 ′, 18 ′,..., The input pixel is multiplied by a coefficient １ ／. Multiplier 210, pixel 2 ',
8 ′, 14 ′... Are multiplied by a coefficient 5/6 at the input pixel to obtain pixel pixels 4 ′, 10 ′, 16 ′.
Are multiplied by the coefficient １ ／ at the timing of obtaining the pixel, and the coefficient １ ／ is multiplied by the input pixel at the timing of obtaining the pixels 6 ′, 12 ′, 18 ′. Coefficient multiplying in the multiplier 232, 2 33 for the even output pixel as described above is switched sequentially by the even-numbered pixel coefficient switching unit 2 34.

In the adder 225, the multipliers 221 to 223
Each odd-numbered pixel is obtained by adding the values obtained in (1). For example,
The adder 225 calculates the pixel value of the pixel 1 ′ by:
The pixel value of (5/6) × pixel 1 output from the multiplier 222 and the pixel value of (1/6) × pixel 2 output from the multiplier 223 are added. In the adder 235 , the multipliers 2 32 , 2 3
Each even pixel is obtained by adding the values obtained in step 3 . For example, in order to obtain the pixel value of the pixel 2 ', output of the multiplier 2 32 (1/6) × outputs the pixel 1 and the multiplier 2 33 (5/6) the sum of the pixel values of × pixels 2 I do.

The odd-numbered pixels 1 resolution conversion result output by the adder 225 ', 3', 5 ', ... and even-numbered pixels 2 output by the adder 2 35', 4 ', ...
Are output in parallel as a pair as shown in FIG. When the pixel value is represented by 8 bits, 8 bits of the odd-numbered pixels and 8 bits of the even-numbered pixels are concatenated by simultaneously outputting them in parallel, and are stored in FIFO1 and FIFO3 of the line memory 13 as data having a width of 16 bits. Is done. FIFO1, is to FIFO3 written in FIG. 3 FIFO1 the write enable signal of the FIFO write control unit 14, such as the output of the adder 225 and the 2 35 as shown in (d) is shown in FIG. (E), FIFO3, the Data as shown in FIG. 7F is held in each FIFO. In this example, the odd pixels and the even pixels are
The reason why the signals are held in parallel to O and transmitted in parallel is to allow the output system to sufficiently follow even when the speed of the output system is high.

FIG. 4 shows another example of a coefficient for performing resolution conversion by interpolation between two points. The way to read the figure is the same as in FIG. In this case, the multiplier 22 shown in FIG.
3 can be omitted.

FIGS. 5A to 5K show the line memory 13.
FIG. 4 is a diagram for explaining control of writing and reading to a sub-scan, sub-scan resolution conversion, and transfer line number conversion. FIG.
The image after the main scanning resolution conversion of (b) (see FIG. 3D) is written into the FIFO 1 of the line memory 13 of FIG. 1 by the FIFO1 write signal of FIG. 5C. FIFO1
The write signal is not generated at the lines 3, 7, 7,. Those lines 3 in FIG.
In response to the FIFO3 write signals generated at the positions corresponding to the lines 7, 11,..., The respective signals are written to the corresponding FIFO3. FIG. 5 shows FIFO2.
The output of FIFO1 is written by the FIFO write signal shown in (e).

As described above, the FIFO of the line memory 13
The image signals of a plurality of adjacent lines in the sub-scanning direction written in 1 to 3 are read by the FIFO read signal of FIG. 5F and supplied to the input of the sub-scanning resolution conversion and transfer line number conversion unit 16. You. FIGS. 5 (g) to 5 (k)
The data read from the FIFOs 1 to 3 and a plurality of line data generated by performing the resolution conversion in the sub-scanning direction and the transfer line number conversion therefrom are shown over time.
FIG. 6 shows the relationship between the line before conversion and the line after conversion. Note that, in FIG. 6, the pre-conversion line at the top of the figure and the pre-conversion line at the bottom are the same, and are overlapped for easy viewing of the figure.

The first line data from FIFO2 is
The data of the second line is read from the FIFO1, and the data of the line after the conversion of the first line and the second line is generated. The next FIFO read signal causes the FIFO
The data of the fourth line from O1 and the second data from FIFO2
The line data is read from the FIFO 3 to the third line data, and the second line data and the third line data are read.
Generate 3'line after conversion from line data,
A converted third line is generated from the third line data and the fourth line data. Further, in response to the next FIFO read signal, the fifth line data from FIFO1 and the fourth line data from FIFO2
The third line data is read from the third line, the converted fifth line is generated from the read third line data and the fourth line data, and the fourth line is generated.
6′l after conversion from the data of the 5th line and the data of the 5th line
generate ine. While repeating such operations,
Resolution conversion in the sub-scanning direction and conversion of the number of transfer lines are performed according to the relationships shown in FIGS. The line memory used for the high-resolution processing has a capacity of three lines, FIFO1 to FIFO3, necessary for the high-resolution processing of 2 (ie, m = 2) line outputs, and the output of the high-resolution processing is two lines. In this embodiment, the resolution is increased and the n-line transfer is performed.
line transfer) to m-line transfer (2 lin in this embodiment)
e-transfer) can be performed at the same time.

FIG. 7 schematically shows the structure of the apparatus for performing the above-described sub-scanning resolution conversion and transfer line number conversion. The register 721 holds pixels sequentially output from each FIFO by FIFO read lock. ~ 72
3. Selectors 731 to 733 for separating pixels held in parallel in the register, multipliers 741 to 743 for performing resolution conversion and transfer line number conversion for generating odd lines, and even lines Multipliers 744-for performing resolution conversion for generation and conversion of the number of transfer lines
746, coefficient switching units 751, 752 and addition 76
1,762.

FIG. 8 shows pixels sequentially read from the FIFO by the FIFO read clock and a group of pixels of a converted line generated from the pixels. The two pixels connected in parallel and held in each FIFO are read out to the registers 721, 722, and 723 by the FIFO read clock. The two parallel pixels in the register are the selector 73
Pixels are selected one by one by 1,732,733 and supplied to multipliers 741,742,743. That is, the selectors 731, 732, and 733 store the registers 721, 72
2, 723 are converted to serial pixels and output.

The operation for sub-scanning resolution conversion is similar to the operation for main resolution conversion. According to the scan line information held in the FIFOs 1 to 3, the scan line information after each conversion is calculated from the plurality of scan line information before conversion in a relationship according to FIG. The conversion generates two (generally m) scanning line information at the same time and outputs them at the same time, thereby simultaneously converting a plurality of lines. As shown in FIG. 6, the first line and the second
1 ′, which is an odd line after conversion from the image information
The image information of the second line which is the line and the even line is calculated. The operation to obtain the odd line after conversion is
The pixel value of the corresponding pixel of the two lines (selector 73
The 8-bit information output from 1 to 733 is multiplied by a predetermined coefficient by multipliers 741 to 743 and added by an adder 761 to obtain a pixel value of a corresponding pixel in the line after resolution conversion. Do it by getting. The operation for obtaining the even-numbered line after the conversion is performed by multiplying the pixel values of the corresponding pixels of the two lines by predetermined coefficients by multipliers 744 to 746.
This is performed by multiplying by the glue and adding them by the adder 762 to obtain the pixel value of the corresponding pixel.

That is, as shown in FIG.
Is the pixel value of the first line × (coefficient 5/6) +
It is determined by calculating the pixel value of the second line × (coefficient 1/6). The pixel value of the first line × (coefficient 5/6) is calculated by the multiplier 742, and the pixel value of the second line × (coefficient 1/6)
Is performed by a multiplier 741, and addition of these multiplication results is performed by an adder 761. The pixel value of the second 'line is the first
The pixel value of the line × (coefficient 1/6) + the pixel value of the second line × (coefficient 5/6) is obtained. The pixel value of the first line × (coefficient 1/6) is calculated by the multiplier 745, and the second line
The calculation of the pixel value of ne × (coefficient 5/6) is performed by the multiplier 744, and the addition of these multiplication results is performed by the adder 762.
The pixel value of the third line is the pixel value of the second line ×
(Coefficient 1/2) + pixel value of third line × (coefficient 1 /
Determined by 2). Pixel value of second line × (coefficient 1 /
The multiplication of 2) is performed by the multiplier 742, and the multiplication of the pixel value of the third line × (the coefficient ２) is performed by the multiplier 743.
The pixel value of the fourth line is the pixel value of the third line ×
(Coefficient 5/6) + pixel value of fourth line × (coefficient 1 /
6), and the pixel value of the third line × (coefficient 5)
/ 6) is performed by the multiplier 746, and the fourth line
The calculation of pixel value × (coefficient 1/6) is performed by the multiplier 744. The pixel value of the fifth line is the pixel value of the third line ×
(Coefficient 1/6) + pixel value of fourth line × (coefficient 5 /
6), the pixel value of the third line × (coefficient 1)
/ 6) is performed by the multiplier 743, and the fourth line
The calculation of the pixel value × (coefficient 5/6) is performed by the multiplier 742. The pixel value of the sixth line is the pixel value of the fourth line × (coefficient 1/2) + the pixel value of the fifth line × (coefficient 1 /
2), and the pixel value of the fourth line × (coefficient 1)
/ 2) is performed by the multiplier 745, and the fifth line
The calculation of pixel value × (coefficient １ ／) is performed by the multiplier 744. The adders 761 and 762 simultaneously output odd-numbered pixel lines and even-numbered lines for each corresponding pixel.

The first to sixth lines described above.
The image resolution conversion can be performed by periodically repeating the conversion operation for obtaining the ine for each of the next 6 lines. Since the odd lines and the even lines are output simultaneously, the line number conversion can be performed at the same time.

FIG. 8 is a diagram for explaining the relationship between pixels on a line held in the FIFO and pixels on a plurality of lines after conversion. When the odd-numbered pixels 1-1 ′, 2-1 ′, and 3-1 ′ are output from the selectors 731, 732, and 733, each of the arithmetic units performs an odd-line output pixel o-1 and an even-line output pixel e−. 1 is generated. Selectors 731 and 73
2, 733 to even pixels 1-2 ', 2-2', 3-2 '
Are output, each operation unit generates a pixel o-2 having an odd line output and a pixel e-2 having an even line output.

In the above description, an example was given in which the main-scanning resolution and the sub-scanning resolution conversion using two-point interpolation were increased by a factor of 1.5. However, other known resolution conversion methods can be employed. Also, it goes without saying that the resolution conversion magnification is not limited to 1.5 times, but can be any resolution. For example, when the resolution is doubled in the resolution conversion using the two-point interpolation, as shown in FIG. 9A, two adjacent lines are stored in a line memory (FI).
FO), and converted to a converted line in a reference relationship as shown in FIG.

In the above description, the input is in units of one line (ie, n = 1) and the output is in units of two lines (ie, m = m).
Although the example of the line number conversion of 2) has been described, the present invention is not limited to this, and an arbitrary number of output lines can be obtained.

The image processing apparatus shown in FIG. 1 is configured to perform the sub-scanning resolution conversion and the transfer line number conversion after the main scanning resolution conversion. However, by changing this, as shown in FIG. A similar result can be obtained even if the scanning resolution conversion and the transfer line number conversion are performed first, and then the main scanning resolution conversion is performed. That is, as shown in FIG. 10, three lines of image information from the image input unit 101 are held in the line memory 103, and the sub-scanning resolution conversion and the transfer line number conversion unit are performed based on the held line information. At 106, resolution conversion and line number conversion are performed. The sub-scanning resolution conversion and transfer line number conversion unit 106 has substantially the same configuration as that of FIG. 7, but the input is different from the example of FIG. Since the data is sent from the line memory 103 in the width, the selector 731 for parallel / serial conversion is not necessary because it is not necessary. The operation is exactly the same as the configuration of multipliers 741 to 746, coefficient switching units 751 to 752, and adders 761 to 762 in FIG. Main scanning resolution converter 10
Reference numeral 2 includes a first resolution conversion unit 1021 for odd lines having substantially the same configuration as the main scanning resolution conversion unit 12 of FIG. 2, and a second resolution conversion unit 1022 for even lines having the same configuration. The difference from the configuration of FIG.
The point is that the output of the first arithmetic unit 22 (FIG. 2) and the output of the second arithmetic unit 23 (FIG. 2) in 1022 can be output alternately instead of in parallel. For this purpose, the first resolution conversion unit 1021 for odd-numbered lines uses two odd-numbered lines for S.
It has RAMs 108A and 108B, and writes the output of the first arithmetic unit 22 to the SRAM 108A.
The output from the AM 108B to the image output unit 107 and the output of the second arithmetic unit 23 are written to the SRAM 108B at the next point in time.
07. Similarly, the second resolution conversion unit 1022 for the even-numbered lines includes two odd-numbered SRAMs 109.
A, 109B and the output of the first arithmetic unit 22 is SRA
When writing to M109A, SRAM 109B
To the image output unit 107, and at the next point in time, while the output of the second arithmetic unit 23 is being written to the SRAM 109B, the data is output from the SRAM 109A to the image output unit 107.

According to the embodiment of the present invention described above, when a plurality of lines are generated from a plurality of adjacent lines in the sub-scanning direction to convert the resolution, a plurality of lines are generated at the same time. Output
Real-time resolution conversion and transfer line number conversion of image data can be performed at one time, making the configuration simpler and producing at relatively low cost compared to the conventional technology that performed resolution conversion and transfer line number conversion separately. Can be
Further, a high data transfer rate can be realized.

[0033]

According to the present invention, resolution conversion of image data and conversion of the number of transfer lines can be realized with a relatively simple configuration, manufacturing can be realized at low cost, and high-speed data transfer can be achieved. Can be realized at a rate.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image processing apparatus according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a configuration example of a main scanning resolution conversion unit;

FIG. 3 is a diagram for explaining the operation of a main scanning resolution conversion unit;

FIG. 4 is a diagram for explaining an operation of a modification of the main scanning resolution conversion unit;

FIG. 5 is a waveform chart for explaining control of a line memory.

FIG. 6 is a diagram illustrating a relationship between a line of an image after conversion and a line of an image before conversion;

FIG. 7 is a diagram showing a configuration of a sub-scanning resolution converter and an output line number converter.

FIG. 8 is a view for explaining the relationship between pixels on a line held in a FIFO and pixels on a plurality of lines after conversion;

FIGS. 9A and 9B are diagrams showing a relationship between lines of an image after conversion and lines of an image before conversion when the resolution is converted from 600 dpi to 1200 dpi.

FIG. 10 is a block diagram showing a schematic configuration of an image processing apparatus according to another embodiment of the present invention.

[Explanation of symbols]

11: image input unit, 12: main scanning resolution conversion unit, 13:
Line memory, 14 ... FIFO write control unit, 15 ... F
IFO read control unit, 16: sub-scanning resolution conversion and transfer line number conversion unit, 17: image output unit, 21: calculation target pixel extraction circuit, 211, 212: latch circuit, 22: first calculation unit, 221-223 ... Multiplier, 224 ... Coefficient switching unit, 225 ... Adder, 23 ... Second arithmetic unit, 72
1 to 733... Register, 731 to 733.
41 to 743: multiplier, 75: coefficient switching unit, 76 ...
Adder.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-146061 (JP, A) JP-A-4-361217 (JP, A) JP-A-6-40071 (JP, A) JP-A-5-205 177867 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) B41J 2/44 G02B 26/10 H04N 1/387 G03G 15/04 G03G 15/22 G09G 5/391

Claims (7)

(57) [Claims] 1. A both means for the first image data inputs of n units of lines when the first image data processing high resolution, converts the n line transfer m (provided that, m> n) to line transfer Means for generating second image data by scanning the second image data sent by m-line transfer with m beams to form a second image. Means for performing the high-resolution processing so that the output of the high-resolution processing becomes m lines, and a line holding a plurality of lines required for the high-resolution processing of the m-line output An image processing device having a memory. 2. The high-resolution processing includes resolution conversion in the main scanning direction and resolution conversion in the sub-scanning direction. After performing resolution conversion in the main scanning direction, resolution conversion in the sub-scanning direction and line transfer conversion are performed. The image processing device according to claim 1. 3. The high-resolution processing includes resolution conversion in the main scanning direction and resolution conversion in the sub-scanning direction. After performing resolution conversion in the sub-scanning direction and line transfer conversion, resolution conversion in the main scanning direction is performed. The image processing device according to claim 1. 4. An image input means for inputting first image data in units of n lines, a first conversion means for performing resolution conversion in the main scanning direction, and a resolution conversion for outputting m lines in the sub scanning direction. A line memory having a large capacity and holding a plurality of lines of image data after the main scanning resolution conversion by the first conversion means; and performing an interpolation operation using the plurality of lines of image data stored in the line memory. second conversion means for simultaneously performing sub-scanning resolution conversion and transfer line number conversion by generating m-line image data; and second image data transmitted by m-line transfer from the second conversion means. And an image output unit for forming a second image by scanning the image with m beams. 5. The first conversion means simultaneously generates odd-numbered pixels and even-numbered pixels after resolution conversion by interpolation of adjacent S pixels (S ≧ 1), 5. The image processing apparatus according to claim 4, wherein the image is transferred. 6. The image processing apparatus according to claim 4, wherein said second conversion means includes m conversion operation units corresponding to the number m of output lines, for outputting by m-line transfer. . 7. An image input means for inputting first image data in units of n lines, and a capacity required for sub-scanning resolution conversion for outputting in units of m lines, and a plurality of lines of image data from the image input means. A line memory for holding, and performing an interpolation operation using image data of a plurality of lines stored in the line memory to generate m-line image data, thereby simultaneously performing sub-scanning resolution conversion and transfer line number conversion. A second conversion unit that performs main-scanning resolution conversion for each line of the m-line image data output from the first conversion unit to generate second image data; An image processing apparatus, comprising: image output means for forming a second image by scanning the second image data sent from the conversion means by m-line transfer with m beams.