JP3207057B2 - Synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizer for a receiver which detects and corrects a clock deviation from a transmitter and corrects the shift. More particularly, the synchronizer operates properly without being affected by the reception state. is there.

[0002]

2. Description of the Related Art In recent years, digitization of communication has been progressing at a remarkable rate. In communication equipment, it is difficult to accurately match the fundamental frequency of the transmitter with the fundamental frequency of the receiver. Therefore, a known pattern is added to the transmission signal and transmitted.
The receiving side detects the known pattern to detect a clock difference between the transmitter and the receiver, and adjusts the fundamental frequency of the receiver to the transmitting side. For this reason, a circuit for detecting a clock difference and a circuit for performing timing correction are very important.

FIG. 11 shows an example of a conventional synchronizer having a clock difference detecting function. This device stores an A / D converter 1 for A / D converting an orthogonal component of a received signal, an A / D converter 2 for A / D converting an in-phase component of the received signal, and stores the converted digital data. A memory A3, a memory B5 storing a known signal pattern, a complex correlator 4 for calculating a complex correlation between a signal stored in the memory A3 and a signal stored in the memory B5, and a complex correlator 4 A comparison circuit 6 for comparing the obtained correlation result with a threshold value, a memory C8 for storing the comparison results output from the comparison circuit 6 in different areas sequentially, and a changeover switch 7 for allocating a storage position of the comparison result in the memory C8. And a timing difference detection circuit 9 for detecting a timing deviation from the difference between the actual reception time of the known pattern and the reception time of the known pattern assumed by the receiver.

A / D converters 1 and 2 of this device, memory A
3 and the complex correlator 4 operate in synchronization with the operation timing A, the changeover switch 7 operates in synchronization with the operation timing B, and the timing difference detection circuit 9 operates in synchronization with the operation timing C.

In this synchronizer, a reception signal and a memory B5 are detected in order to detect the reception time of a known transmission pattern.
The complex correlator 4 obtains a complex correlation with a known pattern stored in. The result of this complex correlation operation takes a value close to 1 when the timing is correct, and has a substantially symmetrical shape around the time when the timing is the best when the timing is shifted forward or backward.

[0006] The result of the complex correlation is compared with a certain threshold value.
If the value is larger than the threshold value, the quantization is performed so as to be “1”, and the others are “0”, and the time at the center of the time at which “1” is continuously output becomes the reception time of the known pattern. The timing difference detection circuit 9 detects and outputs a timing difference from the difference between the reception time of the known pattern and the reception time of the known pattern assumed by the receiver.

[0007]

However, in the conventional synchronizer, the result of correlation between the received signal and the known pattern is compared with a certain threshold value to obtain quantized data of "1" or "0". In some cases, an error occurs in the detection of the quantized data due to a good or bad line condition. In other words, when the line state is good and the reception level is high, the correlation result is large, so that the quantized data becomes "1" even if the correlation of the received signal to the known pattern is low, or conversely, the line state becomes If the reception level is poor and the reception level is low, the correlation result appears to be small. Therefore, even when the reception signal matches the known pattern, it may be “0”.

The present invention solves such a conventional problem, and can correctly detect a clock difference between a transmission side and a reception side without being affected by a reception state.
It is an object of the present invention to provide a synchronizing device that can accurately correct timing based on the detection result.

[0009]

Therefore, in the present invention, A
In a synchronizing device for performing a correlation process between a / D-converted received signal and a known pattern to detect a reception timing of a known pattern inserted into the signal at the time of transmission and correcting a timing deviation of the receiver with respect to the transmitter, Storage means for separately storing each correlation value obtained by the correlation processing performed in the conversion sampling period, detecting the reception time of a known pattern from the maximum value of the correlation value, and detecting the timing of the receiver with respect to the transmitter detection means for determining the deviation, determined detection means
Correction means for correcting the timing deviation;
Is shorter than the sampling period of A / D conversion.
It is configured to correct the timing deviation .

[0010]

[0011]

The correction means includes a correction signal output means for outputting a correction signal when the magnitude of the timing deviation obtained by the detection means exceeds a threshold value, and a correction execution means for correcting the timing deviation using the correction signal. And means.

The correction executing means is constituted by a counter for repeatedly counting up to a certain number in the same cycle, and this counter is formed so as to change a value at the beginning of counting in accordance with the correction signal.

Further, the counter is configured to count in a cycle shorter than the sampling cycle of the A / D conversion.

Further, there is provided a threshold value changing means for changing the threshold value so as to be small at the start of synchronization pull-in and thereafter increased.

Further, there is provided weighting means for enhancing the magnitude of the timing deviation obtained by the detection means.

[0017]

Since the reception timing of the known pattern is detected from the maximum value of the correlation value, the most probable reception timing can be detected irrespective of the line condition, and the timing deviation can be accurately corrected. Can be.

The smaller the step size of the correction of the timing deviation, the more accurate the correction can be made. However, if the sampling time width of the A / D conversion is narrowed to realize it, a high-speed operation element is required. Therefore, the price of the device and the power consumption increase. By reducing the step size of this correction through the function of the correction means, accurate timing correction becomes possible without causing such disadvantages. For example, by halving the counting cycle of the counter constituting the correction means, it is possible to halve the step size of correction when one counter value is corrected.

Further, when the magnitude of the detected value or the accumulated value of the timing deviation obtained by the detection means exceeds a threshold value, a correction signal is output, and in a device for performing timing correction based on this correction signal, the threshold value is set. By increasing the value at the beginning of the synchronization and then increasing the value, the timing is quickly corrected when the timing shift immediately after the synchronization is large, and the operation shifts to the gradual correction when the operation is stabilized.

Further, when the detected timing deviation obtained by the detecting means is weighted to emphasize the timing deviation, the threshold value is immediately exceeded when the deviation is large, so that quick timing correction is performed. Conversely, when the deviation is small, stable timing correction is performed.

[0021]

【Example】

(First Embodiment) As shown in FIG. 1, the synchronizer according to the first embodiment includes A / D converters 1, 2, a memory A3, a memory B5, and a complex as in the conventional synchronizer (FIG. 11). The apparatus includes a correlator 4 and a timing difference detection circuit 10 that detects a reception time of a known pattern from the maximum value of the correlation values calculated by the complex correlator 4.

As shown in FIG. 3, the timing difference detection circuit 10 includes a memory D12 for storing the correlation values output from the complex correlator 4 by sequentially changing the area, and a memory D12 for the correlation values.
Switch 11 for allocating the storage position to the memory D and the memory D
And a maximum value detection circuit 13 for detecting the maximum value of the correlation values stored in 12.

FIG. 2 shows the frame format of the transmission signal. In this example, a known pattern for detecting a clock difference (synchronization words 1, 2, and 3; this known signal is usually called a synchronization word or a synchronization symbol) is arranged at the center of the transmission signal. . The symbol length is N symbols, and in this example, N = 25.

The A / D converters 1 and 2 of the synchronizer convert the received signal at a sampling rate n times the time interval of one symbol of the transmitter in order to detect a clock difference between the transmitter and the receiver. It is sampled and converted to digital data. This sampling is generally referred to as oversampling at n times the symbol rate. In this embodiment, n =
4, ie, 4 times oversampling is performed. Generally, the higher the oversampling ratio is, the more accurately the timing deviation can be detected. However, when the apparatus is implemented, the cost and power consumption are high.

The sampling timing of the A / D converters 1 and 2 is performed in synchronization with the operation timing A.
The digital data converted by the converters 1 and 2 is stored in the memory A3 at the operation timing A.

When the transmission signal includes M symbols in the transmission signal, the complex correlator 4 extracts the data of the synchronization word (M symbols) from the reception signal stored in the memory A3 and stores the data in the memory B5. A correlation operation with the stored known synchronization word is performed.

Now, the received signal s (t) is expressed by the following equation 1. s (t) = I (t) + jQ (t) (Equation 1) (where I (t): in-phase component, Q (t): quadrature) Component). A sample for M symbols from the data at the time nT is stored in the memory A3, and is stored as I (iT) + j
Expressed as Q (iT). The in-phase component of the known pattern stored in the memory B5 is I ₀ (t), and the quadrature component is Q
_{When 0} (t) is set, the correlation operation is performed by Expression 2.

(Equation 2) When the i-th symbol data stored in the memory A3 is a synchronization word, the in-phase component is I ₀ (iT) and the quadrature component is Q ₀ (iT). Therefore, at the reception time of the synchronization word, the result of the correlation operation is u = 1 from Equation 2.
As described above, the result of the correlation operation approaches 1 when the waveforms of the transmission signal and the reception signal are the most similar, that is, when the timing is the best.

The operation of the complex correlator 4 is performed in synchronization with the operation timing A.

The timing difference detection circuit 10 stores only the correlation value for a certain time before and after the optimum timing assumed by the receiver among the correlation results output from the complex correlator 4 in the memory D12. Store in each area in order. This data update of the memory D12 is performed in synchronization with the operation timing B.

The maximum value detector 13 detects, from the correlation results stored in the memory D12, the most probable correlation value that is considered to indicate the reception time of a known pattern. In the present embodiment, since the correlation value is 1 in an ideal case, the time at which the correlation value takes the largest value is the most likely reception time. The maximum value detector 13 detects the maximum value of the correlation values, and outputs a timing difference between the optimal timing assumed by the receiver and the optimal timing corresponding to the detected maximum value. This operation of the maximum value detector 13 is performed in synchronization with the operation timing C.

This timing difference can be obtained as follows.

Each time the sampling clocks of the A / D converters 1 and 2 are input, the count is incremented, and from 0 to n × N−1
Is prepared, and the storage of the correlation value in the memory D12 is controlled in accordance with the counter value of this counter. Here, n is the oversampling ratio of the A / D converter, and N is the number of symbols in one frame. If the counter value x is the optimal timing assumed by the receiver, and if the actual synchronization word is received when the counter value is y, the clock shift is given by Equation 3. ΔT = xy (Equation 3)

Now, the index of the area located at the center of each area of the memory D12, that is, the area storing the correlation value of the optimal timing assumed by the receiver is set to 0, The front area is indexed with a positive serial number, and the rear area is indexed with a negative serial number. The correlation result output from the complex correlator 4 when the counter value of the counter reaches a certain number is stored in the area of the largest index in the memory D12, and the storage area of the correlation result is sequentially changed as the counter value increases. And the counter value is x
It is assumed that the correlation value at the time of is stored in the area of index 0.

If it is detected that the maximum value of the correlation values stored in this order exists in the area of the index i, the counter value y corresponding to the actual synchronization word reception time at which the maximum value is stored is stored. Becomes xi. Therefore, the timing difference obtained from Equation 3 is i. That is,
The maximum value detector 13 can output the timing difference by detecting the maximum value of the correlation value and outputting the index of the area storing the maximum value.

As described above, in the synchronizer according to the embodiment, the maximum value of the correlation value is detected, and the most probable reception time of the synchronization word is obtained based on the detected maximum value. Therefore, as in a conventional device that detects the reception time of a known pattern by comparing the correlation result with a threshold, the known pattern is erroneously detected when the reception condition is good, and the known pattern is detected when the reception condition is bad. (Embodiment 2) The synchronizer according to the second embodiment can detect the timing based on the detected timing difference, stably detecting the most likely timing irrespective of the reception state. Is performed.

As shown in FIG. 4, the synchronizer includes a correction loop counter 14 for correcting the count using the timing difference detected by the timing difference detection circuit 10.
And a decoder 15 that outputs a timing signal based on the corrected count value output from the loop counter 14 with correction. Further, the same operation timing A as the sampling clock of the A / D converters 1 and 2 is given to the loop counter 14 with correction, and the timing difference detection circuit 10 updates the memory D12 and detects the timing difference. For this operation, the decoder 15 outputs a timing signal formed based on the corrected count value. Other configurations are the same as those of the first embodiment.

As shown in FIG. 5, the loop counter with correction 14 adds the clock difference detected for each frame and the clock difference up to the previous frame, and the adder A16, which is output from the adder A16. , A memory E17 for storing data added by the adder A16, a comparator A18 for comparing the output of the adder A16 with a threshold, an adder B20 for outputting a corrected counter value, and storing an output of the adder B20. Memory F
21 and the connection to the adder B20 by the comparator A18 or the memory F
21 and a comparator B which switches the connection of the switch 19 when the counter value of the adder B20 reaches n × N-1 and resets the memory F21.
22.

The adder A16 adds the input clock difference in cooperation with the memory E17 and outputs the accumulated value to the comparator A18. The comparator A18 compares this addition result with a threshold value (z> 0). This comparator A18 operates as follows.

(A) Addition result> Z When the addition result output from the addition value A16 is larger than Z,
Since the synchronization word is received with a shift ahead of the optimal timing assumed by the receiver, it is necessary to correct the timing of the receiver forward. At this time, the comparator A18
Outputs 0 as the correction value. At the same time, the comparator A18 resets the memory E17.

(B) Addition result <-Z When the addition result output from the addition value A16 is smaller than -Z, the synchronization word is received with a backward shift from the optimum timing assumed by the receiver. Therefore, it is necessary to correct the timing of the receiver backward. At this time, the comparator A18 outputs -2 as a correction value. At the same time, comparator A
18 resets the memory E17.

(C) Z ≧ addition result ≧ −Z When the addition result output from the addition value A16 is between Z and −Z, the comparator A18 outputs −1 as a correction value.

At the same operation timing A as the sampling clocks of the A / D converters 1 and 2, the adder B20 outputs the comparator A
18 or 1 is added to the output value of the memory F21, and the result is output as a counter value. In a normal state, the adder B20 is connected to the memory F21 and increments the counter value by one by adding 1 to the previous counter value stored in the memory F21.

When the counter value reaches n × N-1, that is, the number of sampling clocks for one frame, the comparator B
22 switches the connection of the changeover switch 19 to the comparator A18 side,
Further, the memory F21 is reset.

At this time, if the comparator A18 outputs 0 as the correction value (in the case of (a)), the adder B
20 adds 1 to the value 0 and outputs 1 as a counter value. The comparator B22 switches the connection of the changeover switch 19 to the memory F21 because the counter value becomes a value other than n × N-1. Thus, the adder B20 has 1, 2,..., N
× N−1.

Similarly, when the comparator A18 outputs -2 as the correction value (in the case of (b)), the adder B20 similarly outputs -1, 0, 1,. XN-1 is counted.

When the absolute value of the accumulated clock difference is equal to or smaller than the threshold value and the comparator A18 outputs -1 as the correction value, the adder B20 outputs 0, 1,. Count one.

The counter value corrected by the loop counter with correction 14 is sent to the decoder 15 and
Outputs the frame timing based on this counter value, and outputs the memory D in the timing difference detection circuit 10.
An update timing or a timing difference detection timing for the 12 and the maximum value detector 13 is output. As a result, in the memory D12, the correlation value at the reception time of the synchronization word is
The data is stored in the storage area (index 0) of the optimal timing assumed by the receiver, and the timing deviation is eliminated.

As described above, in the synchronization device of the second embodiment,
Based on the detected value of the timing deviation detected from the received signal, the timing of the receiver can be adjusted to match the timing of the transmitter.

(Third Embodiment) In the synchronizer of the third embodiment, a timing deviation can be corrected with a small width. If the step size of the timing correction is large, the detection timing of the received data can be corrected only in a rough range, which causes deterioration of the reception performance. To finely correct the timing deviation,
It is necessary to increase the sampling rate of the / D converters 1 and 2 to reduce the step width of the timing correction. However, when doing so, a high-speed operation element is required when the device is implemented, and the cost increases and the consumption increases. The power also increases.

In view of the above, the synchronizer of the third embodiment is configured so that the timing deviation can be corrected in small steps without changing the sampling rate of the A / D converter.

In this synchronizer, as shown in FIG. 6, the A / D of the second embodiment is
An operation timing A having an integer (m) times the clock frequency of the sampling clock in the converter is supplied,
A / D converters 1 and 2, memory A3, complex correlator 4
The operation timing signal generated by the decoder 15 is supplied to the timing difference detection circuit 10. Other configurations are the same as those of the second embodiment (FIG. 4).

The loop counter with correction 23 is shown in FIG.
As shown in FIG. 5, the second embodiment (FIG. 5)
Is the same as the counter. However, the adder B28 counts up at the operation timing A at m times the speed of the apparatus in FIG. 5 and outputs a counter value up to n × m × N−1. The comparator B30 has a counter value of n × m × N−1.
Is reached, the changeover switch 27 is switched to the comparator A26 side and the memory F29 is reset.

The decoder 15 has a loop counter 23 with correction.
In response to the counter value output from, the operation timing to each unit is output as follows.

The A / D converters 1, 2, the memory A3, and the complex correlator 4 are the same as those of the second embodiment.
The operation timing or the update timing is output at substantially the same cycle as the sampling clocks of the converters 1 and 2, that is, each time the counter value (CNT) is incremented by m.

The memory D of the timing difference detection circuit 10
12, CNT = TMG1 (i) × m (TMG1 (i) is the memory D of the timing difference detection circuit 10)
The update timing is output when the relationship of the update timing (i = 0, 1, ‥) with respect to 12 is satisfied.

The timing difference detection timing is output to the maximum value detector 13 of the timing difference detection circuit 10 when CNT = TMG2 × m (TMG2 is the timing difference detection timing).

When the detected value of the timing deviation is output from the maximum value detector 13, the adder A of the loop counter 23 with correction is output.
24 adds the detected value each time it is input and outputs the accumulated value to a comparator A26. The comparator A26 compares the addition result of the adder A24 with a threshold value (Z) to determine a correction value. Output. This correction value is the same as that of the second embodiment, and the addition value A16
When the addition result of the addition is larger than Z, 0 is output as the correction value, and when the addition result of the addition value A16 is smaller than -Z, -2 is output as the correction value. Is output between Z and -Z, -1 is output as a correction value.

On the other hand, when the counter value output from the adder B28 reaches n.times.m.times.N-1, the comparator B30 switches.
27 is switched to the comparator A26 side, and when the counter value is other than that, the memory F29 is connected to the adder B28.

As a result, when the comparator A26 outputs 0 as the correction value, the adder B28 outputs 1, 2,.
m × N−1, and when −2 is output as the correction value, it is counted as −1, 0, 1, 2, ‥, n × m × N−1, and the accumulated value of the timing deviation In the state where the absolute value of the correction value -1 is less than the threshold value Z, 0, 1, 2,.
‥, count as n × m × N−1. Therefore, adder B
In 28, the counter value can be corrected in a width of 1 / (n × m × N) by the correction value output from the comparator A26. This is 1 / m of the correction increment 1 / (n × N) of the counter value in the second embodiment.

The decoder 15 has a loop counter 23 with correction.
, A frame timing signal based on the corrected counter value output from the A / D converter 1, 2, the memory A3,
A timing signal for the complex correlator 4 and the timing difference detection circuit 10 is output. As a result of the counter value being corrected in small increments, the operation timing of each unit can be controlled in small increments through these signals.

As described above, in the synchronization device of the third embodiment,
By performing the inclinting timing of the loop counter 14 with correction at an integer multiple (m times in the embodiment) of the sampling rate of the A / D converter, the A / D conversion can be performed without changing the sampling rate of the A / D converter. Timing correction can be performed in steps smaller than the sampling rate of the converter. This makes it possible to reduce the deviation of the data detection timing from the optimal time.

(Fourth Embodiment) Immediately after pull-in, there is a large difference between the optimum timing assumed by the receiver and the optimum timing of the transmitter, so that the timing must be corrected promptly. On the other hand, after the timing correction is performed, the timing correction must be performed gently for the stability of the operation.

The synchronizer of the fourth embodiment can meet such a demand. The overall configuration of this device is the same as that of the second embodiment (FIG. 4), and the difference is as shown in FIG.
The difference lies in that the loop counter with correction 14 includes a threshold updating circuit 31 for changing the threshold of the comparator A18 according to the operation timing C.

As shown in FIG. 9, the threshold value updating circuit 31 constitutes a counter together with the memory G32, and each time an operation timing C is inputted, the adder A33 increments the counter value by one, and the counter of the adder A33. A comparator 34 that outputs a control signal when the value and the comparison value match,
An adder B35 that forms a counter together with the memory J38 and increments the counter value according to the control signal from the comparator 34, a memory H36 that outputs a threshold value using the counter value of the adder B35 as an index, and a counter of the adder B35 A memory I37 for outputting the comparison value of the comparator 34 using the value as an index.

Now, the memory I37 outputs 1, 2, 4, and ‥ as comparison values corresponding to the counter values 0, 1, 2, and の of the adder B35, and the memory H36 stores the adder B35 1, 2, 3, and と し て are output as threshold values corresponding to the counter values 0, 1, 2, and の.

The threshold value updating circuit 31 outputs one
Each time the operation timing C is input. When the first operation timing C is input, the adder A33 which forms a counter together with the memory G32 outputs a counter value 1, and the comparator 34 outputs the counter value 1 of the adder A33 and the initial value output from the memory I37. And outputs a control signal to the adder B35 because they match.

The adder B35 which forms a counter together with the memory J38 counts 1 according to this control signal.
Since the counter value of the adder B35 has changed to 1 in the memory H36, the threshold value is changed from 1 to 2, and the memory I37 outputs 2 as the comparison value.

When the operation timing C of the second frame is input, the adder A33 outputs the counter value 2 and the comparison value 34.
Outputs a control signal because this value matches the comparison value 2 output from the memory I37, and the adder B35 receiving the control signal outputs the counter value 2. Therefore, the memory H
36 changes the threshold value to 3, and the memory I37 outputs the comparison value 4.

When the operation timing C of the third frame is input, the adder A33 outputs the counter value 3, but the comparison value
34 does not output a control signal because this value does not match the comparison value 4 output from the memory I37.

When the operation timing C of the fourth frame is input, the adder A33 outputs the counter value 4 and the comparison value 34
Outputs a control signal because this value matches the comparison value 4, and the adder B35 outputs the counter value 3. for that reason,
The threshold value is updated by the memory H36, and a new comparison value is output from the memory I37.

As described above, the threshold value changing circuit 31 outputs a small value as the threshold value immediately after the synchronization pull-in, and changes the threshold value to a large value as time passes.

Therefore, in the synchronizer of this embodiment, immediately after the synchronization is pulled in, the accumulated value of the timing deviation output from the adder A16 exceeds the threshold value in a short time, so that the correction value is output from the comparison value A18 at an early stage. Thus, the timing correction is performed earlier. Thereafter, since the threshold value increases with time, the timing at which the correction value is output from the comparison value A18 is delayed, the interval of the timing correction is lengthened, and the mode shifts to gradual and stable timing correction.

(Fifth Embodiment) A synchronizing device according to a fifth embodiment comprises:
If there is a large difference between the optimal timing assumed by the receiver and the optimal timing of the transmitter, such as immediately after synchronization pull-in, timing correction is performed at high speed, and if the difference is small, , The timing can be corrected gently.

The overall configuration of this synchronizer is the same as that of the second embodiment (FIG. 4).
Only in the internal configuration of As shown in FIG. 10, the timing difference detection circuit 10 includes a memory K39 for storing a weight coefficient corresponding to the magnitude of the timing deviation, a timing deviation detection value output from the maximum value detector 13, and an output from the memory K39. And a multiplier 40 for multiplying the weight coefficient by the weight coefficient. Other configurations are the same as the detection circuit of the second embodiment (FIG. 3). This memory K39 is, for example,
A table is stored in which a weight coefficient of 1 or less corresponds to an index near the center, and one or more weight coefficients correspond to an index separated by a predetermined number or more from the center.

In the timing difference detection circuit 10, when the maximum value detector 13 detects the maximum value of the correlation value stored in the memory D12 and outputs the index of the area where the correlation value is stored as the timing deviation detection value, K39 outputs a weight coefficient corresponding to the detected value to multiplier 40 based on the stored table. The multiplier 40 outputs a value obtained by multiplying the timing deviation detection value output from the maximum value detector 13 by the weight coefficient as a timing difference.

The detected value of the timing difference in which the magnitude of the timing difference is emphasized is input to the loop counter 14 with correction, and the comparator A18 of the loop counter 14 with correction determines the accumulated value of the detected timing difference as a threshold value. Outputs the correction value when it exceeds. Therefore, when the timing deviation is large, the accumulated value increases rapidly, so that the correction value is output quickly from the comparator A18, and quick timing correction is performed. On the other hand, if the timing deviation is small, the increase in the accumulated value becomes small, the output of the correction value from the comparator A18 becomes slow, and gradual timing correction is performed.

As described above, in the synchronizer of the fifth embodiment, by weighting the detected value of the timing deviation,
When the deviation is large, the correction is performed quickly, and when the deviation is small, a stable correction operation can be performed.

[0078]

As is apparent from the above description of the embodiment, the synchronizer of the present invention can stably detect the timing deviation between the transmitter and the receiver regardless of the reception state. Further, the timing of the receiver can be accurately corrected to the timing of the transmitter based on the detection result.

Further, by performing the increment timing of the counter at an integral multiple of the sampling rate of the A / D converter, the sampling rate of the A / D converter can be maintained without changing the sampling rate of the A / D converter. In addition, accurate timing correction can be performed in small steps. In this case, since the sampling rate of the A / D converter is not changed, a high-speed operation element is not required, and the power consumption and the price of the receiver do not increase.

In a device provided with a threshold updating circuit and a timing shift weighting means, timing correction can be performed at high speed immediately after the start of synchronization pull-in, and thereafter, a stable correction operation can be performed. Therefore, the reception state of the receiver is promptly corrected to an appropriate state, and the state is stably maintained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a synchronization device according to a first embodiment of the present invention;

FIG. 2 shows a frame format of a transmission signal for detecting synchronization by the synchronizer of the first embodiment;

FIG. 3 is a block diagram showing a timing difference detection circuit in the synchronization device according to the first embodiment;

FIG. 4 is a block diagram showing a configuration of a synchronization device according to a second embodiment of the present invention;

FIG. 5 is a block diagram of a loop counter with correction in the synchronizer according to the second embodiment;

FIG. 6 is a block diagram illustrating a configuration of a synchronization device according to a third embodiment of the present invention;

FIG. 7 is a block diagram of a loop counter with correction in the synchronizer according to the third embodiment;

FIG. 8 is a block diagram of a loop counter with correction in a synchronizer according to a fourth embodiment of the present invention;

FIG. 9 is a block diagram of a threshold updating circuit in the synchronization device according to the fourth embodiment;

FIG. 10 is a block diagram of a timing difference detection circuit in a synchronization device according to a fifth embodiment of the present invention;

FIG. 11 is a block diagram showing a configuration of a conventional synchronization device.

[Explanation of symbols]

1,2 A / D converter 3,5,8,12,17,21,25,29,32,36,37,38,39
Memory 4 Complex correlator 7, 11 Changeover switch 9, 10 Timing difference detection circuit 13 Maximum value detection circuit 14, 23 Loop counter with correction 15 Decoder 16, 20, 24, 28, 33, 35 Adders 18, 22, 26, 30, 34 Comparator 31 Threshold update circuit 40 Multiplier

Continuation of front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/08 H04L 7/00 H04J 3/06 H04L 27/00

Claims (6)

(57) [Claims] 1. A correlation process between an A / D-converted received signal and a known pattern is performed to detect a reception timing of a known pattern inserted into the signal at the time of transmission, and to correct a timing deviation of the receiver with respect to the transmitter. A synchronizing device, wherein a storage means for storing each correlation value obtained by the correlation processing performed in an A / D conversion sampling cycle in a divided area, and detecting a reception time of the known pattern from a maximum value of the correlation value and, correcting hand for correction and detection means for determining the timing deviation of a receiver for the transmitter, the timing deviation was determined of the detection means
And a compensating means, wherein the correction means comprises a sampler for the A / D conversion
The timing deviation is compensated for in a time width shorter than the ring cycle.
A synchronizing device for performing corrective action . 2. The method according to claim 1 , wherein said correcting means calculates a value obtained by said detecting means.
Correction signal when the timing deviation exceeds the threshold
Correction signal output means for outputting
The synchronization device according to claim 1, further comprising: a correction execution unit that corrects the timing deviation . 3. The method according to claim 2, wherein the correction execution means comprises a fixed number
A counter that repeatedly counts up to
3. The synchronization device according to claim 2, wherein a value at the start of counting is changed according to the correction signal . 4. The A / D converter according to claim 1 , wherein :
It is characterized by counting in a cycle shorter than the pulling cycle
The synchronizer according to claim 3 . 5. The method according to claim 1, wherein the threshold is set at the start of synchronization pull-in.
Threshold changing means for changing so that it is small and then increases
The synchronizing device according to claim 2 , comprising: 6. A method according to claim 5, wherein said detecting means detects a timing deviation.
A weighting means for emphasizing the size is provided.
The synchronization device according to claim 2 .