JP3205028B2 - Image compression apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image compression apparatus, for example, an image compression apparatus having an orthogonal transformation function and a method thereof.

[0002]

2. Description of the Related Art The memory capacity required for storing a halftone image (hereinafter, referred to as an "image") such as a photograph in a memory is calculated by (number of pixels) .times. (Number of gradation bits).
An enormous memory capacity was required to store high-quality color images. For this reason, various information amount compression methods have been proposed. For example, the amount of information is compressed and then stored in a memory to reduce the memory capacity.

FIG. 19 shows JPEG (Joint Photographic Experts) as an international standardized method of color still image coding.
Group), the coding method of the baseline system (basic method) proposed by Yasuda: "International Standardization of Color Still Image Coding", Journal of the Institute of Image Electronics Engineers of Japan, Vol. 18, No. 6, p.
pp. 398-409, 1989).

In FIG. 1, image pixel data inputted from an input terminal 1 is supplied to a
It is cut out in a block shape of × 8 pixels, cosine-transformed by a discrete cosine transform (hereinafter, referred to as “DCT”) circuit 17, and a transform coefficient obtained by this transform is quantized (hereinafter, referred to as a quantizer).
(Referred to as “Q”) 40. In Q40, the linear quantization of the transform coefficient is performed according to the quantization step information applied by the quantization table 41. Among the quantized transform coefficients, the DC coefficient is a predictive coding circuit (hereinafter, referred to as a predictive coding circuit)
"DPCM") 42, the DC of the previous block
The difference (prediction error) from the component is obtained, and this difference is supplied to the one-dimensional Huffman encoding circuit 43. FIG. 20 shows the DPC
It is a block diagram which shows the structure of M42 in detail. The DC coefficient quantized by Q40 is supplied to a delay circuit 53 and a subtractor 5
4 is applied. The delay circuit 53 is a circuit for delaying the discrete cosine transform circuit by one block, that is, the time required for the operation of 8 × 8 pixels. Accordingly, the DC coefficient of the previous block is supplied from the delay circuit 53 to the subtractor 54. Accordingly, the difference (prediction error) of the DC coefficient between the current block and the previous block is output from the subtractor 54. In the present prediction coding, since the previous block value is used as the prediction value, the predictor is constituted by the delay circuit as described above.

[0005] The one-dimensional Huffman encoding circuit 43 uses a DPC
The prediction error signal supplied from M42 is subjected to variable length encoding according to the DC Huffman code table 44, and the variable length encoded data, that is, the DC Huffman code is supplied to the multiplexing circuit 51.

On the other hand, AC coefficients (coefficients other than DC coefficients) quantized by Q 40 are zigzag-scanned in order from a lower-order coefficient by a scan conversion circuit 45 as shown in FIG. Supplied. The significant coefficient detection circuit 46 determines whether or not the quantized AC coefficient is "0". If the quantized AC coefficient is "0", a count-up signal is supplied to the run length counter 47, and the value of the counter is incremented by +.
Increase by one. On the other hand, when the coefficient is "1", a reset signal is supplied to the run length counter to reset the value of the counter, and the coefficient is grouped by the grouping circuit 48 in FIG.
As shown in FIG. 2, the data is divided into a group number SSSS and additional bits, and the group number SSSS is supplied to a two-dimensional Huffman encoding circuit 49 and the additional bits are supplied to a multiplexing circuit 51. The run length counter 47 counts the run length of “0” and supplies the two-dimensional Huffman encoding circuit 49 with the number NNNN of “0” that continues between significant coefficients other than “0”. The Huffman encoding circuit 49 supplies the run length NNNN of “0” and the group number SS of the significant coefficient.
The SS is variable-length coded according to the AC Huffman code table 50, and the variable-length coded data, that is, the AC Huffman code is supplied to the multiplexing circuit 51.

In the multiplexing circuit 51, one block (8 × 8)
DC Huffman code, AC Huffman code and additional bits for the input pixels are multiplexed, and the multiplexed data, that is, compressed image data is output from an output terminal 52. Therefore, the memory capacity can be reduced by storing the compressed data output from the output terminal 52 in a memory and decompressing the data by a reverse operation at the time of reading.

[0008]

However, the above-mentioned prior art has the following drawbacks. It is assumed that the above conventional example is applied to, for example, an image output device. Generally, an image output device is connected to an image input device such as a host computer or an image scanner, and is often operated as a part of a system. In this case, various images such as a CG (Computer Graphic) image created on the host computer and an image input by an image scanner are transmitted to the image output device.

In the above conventional example, in an image in which conversion coefficients are concentrated in a low frequency band in orthogonal transformation, such as an image obtained by digitizing an image such as a photograph by an image scanner,
Although image degradation is suppressed, CG images, font images, CAD
(Computer Aided Design) In artificial line drawings such as images, there is a disadvantage that the compressed and decompressed images are greatly deteriorated.

Conventionally, a technique for adaptively switching a quantization condition according to a value of a transform coefficient is disclosed in U.S. Pat. S. S. No. 738,562, proposed by the applicant, has the following disadvantages:
That is, since an image sampled as an input source is a target, a portion detected by a transform coefficient is configured to be distinguished from an edge portion or a flat portion in the image. No matter how much the original source of the input source input by the device such as the image scanner, that is, the sampled image, the edge portion is deteriorated due to the MTF (modulation transfer function) characteristic of the image scanner. Output image.
Therefore, even if the high-frequency component in the block is slightly coarsely quantized, the image quality is not significantly affected. However, the above-described artificially created image is an image input by a device such as an image scanner, that is, A is strong against a high-frequency component that does not occur in the edge portion of a normal medium-low resolution image.
Often includes C power. If these images are coarsely quantized as in the prior art, the adverse effect increases such that artificially formed fine lines are interrupted or noise such as ringing occurs in a flat portion near the fine lines. Further, even under the condition of switching the quantization condition by the transform coefficient, a simple and low-time-loss method has not been proposed.

The conventional example has the following disadvantages.

Normally, in a halftone image in which an original such as a photograph is input by a device such as an image scanner or the like, coefficients tend to concentrate in a low frequency band in an orthogonally transformed block. In many cases, the generation of coefficients concentrates, and from there, "0" is often continuous in all higher orders.

In this case, if the "0" run continues for 16 or more, the code "R16" is assigned as shown in FIG. 22, and after transmitting this code, the counter of the "0" run is reset. Then, the run length of "0" is counted again. Thereafter, when a significant coefficient other than "0" is generated, two-dimensional Huffman coding is performed using the significant coefficient and a run length of "0" that continues immediately before the significant coefficient.

For this reason, in the zigzag scan in which scanning is performed in order from the low-order coefficient as shown in FIG. 21, even if the generation of the significant coefficient is terminated on the way, the significant coefficient is not changed in the subsequent high-order coefficient. Since it is unknown whether or not this has occurred, the number of “0” must be counted for each coefficient to prepare for the encoding of “R16”. That is, in the zigzag scan in order from the low-order coefficient, it is determined to what extent significant coefficients other than “0” have occurred, in other words, to what extent the coding can be performed. You can't find it without trying. If the highest order coefficient is “0”
If the significant coefficient is other than 0, based on the run length of “0” accumulated so far, if “0” runs are 16 or more, the encoding of R16 and the encoding of subsequent “0” runs are performed. I have to do it again. If the highest order coefficient is also “0”, the “0” runs accumulated so far are reset and “EOB (End Of Block)” is executed.
(Shown in FIG. 22) must be generated.
That is, the time required for encoding in the block may be different at the end. In other words, there is a disadvantage that encoding cannot be performed in a fixed time every time.

The present invention has been made in view of the above-described drawbacks of the conventional example, and has as its object to output edges such as characters, fonts, and line drawings which have been artificially created. Another object of the present invention is to provide an image compression apparatus which can realize appropriate quantization of an image received from any input source with a simple configuration.

Another object of the present invention is to provide an image compression apparatus capable of performing encoding within a predetermined time regardless of what kind of information is in a block, and having a low-cost and simple circuit configuration. The point is to provide.

[0017]

Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the object, an image compression device according to the present invention includes an input unit that inputs image data divided into predetermined blocks, a conversion unit that converts the image data into orthogonal transform coefficient data for each of the blocks, An identification means for determining whether or not an absolute value of orthogonal transform coefficient data in a predetermined area in the block has a value equal to or greater than a predetermined value, and identifying an image type of the block; And quantizing means for quantizing orthogonal transform coefficient data in the block. Further, in the image compression method according to the present invention, image data divided into predetermined blocks is input, the image data is converted into orthogonal transform coefficient data for each block, and orthogonal transform coefficients in a predetermined area in the block are input. It is determined whether or not the absolute value of the data has a value equal to or greater than a predetermined value, and the image type of the block is identified, and the orthogonal transform coefficient data in the block is quantized according to the identification result of the identification unit. It is characterized by the following.

[0018]

[0019]

Embodiments of the present invention will be described below with reference to the accompanying drawings. <First Embodiment> FIG. 1 is a block diagram showing a main part of a first embodiment of an image compression apparatus according to the present invention, and FIG. 2 is a flow chart for explaining main operation procedures according to the first embodiment. FIG. 3 is a diagram showing the inverse scan order of DCT coefficients, and FIG.
FIG. 5 is a diagram showing the order of T coefficient scan order, FIG. 5 is a diagram illustrating the relationship between input data of an image scanner input and DCT coefficients, and FIG. 6 is a diagram showing the relationship between input data artificially created by a computer and DCT coefficients. FIG.

In FIG. 1, reference numeral 100 denotes an input terminal for inputting multi-valued image data input by an image scanner or multi-valued image data artificially created by a computer; 101, a DCT circuit; 102, 103, 111, switches; 10
4 is a reverse scan address generator, 105 is a forward scan address generator, 106 is an absolute value circuit, 107 is a comparator,
Reference numeral 108 denotes a counter determination circuit, 109 and 110 denote quantization tables having different quantization characteristics, 112 denotes an output terminal for DC components, 113 denotes an output terminal for AC components, and 114 denotes Q.

Th is a predetermined threshold, and is manually selected by an operation unit (not shown). The selected Th is set in a predetermined register by a CPU (not shown).

The operation of the above configuration will be described with reference to FIG.

The multi-valued image signal corresponding to the image input from the input terminal 100 is already cut out into a block of 8.times.8 pixels by a block forming circuit (not shown), sent to the DCT circuit 101, and subjected to DCT. (S1). Although the present embodiment is described using an 8 × 8 DCT for the orthogonal transform, for example, other orthogonal transform schemes such as Hadamard transform or block sizes other than 8 × 8 may be used. Of course.

As shown in FIG. 4, the DCT-transformed coefficients are rearranged in a one-dimensional manner in a zigzag manner from low-order coefficients to high-order coefficients. The DCT coefficients arranged one-dimensionally will be defined in the form of an array called “DCT [n] (n = 0 to 63)”. DCT [0] is a coefficient of DC component, DC
T [1] to DCT [63] indicate AC component coefficients, and n
The smaller the value, the lower the coefficient.

Here, the switches 102 and 103 in FIG. 1 are initialized by every 8 × 8 pixel block.
They are connected to terminals a and c, respectively. The inverse scan address generator 104 is a circuit for giving an address for scanning from the highest-order transform coefficient to the lower-order transform coefficient, as indicated by the arrow in FIG. On the other hand, the forward scan address generator 105 is a circuit for giving an address for scanning from the lowest-order transform coefficient to the higher-order transform coefficient as shown by the arrow in FIG. More specifically, the DC component is DCT [0], and the DCT [1],
[2],..., DCT [63]. That is, DCT [n] indicates a conversion coefficient of address n.

The inverse scan address generator 104
First, DCT [63-i] is loaded, and the absolute value circuit 10
6 (ABS (DCT [63-i])
), And sent to the comparator 107. The comparator 107 compares the input ABS (DCT [63-i]) with a threshold value (Th) prepared in advance, and determines whether the AC power is equal to or greater than the threshold value (S2). If "ABS (D
If CT [63-i] ≧ Th ″ is not satisfied, in S3, it is determined whether or not i has reached a preset address by the counter determination circuit 108. This address can take only high-frequency components. For example, if DCT [45] to DCT [63] are set, the address is set to 19.

In S3, if i <address, S
4, the processing of i = i + 1 is performed (counter determination circuit 10
8) Scan the next DCT transform coefficient and repeat the same operation. The method of setting the Th and address values will be described later.

In the counter 108, the terminals of the switches 102 and 103 are also switched, and the condition of S2 is positive, that is, "ABS (DCT [63-i]) ≧ Th".
Or the condition of S3 is not satisfied, ie, “i ≧ address”
At this time, the terminals of the switch 102 and the switch 103 are switched to b and d, respectively. If the condition of S2 is positive, the quantization table 110 for the computer image is selected (S5),
If the condition of S3 is not satisfied, the quantization table 109 for natural images is used.
Is selected (S6). In practice, the quantization table 10
9 is selected at initialization (default). That is, the switch 111 is always initially connected to the terminal e. Further, in design, switching may be performed in accordance with the output from the comparator 107 (a signal indicating that S2 is positive), and loading may be performed.

Now, when one quantization table is selected, this time the forward scan address generator 105 and Q11
4 in accordance with the forward scan arrow shown in FIG. 4, first, the quantization of the DC component which is DCT [0], and then the DCT
AC that is [1], DCT [2], ..., DCT [63]
The components are quantized (S7 in FIG. 2). In FIG. 1, a DC component is output to an output terminal 112, and an AC component is output to an output terminal 113. After quantization, the method described in the related art may be adopted.

Now, in S8, it is determined whether or not j <63 by judging whether or not j <63. If the encoding of one block has not yet been completed, it is determined in S9 that j = j + 1. Perform processing and repeat quantization. In one block, switches 102 and 103
Once the terminals b and d are selected, the selected state is held until the encoding of the block is completed.

Although the configuration and control of this embodiment are simple and simple as described above, the above-mentioned settings of Th, address, and quantization tables 109 and 110 are required in advance.

FIG. 5A shows image data obtained by sampling a natural image (an image of a halftone image) using an image scanner. This image data is 8 bits, and the edge portion is formed in an 8 × 8 block shape. The steep edges are controlled by the MTF of the image scanner.
There is a point in which a sharp edge hardly occurs due to F.

FIG. 5B shows transform coefficients obtained by subjecting the image shown in FIG. 5A to DCT. This is 11 bits and -1024
The DC component can take values up to +1023 (in order to make the dynamic range the same as the AC component, 127 is subtracted from each pixel in FIG. 5A and then DCT-transformed). Thus, even in the edge portion of a natural image, the DC
As for the T-transform coefficient, a large value occurs in the low band, and the AC power decreases even if a large value occurs in the high band.

FIG. 6A shows a signal artificially created on the computer of FIG. This signal is 8 bits as in FIG. 5 (a). The transform coefficient obtained by DCT transforming this signal is shown in FIG.
(B). Since the total AC power is different from that in FIG. 5A, a general comparison cannot be made, but a considerably large value occurs not only in the low band but also in the high band. Although the example shown in FIG. 6 is only an example, a pattern in which the AC power is larger in the high frequency band than in the low frequency band can be created in the edge portion created artificially. That is, in the information input by the image scanner or the like, AC power that cannot be obtained is generated in the high frequency component. Therefore, when considering the system, it is necessary to experimentally and empirically determine the roundness due to the MTF characteristic of a normally connected device such as an image input device, and to determine the above-mentioned address and Th. For example, this time the address is DCT
36 from [28] to DCT [63] (address = 36)
And set Th to 50 (Th = 50). In an artificially created edge portion, it is assumed that there are some components where the absolute value of the DCT coefficient exceeds 50, but no edge portion is generated in an image read by an image scanner. That is, if at least one of the set high-frequency components is equal to or greater than a certain threshold value, it is regarded as an artificially created edge portion, line drawing, or the like. Even in an artificially created image, a flat portion that is not an edge portion is not extracted.

FIGS. 7A and 7B show examples of the above-described quantization tables 109 and 110, respectively. FIG. 7A is a diagram showing a luminance component Y table which is a JPEG standardization table described in the conventional example. This indicates the step width, on which linear quantization is performed. Naturally, the larger the value, the coarser the quantization.

FIG. 7B shows an example of the quantization table 110. According to the quantization table 110, the low band and the high band have substantially the same value. Although the DC components have different values, they may have the same value. That is, the step width of a certain component in the low band in the block from which the artificially created edge portion has not been extracted is S low, the step width of the certain component in the high band is S high, and the edge portion of the artificially created edge portion is If the step widths of certain components in the low and high frequencies in the block determined to be S'low and S'high, respectively,
Set so that Slow / Shigh <S'low / S'high ≧ 1. In other words, the slope of the f-characteristic indicating the range from the low band to the high band is calculated from the quantization table 109 to the quantization table 11.
By setting it to 0, it is possible to make it smoother.

As described above, it is determined by a simple method whether or not the input image is an edge portion created artificially for each block, and the quantization condition is switched.

As described above, according to the first embodiment, an edge portion of an image such as a line drawing created on a computer, for example, a line drawing created on a computer, or a font, is detected with a simple and easy configuration. , By performing appropriate quantization,
An output image can be formed well with any input source.

Further, according to the first embodiment, it is possible to perform image compression that is versatile, high-speed, and with little deterioration in image quality. <Second Embodiment> FIG. 8 is a block diagram showing a main part of an image compression apparatus according to a second embodiment of the present invention, and FIG. 9 is an example of quantization tables 110 to 113 according to the second embodiment. FIG.

This embodiment realizes a larger number of switching of the quantization tables than the first embodiment shown in FIG. 1, and the same parts as those in FIG. 1 are denoted by the same reference numerals. . As different configurations, 801 and 814 are switches, 8
02 is a squaring circuit, 803 is a low-frequency power adder, 804 is a counter determination circuit, 805 is a high-frequency power adder, and 810 and 8
Numerals 11, 812, and 813 indicate quantization tables, respectively.

In FIG. 8, the transform coefficients after the DCT are scanned in the forward scan direction (the direction of the arrow in FIG. 4; however, no DC component is used). First, the lowest A
Read the C transform coefficient DCT [1]. The switch 103 and the switch 801 are respectively connected to c and h by initialization. DCT [1] is calculated by squaring circuit 802 into 2
, And sent to the low-frequency power adder 803. The low-frequency power adder 803 indicates a means for cumulatively adding the square of the low-frequency transform coefficient. For example, the low band has 27 components from DCT [1] to DCT [27], and the high band is DCT [28] to DCT [63].
If there are 36 components, the counter determination circuit 804 counts up to 27 components and switches the switch 801 from h to g.
Switch to the terminal. The high-frequency power adder 805 is

[0042]

(Equation 1) Find the value of and hold. For the high-frequency component, a threshold value (Th) preset by the comparator 107 is prepared, as in the first embodiment described above. In this embodiment, since the conversion coefficient is not an absolute value but is squared, the threshold value also needs to be squared. The counter determination circuit 804 uses DCT [1]
When the scanning up to DCT [63] is completed, the comparator 1
07, receives signals from the high-band power adder 805 and the low-band power adder 803, sends a signal to the switch 806, and switches the quantization tables 810, 811, 812, and 813.

The counter determination circuit 804 obtains the displacement unit high band power P high per component and the average low band power P low per component. For example, as described above,
T [1] to DCT [27], high frequencies from DCT [28] to D
If CT [63],

[0044]

(Equation 2)

[0045]

(Equation 3) Becomes Then, the counter determination circuit 804 obtains the power ratio (P high / P low), and compares this power ratio with the comparator 10
According to the comparison result of No. 7, the quantization table is switched, for example, as follows. That is, there is more than Th and Phi
When gh / P low ≧ 0.8, the quantization table 11
When there is 0 or more than Th and P high / P low <0.8, the quantization table 111 does not have more than Th and
When P high / P low ≧ 0.8, quantization table 1
12. No Th or more, and P high / P low <0.8
In this case, the quantization table 113 is used. As an example,
As shown in FIG.

That is, if the value of the power ratio Phigh / Plow is large, a quantization table is selected such that the ratio of the step width, Slow / Shigh, of the quantization table of the above-described embodiment approaches "1". The above selection is performed by the switch 814, and the instruction is received from the counter determination circuit 804.

When the switching of the quantization table is completed, the forward scan address generator 105 returns to the head address again, and this time from the DC component, DCT [0] to DCT [6].
3] is performed. The switch 103 is connected from c to d, quantized by Q (Q) 114, and D
The C component is output to terminal 112 and the AC component is output to terminal 113.

As described above with reference to FIG. 8, when the quantization step of the DC component is the same in any quantization table, the pipeline is selected during the operation of selecting the quantization table in order to reduce the time. The encoding may be performed in the processing. That is, the table selection operation and the encoding operation may be performed simultaneously for different blocks.

In this embodiment, four quantization tables have been described. However, more or less quantization tables may be used. <Third Embodiment> In the above-described second embodiment, a comparison was made as the sum of the powers that take the sum of the squares in the high band and the low band. The sum of the absolute values of the ranges may be used.

FIG. 10 shows a third example of the image compression apparatus according to the present invention.
It is a block diagram which shows the principal part of Example of this. Since the present embodiment is partially different from the first embodiment, the same portions are denoted by the same reference numerals and only different points will be described.

In FIG. 10, reference numeral 1001 denotes an absolute value sum adder, which takes the absolute value sum of the input high-frequency transform coefficients.
The absolute value sum adder 1001 not only compares the absolute value of the high frequency component with the threshold value described in the first embodiment, but also checks the absolute value sum of the high frequency component. That is, the quantization condition is switched between a case where only one component protrudes into the high frequency range and a case where the overall value is large.

As described in the first embodiment, the switching of the quantization tables (109, 110) is performed artificially depending on whether or not there is an absolute value of a high-frequency transform coefficient larger than Th. It is determined by the switch 111 whether or not it is an edge portion.

FIG. 11 is a diagram showing an example of the quantization table according to the third embodiment.

In the case of a block determined to be an image input by an image scanner or the like, the table shown in FIG.
Select the table in (b). In FIG. 11, only the AC component is shown in the example of the quantization table 109, and the DC component, which is an example of the quantization table 110, should be held separately and fixed. Only when the quantization table 110 is selected, the multiplier 100
A so-called scaling factor (S factor) for multiplying each coefficient of the quantization table by 2 is set. That is, when the sum of absolute values in the high frequency range is large, the S factor is set large, and when the sum is small, it is determined that a certain component protrudes and exceeds the threshold value, and is set small. In the artificial edge part, unlike the edge part of the artificial image, the importance of the high frequency components is large, so all the high frequency components are used as much as possible, but the image is good if a small S factor is set every time. However, since the code amount increases, the above-described processing is effective. <Fourth Embodiment> FIG. 12 is a block diagram showing the configuration of a fourth embodiment of the image compression apparatus according to the present invention. FIGS. 13 and 14 illustrate the main operation procedure according to the fourth embodiment. It is a flow chart.

In FIG. 12, reference numeral 1100 denotes an input terminal for inputting a multi-level image signal similar to the input terminal 100 of FIG.
01 is a DCT circuit, 1102 is a scan conversion circuit, 11
03 is a buffer, 1104 is a Q table, 1105 is Q, 1106 is DPCM, 1107 is a one-dimensional Huffman coding circuit, 1108 is an inverse scan address generation circuit, 1
109 is a forward scan address generation circuit, 1110 is a switch, 1111 is a significant coefficient detection circuit, 1112 and 111
3 is a counter, 1114 is a run length counter, 1115 is a grouping circuit, 1116 is a two-dimensional Huffman coding circuit, 1117 is a DC Huffman table, 1118 is a multiplexing circuit, and 1119 is an output terminal.

Next, the operation of the above configuration will be described with reference to FIGS.

The multi-valued image signal input from the input terminal 1100 is supplied to a block circuit (not shown) at the preceding stage, where the multi-valued image signal is 8 ×
The DCT circuit 11 is cut out into blocks of 8 pixels.
01 and subjected to DCT (S101). In the present embodiment, an explanation is given using 8 × 8 DCT for the orthogonal transform. However, it is a matter of course that other orthogonal transform methods or block sizes other than 8 × 8 may be used.

The arranged DCT coefficients are temporarily stored in the buffer 1103. Then, the DC component (DCT
[0]) is linearly quantized in Q1105 in accordance with the quantization step information applied by the Q table 1104 as in the conventional example, and the transform coefficient after quantization is DPCM.
At 1106, the difference from the DC component of the previous block is calculated, and
A one-dimensional Huffman coding circuit 1107 generates a code. The present embodiment is characterized in the operation procedure of encoding the AC component. The reverse scan address generator 1108 and the forward scan address generator 1109 are both buffer 110
3 is read, and reading is performed in the reverse direction in buffer 1103 (in DCT [n], reading from the larger value of n is defined as reverse scanning). In the forward direction (in DCT [n], reading from the smaller value of n is defined as a forward scan).

For reading the AC component in the block, first, an inverse scan is previously selected by the switch 1110.

Subsequently, in S102, the read D
The CT coefficient (DCT [63-i]: i is assigned “0” in initialization) is linearly quantized in Q1105 in the same manner as the DC component. The quantized DCT coefficient is generally defined as DCT ′ [n] ″. In S102, the generated DCT ′ [63-i] is determined in S103.
It is determined whether it is “0” (significant coefficient detection circuit 11
11). If DCT '[63-i] = 0, the counter i shown in 1112 is incremented by "+1" (S104), and at the same time, the switch 111 is turned on.
A signal for selecting the reverse scan is transmitted to 0 again. Then, only one DCT coefficient component of one lower number (one lower order) of the array in the buffer is newly obtained by the inverse scan, and the same operation is performed until DCT ′ [63-i] ≠ 0. repeat. That is, the counter 1112 counts the number of consecutive "0" s from the highest-order quantized DCT coefficient (DCT '[63]) in the block to the address where the significant coefficient has occurred.

In step S103, DCT '[63
−i] If ≠ 0, the significant coefficient detection circuit 1111 transmits a signal for selecting the forward scan reading to the switch 1110.

In the forward scan reading, a buffer 1103 is used.
The DCT coefficient with the lowest number in the array in the table is read and quantized (S105). In S105, since the initialization of j is “1”, DCT [0] is a DC component, and the lowest order of the AC component is DCT [1].
First, DCT [1] is quantized to generate DCT ′ [1].

Subsequently, in S106, the significance detection circuit 1111 determines whether or not the quantized DCT '[j] is "0". If in S106, D
When CT ′ [j] = 0, the counter 1113
Is incremented by "+1", and at the same time, the count value NNNN of the run length counter 1114 is incremented by "+1" as in the conventional example (S107). S10
In step 6, if DCT '[j] ≠ 0, it is determined whether the number of NNNNs stored so far is more than 15 (S108). “R16” described in the example is transmitted, and 16 is subtracted from the value of NNNN (S109). If the number of NNNN is 15 or less, the grouping circuit 1115 groups generated coefficients DCT ′ [j] other than “0” and generates them as SSSS, as in the related art (S110).
2 of the group number SSSS and the run length NNNN of “0”
Dimensional Huffman coding (two-dimensional Huffman coding circuit 111
A code is generated according to 6), and the additional bits are multiplexed (S111). Subsequently, in S112, the counter 1
The value of the counter 112 is added to the value of the counter 112 to determine whether or not the number is 63. If i + j = 63, an EOB (End Of Block) is output (S113).
The encoding of one block is completed. If i + j <63, the counter 1113 is incremented by "+1", and at the same time, the value of the run length counter NNNN is reset (by substituting "0") and the operation is repeated (S11).
4).

With the above-described configuration, even if any code is generated, it is possible to perform smooth coding within a predetermined time for each block. Further, the circuit configuration is inexpensive, simple, and easy to realize. <Fifth Embodiment> FIG. 15 is a block diagram showing the structure of a fifth embodiment of the image compression apparatus according to the present invention. The explanation of the scan order of the DCT coefficients in the inverse scan is shown in FIG.
The description of the scan order of the DCT coefficients in the forward scan will be described with reference to FIG. The image compression apparatus shown in FIG. 15 is slightly different from the configuration shown in FIG.
The same blocks as in FIG. 2 are described with the same numbers.

In this embodiment, after DCT has been performed, FIG.
As in the fourth embodiment shown in FIG. 2, the DCT circuit 1101 does not provide a configuration in which the data is zigzag-scanned and rearranged one-dimensionally and then stored in a buffer. Is switched.

In FIG. 15, reference numerals 1301 and 1302 denote a zigzag inverse scan circuit and a zigzag forward scan circuit for reading out DCT coefficients, respectively.
A zigzag scan is performed to read the zigzag scan from the forward direction (shown in FIG. 4). 1303 is 1301, 13
02 indicates a switch for switching, and in the initial setting, zigzag reverse scan is selected. As in the fourth embodiment, the zigzag inverse scan is selected after the quantization to detect whether the coefficient is a significant coefficient other than "0" and generate a significant coefficient. The switch 1303 selects the zigzag order scan only when a significant coefficient occurs. Therefore, first, the foremost DC component (DCT [0] in the above-described fourth embodiment) shown in FIG. 4 is read, quantized, and then subjected to DPCM and one-dimensional Huffman coding. Next, quantization and coding are sequentially repeated from a low-order component of the AC component to a component at which a significant coefficient finally occurs.

In this embodiment, the configuration of the counters 1112 and 1113 is the same as that of the fourth embodiment. Since the DC component is read in the same manner as the AC component, it is necessary to initialize the counter 1113 to j = 0. However, when i + j = 63, the encoding of one block can be completed.

A more specific example will be described.

FIG. 16 is a diagram for explaining the state of occurrence of coefficients in a certain block after DCT has been performed, FIG. 17 is a diagram showing a state in which FIG. 16 is inversely scanned, and FIG. It is a figure showing a state.

In FIG. 16, the hatched portion indicates a component where some significant coefficient has occurred, and it is assumed that the frequency component in the blank portion is "0". In this case, for the sake of simplicity, it is assumed that no significant coefficient component is converted to "0" by quantization. First, by reverse scan,
From DCT [63], the Q is zigzag in the direction indicated by the arrow.
To find an address where a significant coefficient occurs.
As shown in FIG. 16, since the generation of the significant coefficients is concentrated in the low band (the upper left of the block), the significant coefficients are not DCT 'for the first time.
This occurs at [8] (FIG. 17). (DCT '[n] is shown in FIG.
The value obtained by quantizing DCT [n] as shown in the second embodiment is referred to as DCT ′ [n]. At this time, the counter 1112
Becomes i = 55. Then, this time, the scan is started in the forward direction with DCT [0], and when j = 8, that is, when the encoding reaches DCT '[8], the encoding of one block is completed (FIG. 18).

By doing so, the counter 1112 and the counter 1113 perform the predetermined time (for example, in the case of the block of n × m, the time when i + j = n × m−1), that is, the reading and encoding of one component are performed by one. Assuming the clock, i
= 0, j = 0, including (n × m + 1) clock times), it is possible to encode one block.

[0072]

As described above, according to the present invention, it is determined whether or not the absolute value of the orthogonal transform coefficient data in a predetermined area in a block has a value greater than a predetermined value, and the image type of the block is determined. , And the orthogonal transform coefficient data in the block is adaptively quantized according to the result of the identification, so that the encoding efficiency and image quality can be improved with a very simple configuration without lowering the encoding processing speed. Can be achieved.

Further, according to the present invention, encoding can be performed within a predetermined time regardless of what kind of information is in the block, and the circuit configuration can be reduced in cost and simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a first embodiment of an image compression apparatus according to the present invention.

FIG. 2 is a flowchart illustrating a main operation procedure according to the first embodiment.

FIG. 3 is a diagram showing an inverse scan order of DCT coefficients.

FIG. 4 is a diagram showing a forward scan order of DCT coefficients.

FIG. 5 is a diagram illustrating a relationship between input data of an image scanner input and DCT coefficients;

FIG. 6 is a diagram illustrating a relationship between input data artificially created and DCT coefficients;

FIG. 7 is a diagram illustrating an example of quantization tables 109 and 110.

FIG. 8 is a block diagram showing a main part of a second embodiment of the image compression apparatus according to the present invention.

FIG. 9 shows quantization tables 110-1 according to the second embodiment.
FIG. 13 is a diagram illustrating an example of a thirteenth embodiment.

FIG. 10 is a block diagram showing a main part of a third embodiment of the image compression apparatus according to the present invention.

FIG. 11 is a diagram illustrating an example of a quantization table according to the third embodiment.

FIG. 12 is a block diagram showing the configuration of a fourth embodiment of the image compression apparatus according to the present invention.

FIG. 13 is a flowchart illustrating a main operation procedure according to a fourth embodiment.

FIG. 14 is a flowchart illustrating a main operation procedure according to a fourth embodiment.

FIG. 15 is a block diagram showing the configuration of a fifth embodiment of the image compression apparatus according to the present invention.

FIG. 16 is a diagram for explaining a state of occurrence of coefficients in a certain block after performing DCT.

FIG. 17 is a diagram showing a state in which FIG. 16 is reversely scanned.

FIG. 18 is a diagram showing a state in which FIG. 16 is sequentially scanned.

FIG. 19 is a block diagram showing the configuration of a conventional image compression apparatus.

FIG. 20 is a block diagram showing a detailed configuration of a prediction encoding circuit according to a conventional example.

FIG. 21 is a diagram showing a scan order of DCT coefficients.

FIG. 22 is a diagram illustrating a relationship between AC coefficients and group numbers SSSS.

[Explanation of Signs] 1,100 Input terminal 2 Blocking circuit 17, 101 DCT circuit 40, 114 Q 41, 109, 110, 810, 811, 812, 81
3 Quantization table 42 DPCM 43 One-dimensional Huffman coding circuit 44 DC Huffman code table 45 Scan conversion circuit 46 Significant coefficient detection circuit 47 Run length counter 48 Grouping circuit 49 Two-dimensional Huffman coding circuit 50 AC Huffman coding circuit 51 Multiplexing Circuit 52, 112, 113 output terminal 53 delay circuit 54 subtractor 102, 103, 111, 801 switch 104 reverse scan address generator 105 forward scan address generator 106 absolute value circuit 107 comparator 108, 804 counter determination circuit 802 2 Multiplying circuit 803 Low band power adder 805 High band power adder 1001 Absolute value sum adder 1002 Multiplier

Continuation of the front page (56) References JP-A-3-283989 (JP, A) JP-A-2-305272 (JP, A) JP-A-4-49778 (JP, A) JP-A-2-202271 (JP , A) JP-A-4-207582 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 1/41-1/419 H04N 7/30

Claims (2)

(57) [Claims] An input unit configured to input image data divided into predetermined blocks; a conversion unit configured to convert the image data into orthogonal transform coefficient data for each block; and an orthogonal transform coefficient in a predetermined area in the block. Identification means for determining whether the absolute value of the data has a value equal to or greater than a predetermined value to identify the image type of the block, and orthogonal transform coefficient data in the block according to the identification result of the identification means. An image compression apparatus comprising: a quantization unit that performs quantization. 2. An image data divided into a predetermined block is input, the image data is converted into orthogonal transform coefficient data for each block, and an absolute value of the orthogonal transform coefficient data in a predetermined area in the block is determined. Determining whether there is a value equal to or greater than the value, identifying the image type of the block, and quantizing the orthogonal transform coefficient data in the block according to the identification result of the identification means. Image compression method.