JP3204393B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, it is directly connected to the scribe line along the outer periphery of the semiconductor element formation region to directly cover the upper surface of the lower interlayer insulation film provided on the semiconductor element formation region. And a semiconductor device having an outer peripheral wiring provided between the semiconductor device and the semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device having a multilayer wiring structure, step coverage in each interlayer insulating film covering each underlying wiring layer is important. For example, in a multilayer wiring structure of three or more layers, the lower wiring is covered with a lower interlayer insulating film, the upper metal wiring of the first layer is provided on the surface of the lower interlayer insulating film, and the upper metal wiring of the second layer is formed. It is provided on the surface of the upper interlayer insulating film.
When the metal material forming the upper metal wiring of the first layer is an aluminum-based metal or tungsten, it is not preferable to employ a BPSG film as the upper interlayer insulating film. In such a case, the upper interlayer insulating film is formed by, for example, depositing a first silicon oxide film, spin-coating, heat-treating and etching back an SOG film, and depositing a second silicon oxide film. The function of the SOG film here is to leave the SOG film only on the side surfaces of the upper metal wiring of the first layer, thereby making the upper surface of the upper interlayer insulating film gentle.

In the above-described semiconductor device having a multilayer wiring structure,
In a DRAM having a substrate potential different from a ground potential (V _SS ) or a semiconductor device including an analog circuit requiring a plurality of types of power supply potentials (V _DD ), for example, an outer peripheral wiring formed by an upper metal wiring of a first layer is used. Is provided. In a semiconductor device including an analog circuit, the outer peripheral wiring is used as, for example, a power supply line or a ground line.

Referring to FIG. 30, which is a circuit diagram of an electrostatic protection device, a semiconductor device provided with one ground potential (V _SS ) connection terminal (bonding pad) and one power supply potential (V _DD ) connection terminal In the case of, the outer peripheral wiring composed of the upper metal wiring of the first layer is connected to the common discharge line CDL (c
ommon-discharge-line). Each connection terminal has an electrostatic breakdown (ES
One ends of the protection elements T and D for D) are connected in parallel,
The other end of the protection element is connected to the common discharge line. The protection element T is a voltage clamp element composed of a horizontal parasitic bipolar transistor, and the protection element D is a protection diode. The connection terminals include signal connection terminals such as an input signal connection terminal, an output signal connection terminal, and an input / output signal connection terminal, including the ground potential connection terminal and the power supply potential connection terminal. The common discharge line has a form surrounding the outer periphery of the semiconductor element formation region via the scribe line region, and is electrically connected to the semiconductor substrate. The connection of the common discharge line to the semiconductor substrate has such a form in order to reduce the contact resistance.

FIG. 31, which is a schematic plan view of a semiconductor device,
Referring to FIG. 32, which is a schematic cross-sectional view of the semiconductor device along the line AA in FIG. 31 (in the manufacturing process), and FIG. 33, which is a schematic cross-sectional view of the semiconductor device along the line BB in FIG. Of the prior art having a common discharge line composed of upper metal wiring
Is configured as follows. 32 and 33, the gate oxide film 211 and the SOG film 252A,
Hatching with the SOG film 252a and the SOG film 252b is omitted.

On the surface of a P-type silicon substrate 201, a scribe line region 202 including a (first) P ⁺ -type diffusion layer 214 and a semiconductor element formation region 203 are provided. The semiconductor element forming region 203 includes an element isolation region 20 including an active region 204 and a field insulating film 208.
5 and is defined by the first outer edge of the field insulating film 208 having a rectangular shape. The depth of the diffusion layer of the P ⁺ type diffusion layer 214 is, for example, about 250 nm, and a half of the line width of the scribe line region 202 (belonging to one semiconductor element formation region 203) is, for example, 50 μm.
It is about. The field insulating film 208 is formed, for example, by selective oxidation, and has a thickness of, for example, about 250 nm. An N-type well such as an N-type well 206 is provided in the semiconductor element formation region 203. N-type well 2
Reference numeral 06 denotes a P-channel MOS transistor (constituting a CMOS transistor), which has a junction depth of, for example, about 1 to 2 μm.

The active region 204 on the surface of the N-type well 206
Is provided with a P ⁺ type diffusion layer 213 constituting a P channel MOS transistor. In the active region 204 provided on the surface of the P-type silicon substrate 201 in the semiconductor element formation region 203, an N ⁺ -type diffusion layer 217 constituting an N-channel MOS transistor and a protection element are constituted (second element).
Of the P ⁺ type diffusion layer 215 and the protection element (first)
It constitutes a) N ⁺ -type diffusion layer 218a and a protective element (second) N ⁺ -type diffusion layer 218b and the like.
The depth of the diffusion layer of the P ⁺ type diffusion layer 215 is, for example, 0.25 μm.
m, the junction depth of the P ⁺ -type diffusion layer 213 is, for example, about 0.25 μm, and the N ⁺ -type diffusion layers 217, 21
The depth of the junction between 8a and 218b is, for example, about 0.2 μm.

The P-channel MOS transistor has a P ⁺ type diffusion layer 213, a gate oxide film 211 and a gate electrode 21.
2 and the N-channel MOS transistor is N
^{It comprises a +} type diffusion layer 217, a gate oxide film 211 and a gate electrode 212. The thickness of the gate oxide film is, for example, about 8 nm. The gate electrode 212 has, for example, a tungsten polycide structure in which a tungsten silicide (WSi ₂ ) film having a thickness of about 100 nm is laminated on an N ⁺ type polycrystalline silicon film (not shown in the drawing) having a thickness of 100 nm. The gate lengths of the N-channel and P-channel MOS transistors are, for example, about 0.4 μm and 0.5 μm.

The surface of the semiconductor element forming region 203 including the MOS transistor and the like is covered with a (first) interlayer insulating film 221 having a second outer edge formed of a rectangle. The interlayer insulating film 221 is made of, for example, a silicon oxide-based insulating film having a thickness of about 300 nm. This interlayer insulating film 221 has a (overlap) width of about 1 μm (= interval between the first and second outer edges), for example, P ⁺
It extends over the surface of the scribe line region 202 with a form directly covering the surface of the mold diffusion layer 214. In the interlayer insulating film 221 (through the interlayer insulating film 221), P
^The contact holes 225 and 226 reaching the ⁺ type diffusion layer 213 and the N ⁺ type diffusion layer 217 are provided. On the surface of the interlayer insulating film 221, a tungsten silicide wiring 230 having a thickness of, for example, about 100 nm is provided. The tungsten silicide wiring 230 is connected to the P ⁺ -type diffusion layer 213, the N ⁺ -type diffusion layer 217 and the like via the contact holes 225 and 226, respectively.

[0010] The surface of the interlayer insulating film 221 including the tungsten silicide wiring 230 is covered with a (second) interlayer insulating film 231 having a third outer edge portion formed of a rectangle. The interlayer insulating film 231 has a thickness of, for example, about 400 nm, and is formed by BP reflowed on a silicon oxide film.
It has a structure in which SG films are stacked. This interlayer insulating film 231
Has a form of directly covering the surface of the P ⁺ type diffusion layer 214 with a width of, for example, about 1 μm (= the interval between the second and third outer edges), and extends over the surface of the scribe line region 202. (The interlayer insulating film 231 and the scribe line region 202
(= The distance between the first and third outer edge portions) is, for example, about 2 μm. Interlayer insulating film 23
1, a contact hole 2 penetrating through the interlayer insulating film 231 and the interlayer insulating film 221 and reaching the P ⁺ type diffusion layer 215 and the like.
35, a contact hole 236 reaching the N ⁺ type diffusion layers 217, 218a and the like, and a contact hole 237 reaching the gate electrode 212. Although not shown, a contact hole penetrating only the interlayer insulating film 231 and reaching the tungsten silicide wiring 230 is provided.

On the surface of the interlayer insulating film 231, (first) upper metal wirings 240, 242 made of tungsten (or aluminum alloy) as a first metal material.
243 and a common discharge line 241 (outer peripheral wiring) having a rectangular inner edge and a fourth outer edge. The common discharge line 241 and the upper metal wires 240, 242, 243 are made of, for example, a tungsten film having a thickness of about 400 nm (or an aluminum alloy film having a thickness of, for example, about 600 nm). Common discharge line 24
1 and upper metal wiring 240 (not directly connected thereto)
Is, for example, about 30 μm, and the minimum distance between the upper metal wirings 240, 242, 243 and the like is, for example, 0.5 μm.
The upper metal wirings 242 and 243 have a line width of, for example, about 10 μm. The upper metal wiring 240 is connected to the N ⁺ -type diffusion layer 217 or the gate electrode 2 through the contact hole 236 or the contact hole 237, respectively.
12 and so on. The upper metal wiring 242 is connected to the N ⁺ type diffusion layer 218 a via the contact hole 236, and further connected to the common discharge line 241. The upper metal wiring 243 is connected to the P ⁺ type diffusion layer 215 via the contact hole 235 and further connected to the common discharge line 241.

The common discharge line 241 has a line width of, for example, about 8 μm, and has a width of, for example, about 4 μm (= the distance between the third and fourth outer edge portions) and the surface of the P ⁺ type diffusion layer 214. It extends over the surface of the scribe line area 202 with a direct covering appearance. That is, the overlap width between the common discharge line 241 and the scribe line region 202 (= the distance between the first and fourth outer edge portions) is, for example, about 6 μm, and the overlap width between the common discharge line 241 and the interlayer insulating film 231 is large. The wrap width (= interval between the inner edge portion and the third outer edge portion) is, for example, about 4 μm, and the overlap between the common discharge line 241 and the field insulating film 208 (via the interlayer insulating films 231 and 221). The wrap width (= interval between the inner edge and the first outer edge) is, for example, about 2 μm. The reason why the common discharge line 241 extends to the surface (upper surface) of the interlayer insulating film 231 is to ensure the adhesion of the common discharge line 241 to the base.

The common discharge line 241 and the upper metal wiring 24
The interlayer insulating film 231 including 0, 242, 243 and the like is covered with a third interlayer insulating film. The third interlayer insulating film includes a common discharge line 241 and upper metal wires 240 and 24.
(First) silicon oxide film 251 that directly covers the top and side surfaces of
And the SOG film 25 left on the side surface of the upper wiring 240 and the like.
2A, 252a, 252b (details will be described later) and SO
It is composed of a laminated film of the (second) silicon oxide film 253 covering the silicon oxide film 251 including the G film 252a and the like.
The thickness of the silicon oxide film 251 immediately above the upper metal wirings 240, 242, 243 or the like or the upper surface of the common discharge line 241 is, for example, about 100 nm, and the thickness of the silicon oxide film 251 immediately below the SOG film 253A is, for example, about 400 nm. It is. The thickness of the silicon oxide film 253 is, for example, 500
nm. In the third interlayer insulating film, a contact hole 255 reaching the P ⁺ -type diffusion layer 213 and the like, a contact hole 256 reaching the N ⁺ -type diffusion layer 217 and the N ⁺ -type diffusion layer 218b and the like, and a gate electrode 212, Tungsten silicide wiring 230 or upper metal wiring 24
A contact hole 257 reaching 0 is provided.

On the surface of the third interlayer insulating film, a connection terminal (bonding pad) 260 and an input / output signal connection terminal 260a made of, for example, an aluminum alloy as a second metal material, and a ground line 261 and a power supply Line 262
And (second) upper metal wirings 264a, 265 and the like. The line width of the upper metal wiring 264a is, for example, 1
It is about 0 μm. The thickness of these second upper metal wires is, for example, about 600 nm, and the size of the connection terminal 260, the input / output signal connection terminal 260a, etc. is, for example, 100 μm.
□, and the line width of the ground line 261 and the power line 262 is 1
The distance between the connection terminal 260, the input / output signal connection terminal 260a and the like and the common discharge line 241 is, for example, 90 μm.
It is about μm.

Connection terminal 260, input / output signal connection terminal 26
0a etc. are upper metal wirings 26 directly connected to these.
4a and the contact hole 256, respectively, are connected to the N ⁺ type diffusion layer 218b. A voltage clamp element as a first protection element and a protection diode as a second protection element are connected in parallel between the connection terminal 260, the input / output signal connection terminal 260a, and the like and the common discharge line 241 respectively. . The voltage clamp element is an N ⁺ type diffusion layer 218
The protection diode includes an N ⁺ -type diffusion layer 218b and a P ⁺ -type diffusion layer 215. The protection diode includes a lateral parasitic NPN transistor including a and an N ⁺ -type diffusion layer 218b.

An input buffer and an output buffer are connected to the input / output signal connection terminal 260a. The input buffer is composed of CMOS transistors, and the N
The N ⁺ -type diffusion layer 217 and the P ⁺ -type diffusion layer 213 serving as the source of the channel and P-channel MOS transistors are connected to the ground line 261 and the power supply line 262 (eg, via the upper metal wiring 240 and the upper metal wiring 265). , N-channel and P-channel MOS transistor gate electrodes 21
2 is connected to the input / output signal connection terminal 260a (for example, via the upper metal wiring 240). The distance between the upper metal wiring 240 (connecting the gate electrode 212 and the input / output signal connection terminal 260a) and the common discharge line 241 is, for example, about 30 μm. N-channel, P-channel MOS
N ⁺ type diffusion layer 217 serving as a drain of the transistor, P
^{The +} type diffusion layer 213 is connected to an internal circuit (for example, via the tungsten silicide wiring 230).

The output buffer is a first N-channel MO.
It comprises an S transistor and a load MOS transistor (comprising a second N-channel MOS transistor). One of the N ⁺ type diffusion layer 217 of the source and the drain of the load MOS transistor and the gate electrode 212 are connected to the power supply line 262 (for example, via the upper metal wiring 265). The distance between the upper metal wiring 265 and the common discharge line 241 is, for example, about 30 μm. The other N ⁺ type diffusion layer 217 of the source / drain of the load MOS transistor and the first N
The N ⁺ type diffusion layer 217 serving as the drain of the channel MOS transistor is provided (for example, via the upper metal wiring 240).
The gate electrode 212 of the first N-channel MOS transistor is connected to the internal circuit (for example, via the tungsten silicide wiring 230), and is connected to the input / output signal connection terminal 260a, and becomes the source of the first N-channel MOS transistor. ^{The +} type diffusion layer 217 is connected to the ground line 261 (for example, via the upper metal wiring 265).

Referring to FIG. 32, which is a schematic cross-sectional view of the manufacturing process of the semiconductor device, and FIGS. 31 and 33, the first conventional method of manufacturing a semiconductor device will be described with respect to the point related to the SOG film. Explain with emphasis).

First, an N-type well 206 is formed in a required region on the surface of a P-type silicon substrate 201. After a pad oxide film (not shown) and a silicon nitride film (not shown) are formed on the entire surface and the silicon nitride film is patterned,
A field insulating film 208 having a thickness of about 250 nm is formed by the selective oxidation method. Thereby, the semiconductor element formation region 203, the active region 204, and the element isolation region 205
Is defined. After removing the silicon nitride film and the pad oxide film, a gate oxide film 211 having a thickness of about 8 nm is formed by thermal oxidation. N ⁺ film thickness of about 100 nm
A polycrystalline silicon film and a tungsten silicide film having a thickness of about 100 nm are formed, and the laminated conductor film is patterned to form a gate electrode 212. Using the gate electrode 212, the field insulating film 208, and the like as masks, P-type impurities are respectively introduced to form P ⁺ -type diffusion layers 213, 214, 215, and the like. Thereby, the scribe line area 202 is defined. Similarly, introduction of N-type impurities and the like are performed, and N ⁺ -type diffusion layers 217 and 2
18a, 218b and the like are formed. An interlayer insulating film 221 made of a silicon oxide insulating film of about 300 nm is formed on the entire surface by a vapor phase growth method or the like.
1, contact holes 225, 226 and the like are formed. At this time, an opening is also formed in the scribe line region 202. A tungsten silicide film having a thickness of about 100 nm is formed on the entire surface and is patterned to form a tungsten silicide wiring 230 (FIG. 32).
(A), FIGS. 31, 33].

Next, a silicon oxide film (not shown in the figure) and a BPSG film (not shown in the figure) are sequentially deposited on the entire surface by a vapor phase growth method, and reflow is performed on the BPSG film. Interlayer insulating film 231 having a thickness of about 400 nm
Is formed. The contact hole 2 is formed in the interlayer insulating film 231.
35, 236, 237 and the like are formed. At this time, an opening is also formed in the scribe line region 202. A tungsten film having a thickness of, for example, about 400 nm is formed on the entire surface, and this is patterned, so that the upper metal wiring 240,
The upper metal wiring 242, the upper metal wiring 243, the common discharge line 241 and the like are formed.

Subsequently, for example, a silicon oxide film 251 of about 400 nm is formed on the entire surface by a vapor growth method. After that, the SOG film 252 is formed by a spin coating method. If the SOG film 252 is an organic SOG film, an alkoxyl group (—OR; R is an alkyl group) is used for some Si.
If the SOG film 252 is an inorganic SOG film, hydroxyl (—OH) is bonded to some Si. Since an organic SOG film is less likely to crack than an inorganic SOG film, it is easy to increase the film thickness. Which of the SOG films 252 is selected depends on the purpose. Since the spin coating of the SOG film 252 is performed on the semiconductor devices connected in a wafer state, the semiconductor device formation region 203 is located in the vicinity of any one of the four corners (for example, the corner). (In the range of about 150 to 250 μm from the portion) (the common discharge line 241 acts as a barrier against the spill to the scribe line region 202), and the thickness of the SOG film 252 increases (FIG. 32B).

Next, a heat treatment is performed to remove the solvent of the SOG film 252. Subsequently, the SOG film 252 is etched back by anisotropic etching on the silicon oxide film. Due to this etch back, for example, between the upper metal wiring 242 and the upper metal wiring 243, between the upper metal wiring 240 and the upper metal wiring 243, or between the upper metal wiring 240 and the common discharge line 241, In a portion where the upper metal wiring 1 is in proximity, an SOG film 252A having a form substantially covering the upper surface of the interlayer insulating film 231 therebetween (via the silicon oxide film 251) is left. Even in the vicinity of the corner, the upper surface of the interlayer insulating film 231 has a relatively wide hem (relatively via the silicon oxide film 251) on the side surface on the side without the first upper metal wiring (for example, the upper metal wiring 242). The SOG film 252b (covered with a form) is left. The shape of the SOG film 252A depends on the viscosity of the SOG film, forming conditions, etch-back conditions, and the like. SOG film 25
The same applies to the extent of the spread of the foot of 2b. On the side surface of the common discharge line 241 on the scribe line region 202 side, the SOG film 252a (having a shape narrower than the SOG film 252b) is provided.
Is left behind. In addition, the silicon oxide film 251 is etched by a maximum of about 300 nm by this etch back (FIG. 32C).

Subsequently, a silicon oxide film 253 having a thickness of about 500 nm is formed on the entire surface by a vapor phase growth method, and the formation of the third interlayer insulating film is completed. Contact holes 255, 256, 257 and the like penetrating the third interlayer insulating film and the like are formed. For example, an N ⁺ type diffusion layer 218 b provided between the upper metal wiring 240 and the upper metal wiring 243.
Contact hole 256 reaching the upper metal wiring 2
In the contact holes 256 that reach the N ⁺ -type diffusion layers 217 provided between the SOG film 40 and the common discharge line 241, the SOG film 252A is exposed on a part of the side wall. An aluminum alloy film of about 600 nm is formed on the entire surface. This aluminum film is patterned,
Connection terminal 260, input / output signal connection terminal 260a, ground line 261, power supply line 262, and upper metal wiring 264a, 2
65 (FIG. 32D, FIG. 31, FIG. 3).
3]. Although illustration is omitted, a surface protection film is thereafter formed, an opening is provided in the surface protection film, the wafer is diced, and further, the semiconductor device is completed by packaging.

In the first conventional semiconductor device, one ground potential connection terminal and one power supply potential connection terminal are provided. For example, JP-A-10-214940 discloses that
A semiconductor device provided with a plurality of ground potential connection terminals and a plurality of power supply potential connection terminals is disclosed. According to this patent publication, as an ESD countermeasure between a ground potential connection terminal and a power supply potential connection terminal, a second upper metal wiring made of a second metal material is used (an outer peripheral wiring).
A second common discharge line is provided.

Referring to FIG. 34 which is a circuit diagram of the electrostatic protection device, in the semiconductor device according to the above-mentioned publication, signal connection terminals are connected to the signal connection terminals in the same manner as in the first conventional semiconductor device.
An outer peripheral wiring composed of an upper metal wiring of the first layer is used as a first common discharge line, and each signal connection terminal is provided with E
The first protection element T for SD, the second end of the protective device D ₁ are connected in parallel, the common discharge line CDL-1 protection element T, the other end of the D ₁ is connected.

Each ground potential (V_SS) To the connection terminal
Are the first protection element T (similar to the signal connection terminal),
Protection element D₁ Are connected in parallel, and the common discharge line C
DL-1 has protection elements T and D₁ Is connected to the other end
You. In addition, each ground potential connection terminal (signal
Third protective element D against ESD)
_Two Of the protection element D_Two The other end of (the second gold
The second upper metal wiring made of a metal
A) Common discharge line CDL-2.

Each power supply potential (V_DD) To the connection terminal
Also, like the signal connection terminal, the first protection element T, the second protection element
Protection element D₁ Are connected in parallel, and the common discharge line C
DL-1 has protection elements T and D₁ Is connected to the other end
You. In addition, each power supply potential connection terminal
Fourth protection element D against ESD)
_Three Of the protection element D_Three Is the other end of the common discharge line
CDL-2 connection. The protection element T is a horizontal parasitic bus.
A voltage clamp element consisting of an bipolar transistor
Protection element D₁ , D_Two , D_Three Is a protection diode
You.

FIG. 35 which is a schematic plan view of a semiconductor device;
FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line AA in FIG.
6 and FIG. 37, which is a schematic cross-sectional view of the semiconductor device taken along the line CC in FIG. ing. In FIGS. 36 and 37,
In order to avoid drawing complexity, the gate oxide film 211 and
SOG film 252A, SOG film 252a and SOG film 2
The hatching with 52b is omitted.

On the surface of the P-type silicon substrate 201, a scribe line region 202 including a (first) P ⁺ -type diffusion layer 214 and a semiconductor element formation region 203 are provided. The semiconductor element forming region 203 includes an element isolation region 20 including an active region 204 and a field insulating film 208.
5 and is defined by the first outer edge of the field insulating film 208 having a rectangular shape. A first N-type well 206a,
An N-type well such as the second N-type well 206b is provided.

In the active region on the surface of the N-type well (not shown)
Is a P-channel MOS transistor.⁺ Mold expansion
A scattering layer is provided. P of the semiconductor element formation region 203
Active region 20 provided on the surface of die type silicon substrate 201
4 includes an N channel MOS transistor.⁺ 
Type diffusion layer 217, (second) P constituting a protection element⁺Type
Diffusion layer 215, (first) N constituting protection element⁺ Mold expansion
(Second) N constituting dispersion layer 218a and protection element⁺ 
A mold diffusion layer 218b and the like are provided. N-type well 20
A protection element is formed in the active region 204 provided in 6a.
(Third) P ⁺ Mold diffusion 216a and (third) N⁺ 
A mold diffusion layer 219a is provided. P-type silicon substrate
Area including the boundary between the first and second wells 201 and 206b
In the active region 204 and the N-type well 206b.
The (fourth) N⁺ Diffusion layer
219b and (fourth) P⁺ Mold diffusion layer 216b
It is provided.

For example, an N-channel MOS transistor includes an N ⁺ type diffusion layer 217, a gate oxide film 211, and a gate electrode 212.

The surface of the semiconductor element forming region 203 including the MOS transistor and the like is covered with a (first) interlayer insulating film 221 having a second outer edge formed of a rectangle. This interlayer insulating film 221 has a form of directly covering the surface of the P ⁺ type diffusion layer 214 with an (overlap) width of about 1 μm (= interval between the first and second outer edges), for example. The scribe line region 202 extends on the surface. The interlayer insulating film 221 is provided with a contact hole 226 reaching the N ⁺ type diffusion layer 217 and the like. On the surface of the interlayer insulating film 221, a tungsten silicide wiring 2
30 are provided. Tungsten silicide wiring 2
Reference numeral 30 denotes an N ⁺ type diffusion layer 2 through a contact hole 226 or the like.
17 and so on.

The surface of the interlayer insulating film 221 including the tungsten silicide wiring 230 is covered with a (second) interlayer insulating film 231 having a third outer edge formed of a rectangle. The insulating film 231 is, for example, 1 μm
Of the order of width (= interval between the second and third outer edges)
^It has a form that directly covers the surface of ⁺ type diffusion layer 214 and extends on the surface of scribe line region 202 (the overlap width between interlayer insulating film 231 and scribe line region 202 (= the first width and the first width). The distance between the third outer edges is, for example, about 2 μm). In the interlayer insulating film 231, a contact hole 235 penetrating through the interlayer insulating film 231 and the interlayer insulating film 221 and reaching the P ⁺ -type diffusion layers 215 and the like, and a contact hole 236 reaching the N ⁺ -type diffusion layers 217 and 218 a and the like.
And a contact hole 237 reaching the gate electrode 212. Further, although not shown, the tungsten silicide wiring 2 penetrates only through the interlayer insulating film 231.
A contact hole reaching 30 is provided.

On the surface of the interlayer insulating film 231, (first) upper metal wirings 240, 242 made of tungsten (or aluminum alloy) as a first metal material.
243 and the (first) common discharge line 24 which is an outer peripheral wiring having a rectangular inner edge and a fourth outer edge.
1 is provided. The minimum distance between the common discharge line 241 and the upper metal wiring 240 (not directly connected thereto) is, for example, about 30 μm.
For example, the minimum distance between the upper metal wirings 242 and 243 is, for example, about 10 μm.
m. The upper metal wiring 240 is formed in the contact hole 2
36 or via a contact hole 237 or the like, respectively, to the N ⁺ type diffusion layer 217 or the gate electrode 212 or the like. The upper metal wiring 242 is formed in the contact hole 23.
6, and connected to the N ⁺ type diffusion layer 218a.
The common discharge line 241 is connected. Upper layer metal wiring 24
3 is a P ⁺ type diffusion layer 215 through a contact hole 235.
, And further connected to the common discharge line 241.

[0035] common discharge line 241 has, for example, a line width of about 8 [mu] m, for example, in 4μm a width of about (= distance between the third and fourth outer edges) of the surface of the P ⁺ -type diffusion layer 214 It extends over the surface of the scribe line area 202 with a direct covering feature. That is, the overlap width between the common discharge line 241 and the scribe line region 202 (= the distance between the first and fourth outer edge portions) is, for example, about 6 μm, and the overlap width between the common discharge line 241 and the interlayer insulating film 231 is large. The wrap width (= interval between the inner edge portion and the third outer edge portion) is, for example, about 4 μm, and the overlap between the common discharge line 241 and the field insulating film 208 (via the interlayer insulating films 231 and 221). The wrap width (= interval between the inner edge and the first outer edge) is, for example, about 2 μm.

The common discharge line 241 and the upper metal wiring 24
The interlayer insulating film 231 including 0, 242, 243 and the like is covered with a third interlayer insulating film. The third interlayer insulating film includes a common discharge line 241 and upper metal wires 240 and 24.
(First) silicon oxide film 251 that directly covers the top and side surfaces of
And the SOG film 25 left on the side surface of the upper wiring 240 and the like.
2A, 252a, 252b, and a (second) silicon oxide film 253 covering the silicon oxide film 251 including the SOG film 252a and the like. The third interlayer insulating film has a contact hole 255 reaching the P ⁺ -type diffusion layers 216a and 216b and a contact hole reaching the N ⁺ -type diffusion layer 217 or the N ⁺ -type diffusion layers 218b, 219a and 219b. 256, the gate electrode 212, the tungsten silicide wiring 230 or the upper metal wiring 24
A contact hole 257 reaching 0 is provided.

[0037] On the surface of the third interlayer insulating film, a second metal material for example input and output signal connection terminals 260a made of an aluminum alloy, a ground potential (V _SS) connecting terminals 260
b and a connection terminal such as a power supply potential (V _DD ) connection terminal 260b, a ground line 261 and a power supply line 262, and (second)
The common discharge line 263 and the (second) upper metal wiring 264
a, 264b, 264c, 265, 266, etc. are provided. The line width of the common discharge line 263 is, for example, about 8 μm, and the upper metal wires 264a, 264b, 264c,
The line width of 266 is, for example, about 10 μm. The common discharge line 263 is provided almost directly above the common discharge line 241 via the third interlayer insulating film. Upper layer metal wiring 266
Are directly connected to the common discharge line 263, and are further connected to the N through the contact hole 256 or the contact hole 255.
⁺ Diffusion layer 219a or P ⁺ diffusion layer 216b. The size of the input / output signal connection terminal 260a and the like is, for example, about 100 μm □, the line width of the ground line 261 and the power supply line 262 is 10 μm or more, and the distance between the input / output signal connection terminal 260a and the like and the common discharge line 241 is For example, 9
It is about 0 μm.

Signal connection terminals such as input / output signal connection terminal 260a are connected to upper metal wiring 264 directly connected thereto.
a and the N ⁺ -type diffusion layer 218 b via the contact hole 256. I / O signal connection terminal 2
A voltage clamp element as a first protection element and a first protection diode as a second protection element are connected in parallel between a signal connection terminal such as 60 a and the common discharge line 241. Voltage clamp element is N ⁺ type diffusion layer 2
Consists lateral parasitic NPN transistor comprising 18a and the N ⁺ -type diffusion layer 218b, a first protection diode comprises an N ⁺ -type diffusion layer 218b and the P ⁺ -type diffusion layer 215.

Each ground potential connection terminal 260b is
The upper metal wiring 264b connected to the N ⁺ -type diffusion layer 218b via the upper metal wiring 264a and the contact hole 256 directly connected thereto, and directly connected thereto.
P ⁺ -type diffusion layer 216 a through contact hole 255
It is connected to the. Each ground potential connection terminal 260
b and the common discharge line 241, a voltage clamp element as a first protection element and a first protection diode as a second protection element are connected in parallel, respectively, and are connected in common with the respective ground potential connection terminals 260b. A second protection diode, which is a third protection element, is connected between the discharge line 263 and the discharge line 263. The second protection diode is an N ⁺ type diffusion layer 2
19a and a P ⁺ type diffusion layer 216a.

Each power supply potential connection terminal 260c is
The upper metal wiring 264c connected to the N ⁺ -type diffusion layer 218b via the upper metal wiring 264a and the contact hole 256 directly connected thereto, and directly connected thereto.
N ⁺ -type diffusion layer 219b through the contact hole 256
It is connected to the. Each power supply potential connection terminal 260
A voltage clamp element as a first protection element and a first protection diode as a second protection element are connected in parallel between c and the common discharge line 241, respectively, and are connected to the respective power supply potential connection terminals 260c. A third protection diode, which is a fourth protection element, is connected between the discharge line 263 and the discharge line 263. The third protection diode includes an N ⁺ type diffusion layer 219b and a P ⁺ type diffusion layer 216b (further, a P ⁺ type diffusion layer 215).

An input buffer and an output buffer are connected to the input / output signal connection terminal 260a. Illustration of the input buffer is omitted. The output buffer comprises a first N-channel MOS transistor and a load MOS transistor (comprising a second N-channel MOS transistor).
N of one of source and drain of load MOS transistor
⁺ Type diffusion layer 217 and gate electrode 212 are connected to power supply line 262 (for example, via upper metal wiring 240).
The distance between the upper metal wiring 240 and the common discharge line 241 is, for example, about 30 μm. The other N ⁺ -type diffusion layer 217 of the source / drain of the load MOS transistor and N serving as the drain of the first N-channel MOS transistor
⁺ Type diffusion layer 217 is connected to input / output signal connection terminal 260 a (for example, via upper metal wiring 265), and gate electrode 212 of the first N-channel MOS transistor is connected (for example, via tungsten silicide wiring 230).
An N ⁺ -type diffusion layer 217 connected to an internal circuit and serving as a source of the first N-channel MOS transistor is connected to a ground line 261 (for example, via an upper metal wiring 265).

[0042]

Conventionally, in order to avoid a defect of a semiconductor device which depends on a manufacturing process after a wafer process, a semiconductor device forming region close to a scribe line region is provided with a semiconductor device. Formation has been avoided. By improving the above-mentioned manufacturing process accompanying the high integration of the semiconductor device, it is possible to provide the semiconductor element at the peripheral portion of the semiconductor element forming region at least about 30 μm away from the scribe line region while avoiding the above-described defect. It is becoming.

However, the conventional first and second conventional techniques described above
The semiconductor device has a multi-layer wiring structure of three or more layers as in the semiconductor device of (1), wherein the first metal material forming the first upper metal wiring is made of an aluminum alloy or tungsten,
In a semiconductor device having an outer peripheral wiring like a common discharge line of an upper metal wiring and a second upper metal wiring made of an aluminum alloy as a second metal material,
The defect related to the method of manufacturing the interlayer insulating film between the upper metal wiring and the second upper metal wiring is likely to occur. A part of the interlayer insulating film includes an SOG film formed by spin coating, heat-treated, and further etched back.

As shown in FIGS. 31 to 33 or FIGS. 35 to 37, in the semiconductor device, the SOG film 252
In the semiconductor element formation region near the corner portion (at least one of the four corner portions) of the semiconductor element formation region, the thickness of the SOG 252 in the other portion is larger than that in the semiconductor device formation region. Even if the etch back is performed in such a state (after the heat treatment), the common discharge line 241 as the outer peripheral wiring is formed in the scribe line region 2 of the SOG film 252.
In this part, the SOG film 252A has the shape of the SOG film, so that the SOG film easily remains. In the vicinity of the corner, the SOG film 252
The place where A is likely to be left is a portion sandwiched between the first upper metal wiring (including the common discharge line 241) and the first upper metal wiring or the lower wiring. In particular, between the upper metal wiring 242 and the upper metal wiring 243 constituting the protection element of the connection terminal 260a (provided near the corner), these wirings and the common discharge line 241 are formed in a U-shape. Since the connection is established, the SOG film 252A is easily left. For the same reason, the connection terminal (for example, the ground potential connection terminal 260b,
Also at the power supply potential connection terminal 260c), the upper metal wiring 242 and the upper metal wiring 24
3, the SOG film 252A tends to remain.

In the case of an inorganic SOG film, when the solvent is removed by heat-treating the inorganic SOG film, the SOG film itself is exposed to a dehydration reaction (by moisture (H ₂ O) from —OH groups). Since the SOG film shrinks due to the dehydration reaction, cracks are likely to occur in an inorganic SOG film having a large thickness. However, it is extremely difficult to carry out this dehydration reaction on the wall, and the heat-treated inorganic SOG
In the film, a small amount of H ₂ O or unreacted —O
The H group will remain. On the other hand, in the organic SOG film, the solvent is removed by the heat treatment, but the elimination of the alkoxyl group (-OR) does not occur. As is evident from this, the organic SOG film does not easily shrink even when subjected to heat treatment.

When a contact hole 256 or the like is formed in a portion of the third interlayer insulating film where the SOG film 252A is left,
SOG films 252A are formed on the side surfaces of these contact holes 256.
Will be exposed. Upper metal wirings 265, 264a connected to N ⁺ type diffusion layers 217, 218b via these contact holes 256 are formed. SO
When the G film 252A is made of an inorganic SOG film, these upper metal wirings 265 and 264a are formed of the remaining moisture, -O
Corrosion due to H groups is likely to occur. On the other hand, the SOG film 25
If 2A is made of an inorganic SOG film, contact hole 2
56 alkoxyl group or an alkyl group remaining on the SOG film 252A in the formation process of the N ⁺ -type diffusion layer 21
7,218b reacts with Si on the surface to form contact hole 2
Silicon carbide (SiC) can be easily formed at the bottom of 56. Therefore, the contact resistance between upper metal wirings 265 and 264a and N ⁺ -type diffusion layers 217 and 218b tends to be extremely high. In particular, when the contact resistance between the upper metal wiring 264a constituting the protection element and the N ⁺ type diffusion layer 218b increases, the function as the protection circuit will be significantly reduced.

Therefore, the purpose of the semiconductor device of the present invention is to
An object of the present invention is to provide a semiconductor device having an outer peripheral wiring having the above-mentioned configuration, which has a structure that facilitates the flow of an SOG film into a scribe line region during spin coating. Still another object of the present invention is to provide a structure in which exposure of the SOG film on the side surface of the contact hole in the vicinity of a corner portion of the semiconductor element formation region is easy to avoid, thereby suppressing corrosion of the uppermost metal wiring or improving the uppermost layer. It is an object of the present invention to provide a semiconductor device having a structure that can easily suppress an increase in contact resistance of a metal wiring.

[0048]

[0049]

According to a first preferred embodiment of the semiconductor device of the present invention, a scribe line region including a first P ⁺ type diffusion layer and an active region are formed on a surface of a P type silicon substrate. And a device isolation region including a field isolation film. The semiconductor device region is defined by a first outer edge of the field insulation film having a rectangular shape. The active region is provided with at least first and second N ⁺ -type diffusion layers and a second P ⁺ -type diffusion layer, and the voltage clamp element serving as the first protection element includes these first N ⁺ -type diffusion layers. And a second N ⁺ -type diffusion layer, and a first protection diode as a second protection element includes these second N ⁺ -type diffusion layer and a second P ⁺ -type diffusion layer. And the semiconductor element region is covered with the first interlayer insulating film. The first interlayer insulating film has a second outer edge, and the second outer edge is provided so as to directly cover the surface of the scribe line region. The first interlayer insulating film is covered with the first interlayer insulating film, the second interlayer insulating film has a third outer edge, and the third outer edge is a surface of the scribe line region. And a first common metal line made of a first metal material and a first common discharge line (CDL) are provided on the surface of the second interlayer insulating film. The first common discharge line is connected to the first N ⁺ -type diffusion layer and the second P ⁺ -type diffusion layer via the first upper metal wiring, respectively. At least a portion of a common discharge line is provided along the first outer edge, and the first common discharge line is a fourth outer edge. An inner edge, and the fourth outer edge is provided so as to directly cover the surface of the scribe line region, and is provided along the first outer edge. The inner edge of the portion is provided so as to directly cover the surface of the second interlayer insulating film, and the first common discharge line is
The semiconductor element in which the inner edge at a portion provided along the first outer edge is provided between the second outer edge and the third outer edge. The first portion near the corner of the formation region and the inner edge at a portion provided along the first outer edge are connected to the first portion via the second interlayer insulating film. A second portion provided on the interlayer insulating film, the second interlayer insulating film including the upper surface and the side surface of the first upper metal wiring and the first common discharge line; Covered with interlayer insulating film,
A first silicon oxide film that directly covers the upper surface and side surfaces of the first upper metal wiring and the first common discharge line and a surface of the second interlayer insulating film;
The S remaining on the side surfaces of the first upper metal wiring and the first common discharge line via the first silicon oxide film is formed.
An OG film, and a second silicon oxide film including these SOG films and covering the first silicon oxide film.
A second upper metal wiring and a connection terminal (bonding pad) made of a second metal material are provided on the surface of the third interlayer insulating film, and these connection terminals are connected to the second upper metal wiring. And the second, third and fourth outer edge portions are connected to the second N ⁺ type diffusion layer through
Have a rectangular shape .

The second preferred embodiment of the semiconductor device of the present invention has the following configuration different from that of the first embodiment. At least a first and a second N-type well are provided in the semiconductor element region, and a third P ⁺ -type diffusion and a third N-type well are provided in an active region provided in the first N-type well.
⁺ Diffusion layer is provided, and the second protection diode, which is the third protection element, includes the third P ⁺ diffusion layer and the third N ⁺ diffusion layer, and includes a silicon substrate and the second N ⁺ diffusion layer. A fourth N ⁺ type diffusion layer and a fourth P ⁺ type diffusion layer are provided in the active region provided in the region including the boundary with the type well and the active region provided in these second N type wells. DOO are respectively provided, a third protection diode is a fourth protection element consists of these fourth P ⁺ -type diffusion and fourth N ⁺ -type diffusion layer on the surface of the third interlayer insulating film Represents a second common discharge line made of a second metal material, a plurality of signal connection terminals made of the second metal material, and a ground potential (V
_CC ) connection terminal and a power supply potential (V _DD ) connection terminal, at least a part of the second common discharge line is provided along a first outer edge, and the second common discharge line is provided. The electric wire is connected to the third N ⁺ -type diffusion layer and the fourth P-type diffusion layer via the second upper-layer metal wiring and the first upper-layer metal wiring, respectively.
^{And the} signal connection terminal is connected to the second N ⁺ -type diffusion layer via a second upper metal wiring, and the ground potential connection terminal is connected via a second upper metal wiring. These second N ⁺ type diffusion layers and the third P
⁺ Type diffusion layer, and the power supply potential connection terminal is connected to the second
Are connected to these second N ⁺ -type diffusion layers and the fourth N ⁺ -type diffusion layers, respectively, through upper metal wirings.

Preferably, in the first and second aspects, the second, third and fourth outer edge portions are each rectangular, and further at a position apart from the first portion, The inner edge at a portion provided along the first outer edge is the second outer edge and the third edge.
A third portion provided between the first portion and the outer edge of the first portion.
Have a common discharge line. A semiconductor device in which the connection terminals, such as signal connection terminals, are provided at a predetermined interval on the surface of the third interlayer insulating film on the semiconductor element formation region near the first outer edge portion , The third portion of the first common discharge line is connected to a first upper metal wiring connected to the first N ⁺ -type diffusion layer and to the second P ⁺ -type diffusion layer. And the first upper metal wiring.

More preferably, in the first and second aspects, the second and third outer edge portions each form a rectangle, and the third outer edge portion in the first portion and the third outer edge portion are connected to each other. The distance between the fourth outer edge and the fourth outer edge is wider than the distance between the third outer edge and the fourth outer edge in the second portion excluding the vicinity of the first portion. Has become. Further, at a position distant from the first portion, the inner edge portion at a portion provided along the first outer edge portion is connected to the second outer edge portion and the third outer edge portion. The first common discharge line has a third portion provided between the first common discharge line and the third outer edge and the fourth outer edge of the first and third portions. The distance from the end is wider than the distance between the third outer edge and the fourth outer edge in the second portion excluding the vicinity of the first and third portions. I have. A semiconductor device in which the connection terminals, such as signal connection terminals, are provided at a predetermined interval on the surface of the third interlayer insulating film on the semiconductor element formation region near the first outer edge portion If it is,
The third portion of the first common discharge line is the first N
The first upper metal wiring connected to the ⁺ type diffusion layer and the second upper metal wiring.
And the first upper metal wiring connected to the P ⁺ type diffusion layer.

According to a third preferred aspect of the semiconductor device of the present invention, a scribe line region including a first P ⁺ type diffusion layer, an active region and a field insulating film are provided on a surface of a P type silicon substrate. And a semiconductor element region constituted by an element isolation region comprising: a semiconductor element region defined by a first outer edge of the field insulating film having a rectangular shape; and a corner of the semiconductor element formation region. A first silicon nitride film which directly covers the surface of the field insulating film and covers the surface of the scribe line region via a pad oxide film in the vicinity of the portion, and at least the first and second silicon nitride films are provided in the active region the N ⁺ -type diffusion layer and the second P ⁺ -type diffusion layer is provided, the voltage clamping device first of these N ⁺ -type diffusion layer and the second is the first protection element
Of comprises an N ⁺ -type diffusion layer, the first protective diode is a second protection element comprises a second N ⁺ -type diffusion layer and the second P ⁺ -type diffusion layer thereof, the first The semiconductor element region except for the silicon nitride film is covered with a first interlayer insulating film, and the first interlayer insulating film directly covers a part of the surface of the first silicon nitride film;
The first interlayer insulating film has a second outer edge, and the second outer edge directly covers the surfaces of the first silicon nitride films, and the first silicon nitride film has a second outer edge. In a region excluding the film, the scribe line region is provided so as to directly cover the surface of the scribe line region.
The second interlayer insulating film directly covers a part of the surface of the first silicon nitride film, and the second interlayer insulating film has a third outer edge. The third outer edge directly covers the surface of the first silicon nitride film, and in a region excluding the first silicon nitride film, directly covers the surface of the scribe line region. A first upper metal wiring made of a first metal material and a first common discharge line are provided on a surface of the second interlayer insulating film; Are respectively connected to the first N ⁺ -type diffusion layer and the second P ⁺ -type diffusion layer via the first upper metal wiring,
At least a portion of the first common discharge line is provided along the first outer edge, and the first common discharge line has a fourth outer edge and an inner edge. The fourth outer edge is provided so as to directly cover the surface of the scribe line region, and the inner edge at a portion provided along the first outer edge. The portion directly covers the surface of the first silicon nitride film in a region where the first silicon nitride film is provided, directly intersects with the third outer edge portion, and The second outer edge portion is provided so as to intersect with the second outer edge portion via an insulating film, and the portion where the first silicon nitride film does not exist is provided through the second interlayer insulating film. The first upper metal wiring and the first upper metal wiring are provided so as to cover the surface of the first interlayer insulating film. The second interlayer insulating film including the upper surface and the side surfaces of the through-discharge lines and a part of the surface of the silicon nitride film is covered with a third interlayer insulating film, and the third interlayer insulating film is A first silicon oxide film directly covering the upper surface and side surfaces of the first upper metal wiring and the first common discharge line, the surface of the second interlayer insulating film, and a part of the surface of the first silicon nitride film; And an SOG film left on the side surfaces of the first upper metal wiring and the first common discharge line via the first silicon oxide film; and the first silicon oxide including these SOG films. A second silicon oxide film covering the film, and a second upper metal wiring and a connection terminal made of a second metal material are provided on the surface of the third interlayer insulating film. Via the second upper metal wiring Characterized in that it is connected to the N ⁺ -type diffusion layer.

The fourth preferred embodiment of the semiconductor device of the present invention has the following configuration different from that of the third embodiment. At least a first and a second N-type well are provided in the semiconductor element region, and a third P ⁺ -type diffusion and a third N-type well are provided in an active region provided in the first N-type well.
⁺ Diffusion layer is provided, and the second protection diode, which is the third protection element, includes the third P ⁺ diffusion layer and the third N ⁺ diffusion layer, and includes a silicon substrate and the second N ⁺ diffusion layer. A fourth N ⁺ type diffusion layer and a fourth P ⁺ type diffusion layer are provided in the active region provided in the region including the boundary with the type well and the active region provided in these second N type wells. DOO are respectively provided, a third protection diode is a fourth protection element consists of these fourth P ⁺ -type diffusion and fourth N ⁺ -type diffusion layer on the surface of the third interlayer insulating film Represents a second common discharge line made of a second metal material, a plurality of signal connection terminals made of the second metal material, and a ground potential (V
_CC ) connection terminal and a power supply potential (V _DD ) connection terminal, at least a part of the second common discharge line is provided along a first outer edge, and the second common discharge line is provided. The electric wire is connected to the third N ⁺ -type diffusion layer and the fourth P-type diffusion layer via the second upper-layer metal wiring and the first upper-layer metal wiring, respectively.
^{And the} signal connection terminal is connected to the second N ⁺ -type diffusion layer via a second upper metal wiring, and the ground potential connection terminal is connected via a second upper metal wiring. These second N ⁺ type diffusion layers and the third P
⁺ Type diffusion layer, and the power supply potential connection terminal is connected to the second
Are connected to these second N ⁺ -type diffusion layers and the fourth N ⁺ -type diffusion layers, respectively, through upper metal wirings.

Preferably, in the third and fourth aspects, the fourth outer edge and the inner edge at a portion provided along the first outer edge are respectively formed. It has a rectangular shape. Further, a second silicon nitride film is provided at a position distant from the first silicon nitride film, directly covering the surface of the field insulating film, and covering the surface of the scribe line region via a pad oxide film, A part of the surface of the second silicon nitride film is directly covered with the first and second interlayer insulating films, respectively, and the inner surface at a portion provided along the first outer edge. The edge is provided so as to directly cover the surface of the second silicon nitride film. A semiconductor device in which the connection terminals, such as signal connection terminals, are provided at a predetermined interval on the surface of the third interlayer insulating film on the semiconductor element formation region near the first outer edge portion In the case of the above, the second silicon nitride film is connected to the first N ⁺ type diffusion layer by the first silicon nitride film.
Is provided in a region including a portion sandwiched between the upper metal wiring and the first upper metal wiring connected to the second P ⁺ -type diffusion layer.

More preferably, in the third and fourth aspects, the fourth outer edge is rectangular, and the inner edge directly covers the surface of the first silicon nitride film. , The overlap width of the first common discharge line and the first silicon nitride film in the first common discharge line at a portion where the inner edge crosses the second outer edge. And the width of the overlap with the first silicon nitride film. Further, a second silicon nitride film is provided at a position distant from the first silicon nitride film, which directly covers the surface of the field insulating film and covers the surface of the scribe line region via a pad oxide film, Part of the surface of the second silicon nitride film is directly covered by the first and second interlayer insulating films, respectively, and further, the part of the surface provided along the first outer edge is formed. An inner edge is provided so as to directly cover the surface of the second silicon nitride film, and the inner edge is provided at a position where the inner edge directly covers the surface of the second silicon nitride film. One common discharge line and their second
The overlap width between the first common discharge line and the second silicon nitride film at the portion where the inner edge crosses the second outer edge is defined as the width of the overlap with the silicon nitride film. It is narrower than the width. A semiconductor device in which the connection terminals, such as signal connection terminals, are provided on the surface of the third interlayer insulating film on the semiconductor element formation region near the first outer edge at a predetermined interval; Wherein the second silicon nitride film comprises a first upper metal interconnect connected to the first N ⁺ type diffusion layer and a first upper metal interconnect connected to the second P ⁺ type diffusion layer. It is provided in a region including a portion sandwiched between the wirings.

Still preferably, in the third and fourth aspects, the first outer edge and the first outer edge at a portion where the inner edge directly covers the surface of the first silicon nitride film. 4 are spaced apart from the outer edges of these first
The distance between the first outer edge and the fourth outer edge at a position distant from the silicon nitride film is wider than the distance between the first outer edge and the fourth outer edge. The overlap width between the first common discharge line and the first silicon nitride film in the portion directly covering the surface is such that the inner edge of the first common discharge line is the second silicon nitride film on the first silicon nitride film. The overlap width between the first common discharge line and the first silicon nitride film at a portion intersecting the outer edge is narrower. Further, a second silicon nitride film is provided at a position distant from the first silicon nitride film, which directly covers the surface of the field insulating film and covers the surface of the scribe line region via a pad oxide film, Part of the surface of the second silicon nitride film is directly covered by the first and second interlayer insulating films, respectively,
Further, the inner edge at a portion provided along the first outer edge is provided so as to directly cover the surfaces of the second silicon nitride films, and the inner edge is provided. The distance between the first outer edge and the fourth outer edge at a portion whose end directly covers the surface of the second silicon nitride film is equal to the distance between the first silicon nitride film and the first silicon nitride film. The distance between the first outer edge and the fourth outer edge at a position distant from the second silicon nitride film is wider than the distance between the first outer edge and the fourth outer edge, and the inner edge is the second silicon nitride. The overlap width of the first common discharge line and the second silicon nitride film in the portion directly covering the surface of the film is such that the inner edge crosses the second outer edge. Between the first common discharge line and the second silicon nitride film at Burlap is narrower than the width. A semiconductor device in which the connection terminals, such as signal connection terminals, are provided at a predetermined interval on the surface of the third interlayer insulating film on the semiconductor element formation region near the first outer edge portion In the case of the above, the second silicon nitride film is
Is provided in a region including a portion sandwiched between the first upper-layer metal wiring connected to the N ⁺ -type diffusion layer and the first upper-layer metal wiring connected to the second P ⁺ -type diffusion layer. I have.

[0058]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic plan view of the semiconductor device, FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line AA and BB in FIG. 1, and a schematic cross-sectional view of the semiconductor device is taken along line DD in FIG. 3, the semiconductor device according to the first example of the first embodiment of the present invention is configured as follows. In FIGS. 2 and 3, the gate oxide film 111 and the SO
Hatching with the G film 152a and the SOG film 152b is omitted.

On the surface of the P-type silicon substrate 101, a scribe line region 102 including a (first) P ⁺ -type diffusion layer 114 and a semiconductor element formation region 103 are provided. The semiconductor element formation region 103 includes an element isolation region 10 including an active region 104 and a field insulating film 108.
5 and is defined by the first outer edge of the field insulating film 108 which is a rectangle. The depth of the diffusion layer of the P ⁺ type diffusion layer 114 is, for example, about 250 nm, and a half of the line width of the scribe line region 102 (belonging to one semiconductor element formation region 103) is, for example, 50 μm.
It is about. The field insulating film 108 is formed by, for example, selective oxidation and has a thickness of, for example, about 250 nm. An N-type well such as an N-type well 106 is provided in the semiconductor element formation region 103. N-type well 1
Reference numeral 06 denotes a P-channel MOS transistor (constituting a CMOS transistor), which has a junction depth of, for example, about 1 to 2 μm.

Active region 104 on the surface of N-type well 106
Is provided with a P ⁺ type diffusion layer 113 constituting a P-channel MOS transistor. In the active region 104 provided on the surface of the P-type silicon substrate 101 in the semiconductor element formation region 103, an N ⁺ type diffusion layer 117 forming an N-channel MOS transistor and a protection element are formed (second).
Of the P ⁺ type diffusion layer 115 and the protection element (the first).
It constitutes a) N ⁺ -type diffusion layer 118a and a protective element (such as a second) N ⁺ -type diffusion layer 118b is provided.
The depth of the diffusion layer of the P ⁺ type diffusion layer 115 is, for example, 0.25 μm.
m, the junction depth of the P ⁺ type diffusion layer 113 is, for example, about 0.25 μm, and the N ⁺ type diffusion layers 117, 11
The junction depth of 8a and 118b is, for example, about 0.2 μm.

The P channel MOS transistor has a P ⁺ type diffusion layer 113, a gate oxide film 111 and a gate electrode 11.
2 and the N-channel MOS transistor is N
It is composed of a ⁺ type diffusion layer 117, a gate oxide film 111 and a gate electrode 112. The thickness of the gate oxide film 111 is, for example, about 8 nm. The gate electrode 112
For example, it has a tungsten polycide structure in which a tungsten silicide (WSi ₂ ) film having a thickness of about 100 nm is laminated on an N ⁺ type polycrystalline silicon film (not shown in the drawing) having a thickness of 100 nm. The gate lengths of the N-channel and P-channel MOS transistors are, for example, about 0.4 μm and 0.5 μm.

The surface of the semiconductor element forming region 103 including the MOS transistor and the like is covered with a (first) interlayer insulating film 121 having a rectangular second outer edge. The interlayer insulating film 121 has a thickness of, for example, about 300 nm, and is formed by stacking, for example, a BPSG film reflowed on a silicon oxide film. The interlayer insulating film 121 has an appearance of directly covering the surface of the P ⁺ type diffusion layer 114 with a (overlap) width of about 1 μm (= interval between the first and second outer edges), for example, and is scribed. It extends on the surface of the line region 102. In the interlayer insulating film 121 (through the interlayer insulating film 121), the P ⁺ type diffusion layer 113, N ⁺
Contact holes 125 and 126 reaching mold diffusion layer 117 and the like.
Etc. are provided. On the surface of the interlayer insulating film 121,
For example, a tungsten silicide wiring 130 (a lower wiring) having a thickness of about 100 nm is provided. The tungsten silicide wiring 130 is connected to the P ⁺ type diffusion layer 1 through the contact holes 125 and 126, respectively.
13, N ⁺ type diffusion layer 117 and the like.

Including tungsten silicide wiring 130
In this case, the surface of the interlayer insulating film 121 is
Covered by (second) interlayer insulating film 131 having side edge portions
Have been The interlayer insulating film 131 is, for example, about 400 nm.
BP having a film thickness of about 10 degrees and reflowed on a silicon oxide film
It has a structure in which SG films are stacked. This interlayer insulating film 131
Has a width of, for example, about 1 μm (= the second and third outer edges
P at end spacing)⁺ Figure that directly covers the surface of diffusion layer 114
Extending over the surface of the scribe line region 102
(The interlayer insulating film 131 and the scribe line region 102
Overlap width (= the first and third outer edge ends)
The interval is, for example, about 2 μm). Interlayer insulating film 131
Through the interlayer insulating film 131 and the interlayer insulating film 121
Then N ⁺ Contour reaching the diffusion layers 117, 118a, etc.
Contact 136 and the contact reaching the gate electrode 112
A hole 137 and P (not shown)⁺ The condenser that reaches the mold diffusion layer
A tact hole is provided. Further, illustration is omitted.
However, the tungsten silicon
A contact hole reaching the side wiring 130 is provided.
You.

On the surface of the interlayer insulating film 131, (first) upper metal wirings 140, 142, 142 made of tungsten (or aluminum alloy) as a first metal material
143, and a common discharge line 141a (outer peripheral wiring) having an inner edge and a fourth outer edge made of a rectangle are provided. At this time, although not shown, a titanium (Ti) film is formed on the bottom of the upper metal wiring by titanium nitride (Ti).
N) A barrier film formed by laminating films is provided. The common discharge line 141a and the upper metal wires 140, 142,
Reference numeral 143 denotes a tungsten film having a thickness of, for example, about 400 nm (or an aluminum alloy film having a thickness of, for example, about 600 nm). The minimum distance between the common discharge line 141a and the upper metal wiring 140 (not directly connected thereto) is, for example, about 30 μm.
2, 143, etc., is about 0.5 μm, for example, and the line width of the upper metal wirings 142, 143 is, for example, 10 μm.
m. The upper metal wiring 140 is formed in the contact hole 1
It is connected to the N ⁺ -type diffusion layer 117 or the gate electrode 112 or the like via the contact hole 36 or the contact hole 137 or the like. The upper metal wiring 142 is formed in the contact hole 13.
6, and connected to the N ⁺ type diffusion layer 118a.
It is connected to the common discharge line 141a. Upper layer metal wiring 1
43 denotes a P ⁺ type diffusion layer 11 via a contact hole 135.
5 and further to the common discharge line 141a.

The common discharge line 141a has a first portion and a second portion. The first part of the common discharge line 141a is
It is provided between a corner portion of the semiconductor element formation region 203 and a position separated from them by, for example, about 130 to 150 μm. The portion of the common discharge line 141a other than the first portion is a second portion.

The inner edge of the common discharge line 141a in the first portion is between the second outer edge and the third outer edge. Common discharge line 141a in first portion
Has a line width of about 4.5 μm, for example,
with a width of about m (= interval between the third and fourth outer edge portions) and directly covering the surface of the P ⁺ type diffusion layer 114,
It extends on the surface of the scribe line area 102. That is, the overlap width between the common discharge line 141a and the scribe line region 102 in the first portion (= the interval between the first and fourth outer edges) is, for example, about 6 μm,
In these portions, the common discharge line 141a and the interlayer insulating film 13
The overlap width (= interval between the inner edge and the third outer edge) of the common discharge line 1 (via the interlayer insulating films 131 and 121) is about 1.5 μm, for example.
There is no overlap between 41a and the field insulating film 208, and the distance between the inner edge and the first outer edge is, for example, about 1.5 μm.

The common discharge line 141a in the second part
Has a line width of, for example, about 8 μm, and has a width of, for example, about 4 μm (= the distance between the third and fourth outer edges), and P ⁺
It extends over the surface of scribe line region 102 with a form directly covering the surface of mold diffusion layer 114. That is, the overlap width between the common discharge line 141a and the scribe line region 102 in the second portion (= the interval between the first and fourth outer edges) is, for example, about 6 μm, and the common discharge line 141a is The overlap width with the film 131 (= interval between the inner edge and the third outer edge) is, for example, about 4 μm.
The overlap width (= interval between the inner edge and the first outer edge) between the common discharge line 141a and the field insulating film 108 in the second portion (via the first portion 21) is, for example, 2 μm.
It is about.

The height of the upper surface of the common discharge line 141a at the inner edge of the first portion is higher than the height of the upper surface of the common discharge line 141a at the inner edge of the second portion.
At least the thickness of the interlayer insulating film 121 (for example, 300 nm
Only the value corresponding to (degree) is low. The reason why the common discharge line 141a extends to the surface (upper surface) of the interlayer insulating film 131 is to ensure the adhesion of the common discharge line 141a to the base. In addition, the common discharge line 141a extends over the entire circumference along the first outer edge, and the scribe line region 102
Is directly connected to the surface of the semiconductor device in order to make the protection elements belonging to each function equally under a sufficiently low contact resistance with respect to ESD at any connection terminal.

The common discharge line 141a and the upper metal wiring 1
The interlayer insulating film 131 including the layers 40, 142, 143 and the like is covered with the third interlayer insulating film. The third interlayer insulating film includes the common discharge line 141a and the upper metal wiring 140,
The (first) silicon oxide film 15 that directly covers the top and side surfaces of the 142 and 143 and covers the surface of the interlayer insulating film 131
1, 152a left on the side surface of the upper wiring 140, etc.,
152b (details will be described later, but in the present embodiment, the SOG film 252A corresponding to the remaining SOG film 252A in the conventional semiconductor device)
No OG film remains) and the SOG film 152a, 1
Cover the silicon oxide film 151 including 52b (second)
It is composed of a laminated film with the silicon oxide film 153. Upper layer metal wiring 140, 142, 143, etc. or common discharge line 141
The film thickness of the silicon oxide film 151 immediately above the upper surface of “a” is, for example, about 200 nm, and the silicon oxide film 151 is directly covered by the silicon oxide film 151 with the interlayer insulating film 131.
The film thickness of 51 is, for example, about 300 nm. The thickness of the silicon oxide film 153 is, for example, about 400 nm. Third
The contact holes 155 reaching the P ⁺ -type diffusion layers 113 and the like, and the contact holes 15 reaching the N ⁺ -type diffusion layers 117 and the N ⁺ -type diffusion layers 118b and the like, respectively.
6 and a contact hole 157 reaching the gate electrode 112, the tungsten silicide wiring 130, or the upper metal wiring 140, respectively.

On the surface of the third interlayer insulating film, connection terminals (bonding pads) 160 and input / output signal connection terminals 160a made of, for example, an aluminum alloy as a second metal material, a ground line 161 and a power supply Line 162
And (second) upper metal wirings 164a, 165 and the like. The line width of the upper metal wiring 164a is, for example, 1
It is about 0 μm. The thickness of the second upper metal wiring is, for example, about 600 nm, and the size of the connection terminal 160, the input / output signal connection terminal 160a, etc. is, for example, 100 μm.
□, and the line width of the ground line 161 and the power line 162 is 1
The distance between the connection terminal 160, the input / output signal connection terminal 160a and the like and the common discharge line 141a is, for example, 9 μm.
It is about 0 μm.

Connection terminal 160, input / output signal connection terminal 16
0a and the like are the upper metal wirings 16 directly connected to them.
4a and the contact hole 156 are connected to the N ⁺ type diffusion layer 118b. A voltage clamp element serving as a first protection element and a protection diode serving as a second protection element are connected in parallel between the connection terminal 160, the input / output signal connection terminal 160a, and the like and the common discharge line 141a. . The voltage clamp element is an N ⁺ type diffusion layer 11
8a and a lateral parasitic NPN transistor including the N ⁺ type diffusion layer 118b, and the protection diode is N ⁺
And a P ⁺ type diffusion layer 115.

An input buffer and an output buffer are connected to the input / output signal connection terminal 160a. The input buffer is composed of CMOS transistors, and the N
The N ⁺ -type diffusion layer 117 and the P ⁺ -type diffusion layer 113 serving as the source of the channel and P-channel MOS transistors are connected to the ground line 161 and the power supply line 162 (for example, via the upper metal wiring 140 and the upper metal wiring 165). , N-channel, P-channel MOS transistor gate electrode 11
2 is connected to the input / output signal connection terminal 160a (for example, via the upper metal wiring 140). The distance between the upper metal wiring 140 (connecting the gate electrode 112 and the input / output signal connection terminal 160a) and the common discharge line 141a is, for example, about 30 μm. N-channel, P-channel MO
An N ⁺ type diffusion layer 117 serving as a drain of the S transistor,
The P ⁺ type diffusion layer 113 is connected to an internal circuit (for example, via a tungsten silicide wiring 130).

The output buffer is a first N-channel MO.
It comprises an S transistor and a load MOS transistor (comprising a second N-channel MOS transistor). One of the N ⁺ type diffusion layer 117 of the source and the drain of the load MOS transistor and the gate electrode 112 are connected to the power supply line 162 (for example, via the upper metal wiring 165). The distance between the upper metal wiring 165 and the common discharge line 141a is
For example, it is about 30 μm. Load MOS source and drain of the other N ⁺ -type diffusion layer 117 of the transistor and the N ⁺ -type diffusion layer 117 serving as the drain of the first N-channel MOS transistor (e.g., via an upper metal wiring 140) input and output signal connection The first N
The gate electrode 112 of the channel MOS transistor is connected to the internal circuit (for example, via the tungsten silicide wiring 130), and the N ⁺ type diffusion layer 117 serving as the source of the first N-channel MOS transistor is connected (for example, via the upper metal layer 1265). ) Is connected to the ground line 161.

Referring to FIG. 4, which is a schematic cross-sectional view of the manufacturing process of the semiconductor device along the line AA in FIG. 1, and FIG. 1, FIG. 2 and FIG. A method for manufacturing a semiconductor device according to the first embodiment will be described (with emphasis on points relating to the SOG film). Note that in FIG. 4 also, the gate oxide film 111 and the SOG
The hatching between the film 152a and the SOG film 152b is omitted.

First, an N-type well 106 is formed in a required region on the surface of a P-type silicon substrate 101. After a pad oxide film (not shown) and a silicon nitride film (not shown) are formed on the entire surface and the silicon nitride film is patterned,
The field insulating film 108 having a thickness of about 250 nm is formed by the selective oxidation method. Thereby, the semiconductor element formation region 103, the active region 104, and the element isolation region 105
Is defined. After removing the silicon nitride film and the pad oxide film, a gate oxide film 111 having a thickness of about 8 nm is formed by thermal oxidation. N ⁺ film thickness of about 100 nm
A polycrystalline silicon film and a tungsten silicide film having a thickness of about 100 nm are formed, and the laminated conductor film is patterned to form a gate electrode 112. Using the gate electrode 112, the field insulating film 108 and the like as a mask, a P-type impurity is introduced, and the P ⁺ -type diffusion layer 1 is formed.
13, 114, 115 and the like are formed. Thereby, the scribe line area 102 is defined. Similarly, introduction of N-type impurities and the like are performed, and N ⁺ -type diffusion layers 117 and 118 are formed.
a, 118b and the like are formed. For example, a silicon oxide film and a BPSG film are formed on the entire surface by a vapor phase growth method or the like.
The BPSG film is reflowed to form an interlayer insulating film 121 made of a silicon oxide based insulating film of about 300 nm.
6 and the like are formed. At this time, the scribe line area 102
An opening is also formed. A tungsten silicide film having a thickness of about 100 nm is formed on the entire surface, and is patterned to form a tungsten silicide wiring 130 (FIGS. 4A, 1, 2, and 3).

Next, a silicon oxide film (not shown in the figure) and a BPSG film (not shown in the figure) are sequentially deposited on the entire surface by a vapor phase growth method, and reflow is performed on the BPSG film. Interlayer insulating film 131 having a thickness of about 400 nm
Is formed. The contact hole 1 is formed in the interlayer insulating film 131.
35, 136, 137 and the like are formed. At this time, an opening is also formed in the scribe line region 102. A tungsten film having a thickness of, for example, about 400 nm is formed on the entire surface (after a titanium film and a titanium nitride film, not shown) are formed, and this is patterned and the upper metal wiring 1 is formed.
40, an upper metal wiring 142, an upper metal wiring 143, a common discharge line 141a, and the like.

Subsequently, a silicon oxide film 151 of, for example, about 300 nm is formed on the entire surface by a vapor deposition method. After that, the SOG film 152 is formed by a spin coating method. Whether the SOG film 152 is organic or inorganic is selected depending on the purpose. Even when the spin coating of the SOG film 152 is performed on the semiconductor devices connected in a wafer state, the common discharge line 141a at the corner of each semiconductor element formation region 103 is formed of the first portion. 152 flows smoothly to the scribe line area 102,
The thickness of the SOG film 152 does not increase as in the case of the SOG film 252 found in the conventional semiconductor device, and the thickness of the SOG film 152 is reduced as a whole (FIG. 4B).

Next, heat treatment is performed to remove the solvent of SOG film 152. Subsequently, the SOG film 152 is etched back by anisotropic etching on the silicon oxide film. Due to this etch-back, most of the upper metal wiring lines 140, 142, 143 and the common discharge line 141a have side surfaces (the width of the hem is extremely narrow).
The SOG film 152a is left. (In the conventional semiconductor device, 252A was easily left.)
The common discharge line 141a and the upper metal wiring 143
Even in the portion having the shape of a square, for example, the common discharge line 141a is located at a portion distant from the corner portion and the common discharge line 141a belongs to the second portion only (in a form having a relatively wide skirt).
The SOG film 152b remains. Further, in this etch-back, the thickness of the spin-coated SOG film 152 is small, so that it is easy to set a shorter etching time. It becomes easier to make the device thinner than before [FIG. 4 (c)].

Subsequently, a silicon oxide film 153 having a thickness of about 400 nm is formed on the entire surface by a vapor phase growth method, and the formation of the third interlayer insulating film is completed. Contact holes 155, 156, 157 and the like penetrating the third interlayer insulating film and the like are formed. In this embodiment, the SOG films 152a, 152
Since only 52b is left, exposure of the SOG film to the side surfaces of the contact holes 155, 156, 157 and the like is avoided. An aluminum alloy film of about 600 nm is formed on the entire surface. This aluminum film is patterned to form a connection terminal 160, an input / output signal connection terminal 160a, a ground line 161, a power supply line 162, upper layer metal wirings 164a and 165, etc. [FIG.
FIG. 1, FIG. 2, FIG. 3]. Although illustration is omitted, a surface protection film is thereafter formed, an opening is provided in the surface protection film, the wafer is diced, and further, the semiconductor device is completed by packaging.

According to the first embodiment, since the inner edge of the common discharge line is provided on the second interlayer insulating film, the adhesion of the common discharge line is not impaired. Further, SOG (constituting a part of the third interlayer insulating film) on the side surface of the contact hole provided in the third interlayer insulating film.
Since exposure of the film is avoided, in the semiconductor device according to the present embodiment, even if an organic SOG film is used, it is easy to suppress an increase in contact resistance at the bottom of the contact hole, and an inorganic SOG film is used. Is adopted (provided on the surface of the third interlayer insulating film), it is possible to avoid corrosion of the second upper metal wiring. Connection terminal (bonding
If this embodiment is applied to a semiconductor device in which a pad) is provided in a semiconductor element formation region near a scribe line region,
This is extremely effective in suppressing the deterioration of the function of the protection element (for ESD) connected to these connection terminals.

Referring to FIG. 5 which is a schematic plan view of a main part of the semiconductor device, a semiconductor device according to an application example of the first embodiment of the first embodiment will be described.

In the first embodiment, the line width (for example, about 4.5 μm) of the first portion of the common discharge line 141a is the second width.
Is smaller than the line width (for example, about 8 μm) of the portion of the common discharge line 141a. When importance is placed on the current density of the common discharge line 141a, the common discharge line 1 shown in FIG.
As in 41aa, the line width of the common discharge line in the first portion may be increased. In the common discharge line 141aa, in the region including the first portion, (the second interlayer insulating film 131
And the third outer edge (the common discharge line 141ab)
Is set to, for example, 7.5 μm (wider than other regions).

Referring to FIG. 6, which is a schematic plan view of the semiconductor device, and FIG. 7, which is a schematic cross-sectional view of the semiconductor device taken along line DD in FIG. 6, a second example of the first embodiment will be described. The semiconductor device according to the first embodiment has the common discharge 14 in the first embodiment.
A common discharge 141b is provided instead of 1a. In addition,
Also in FIG. 7, hatching of the gate oxide film 111 and the SOG film 152a is omitted to avoid complication of the drawing.

The common discharge 141b includes a common discharge 141a.
(The inner edge of the common discharge 141b is provided between the second outer edge and the third outer edge) in the vicinity of the corner of the semiconductor element formation region 103 It is provided in. Further, the common discharge 141b is provided with a third portion between the upper metal wirings 142 and 143 constituting the protection element belonging to the connection terminal 160 provided at a position away from the corner portion. In this portion, similarly to the first portion, the inner edge of the common discharge 141b is provided between the second outer edge and the third outer edge.
The distance between the inner edge and the third outer edge here is, for example, about 0.5 μm.

The common discharge line 1 near the connection terminal 160
Since the third portion is provided in the portion 41b, the upper portion metal wiring 142, the common discharge line 141b, and the upper metal wiring 143 in the vicinity of this portion are left on the side walls of the U-shaped central portion of these wirings. The SOG film becomes the SOG film 152a (unlike the SOG film 152b of the first embodiment). As a result, in the second embodiment, the increase in the contact resistance or the second
It is easy to avoid corrosion of the upper metal wiring.

A semiconductor device according to an application example of the second embodiment of the first embodiment will be described with reference to FIG. 8 which is a schematic plan view of a main part of the semiconductor device.

Also in the second embodiment, the line width (for example, about 4.5 μm) of the first and third portions at the common discharge line 141b is equal to the line width (for example, about 4.5 μm) of the second portion. (About 8 μm). Common discharge line 141
When importance is placed on the current density b, the line width of the common discharge line of the first and third portions may be increased as in the case of the common discharge line 141ba shown in FIG. Common discharge line 14
1ba, in a region including the first and third portions, the third outer edge (of the second interlayer insulating film 131) and the fourth outer edge (of the common discharge line 141ba) Is set to, for example, 7.5 μm (wider than other regions).

Referring to FIG. 9 which is a schematic plan view of the semiconductor device, and FIG. 10 which is a schematic cross-sectional view of the semiconductor device taken along lines AA and EE in FIG. 9, the third embodiment of the present invention will be described. The semiconductor device according to this embodiment is different from the first and second embodiments in that the common discharges 141a and 141b are replaced with a common discharge 14a.
1c. Note that in FIG. 10 also, the gate oxide film 111 and the SOG
The hatching of the film 152a is omitted.

The common discharge 141c, the common discharge 141a,
A first portion is provided similarly to 141b. The range in which the first portion of the common discharge 141c is provided is smaller than the range in which the first portion of the common discharges 141a and 141b is provided. The common discharge line 141c includes
A third portion is provided at the same position as the common discharge line 141b, and a third portion is provided at an arbitrary position. In these third portions (common discharge 141c)
The distance between the inner edge and the third outer edge is, for example, about 0.5 μm.

The third embodiment has the same effect as the second embodiment.

With reference to FIG. 11 which is a schematic plan view of a main part of the semiconductor device, a semiconductor device according to an application example of the third embodiment of the first embodiment will be described.

Also in the third embodiment, the line width (for example, about 4.5 μm) of the first and third portions at the common discharge line 141c is equal to the line width (for example, about 4.5 μm) of the second portion. (About 8 μm). Common discharge line 141
When importance is placed on the current density of c, the line width of the common discharge line of the first and third portions may be increased as in the case of the common discharge line 141ca illustrated in FIG. Common discharge line 1
Also at 41ca, in the region including the first and third portions, the third outer edge (of the second interlayer insulating film 131) and the fourth outer edge (of the common discharge line 141ca) Is set to, for example, 7.5 μm (wider than other regions).

In the first embodiment, the SOI is improved by devising the shape of the outer peripheral wiring composed of the first upper metal wiring.
This solves the problem of the semiconductor device caused by the spin coating of the G film. In the first embodiment, the lower interlayer insulating film serving as a base for the first upper metal wiring has a laminated structure in which, for example, a second interlayer insulating film is laminated on a first interlayer insulating film to form an upper layer. The overlap width of the lower interlayer insulating film forming the scribe line region is made wider than the overlap width of the lower interlayer insulating film forming the lower layer to the scribe line region, and the outer periphery of the shape utilizing the step at the overlap portion is formed. Wiring is provided. That is, by utilizing this, a low-height portion is formed on the upper surface of the inner edge of the outer peripheral wiring.

Note that the first, second and third examples of the first embodiment have the CM on the surface of the P-type silicon substrate.
The present invention relates to a semiconductor device including an OS transistor, in which an element isolation region is formed of a LOCOS type field insulating film and an outer peripheral wiring is formed of a common discharge. However, the first embodiment is not limited to the first, second and third embodiments, but may be an N-type silicon substrate or another semiconductor substrate.
The present invention can also be applied to a semiconductor device composed of an S transistor, a P-channel MOS transistor, a bipolar transistor or a BiCMOS transistor, and has an element isolation region of STI (Shallow Trench Isolation).
The present invention is also applicable to a semiconductor device having a structure.

In the first, second, and third examples of the first embodiment, the connection terminals of the semiconductor element formation region (the length of the semiconductor element formation region) are different from those of the latest DRAM. The present invention can also be applied to a center bonding type semiconductor device provided along a center line (parallel to the edge). It should be noted that the first, second and third embodiments also have specific materials adopted in the detailed description thereof,
The numerical values and the like are not limited to these.

In the second embodiment of the present invention, the (first) outer peripheral wiring formed of the first upper metal wiring and the first upper wiring formed on the surface of the upper interlayer insulating film covering the first upper metal wiring are provided. The technical idea of the first embodiment is applied to a semiconductor device having a second outer peripheral wiring composed of two upper metal wirings.

FIG. 12, which is a schematic plan view of a semiconductor device,
Referring to FIG. 13, which is a schematic cross-sectional view of the semiconductor device along line AA, FF, and GG in FIG. 12, and FIG. 14, which is a schematic cross-sectional view of the semiconductor device along line CC in FIG.
The semiconductor device according to the first example of the second embodiment of the present invention is configured as follows. 13 and 14, hatching between the gate oxide film 111 and the SOG film 152a and the SOG film 152b is omitted to avoid complication of the drawings.

On the surface of P-type silicon substrate 101, scribe line region 102 including (first) P ⁺ type diffusion layer 114 and semiconductor element formation region 103 are provided. The semiconductor element formation region 103 includes an active region 204 and an element isolation region 10 including a field insulating film 108.
5 and is defined by the first outer edge of the field insulating film 108 which is a rectangle. In the semiconductor element formation region 103, a first N-type well 106a,
An N-type well such as the second N-type well 106b is provided.

In the active region on the surface of the N-type well (not shown)
Is a P-channel MOS transistor.⁺ Mold expansion
A scattering layer is provided. P of the semiconductor element formation region 103
Region 10 provided on the surface of a silicon substrate 101
4 includes an N channel MOS transistor.⁺ 
Diffusion layer 117, (second) P constituting a protection element⁺Type
Diffusion layer 115, (first) N constituting protection element⁺ Mold expansion
(Second) N constituting dispersion layer 118a and protection element⁺ 
A mold diffusion layer 118b and the like are provided. N-type well 10
A protection element is formed in the active region 104 provided in 6a.
(Third) P ⁺ Mold diffusion 116a and (third) N⁺ 
A mold diffusion layer 119a is provided. P-type silicon substrate
A region including a boundary with 101 and N-type well 106b
In the active region 104 and the N-type well 106b.
The (fourth) N⁺ Diffusion layer
119b and (fourth) P⁺ Mold diffusion layer 116b
It is provided.

For example, an N-channel MOS transistor includes an N ⁺ type diffusion layer 117, a gate oxide film 111, and a gate electrode 112.

The surface of the semiconductor element forming region 103 including the MOS transistor and the like is covered with a (first) interlayer insulating film 121 having a second outer edge formed of a rectangle. This interlayer insulating film 121 has an appearance of directly covering the surface of the P ⁺ type diffusion layer 114 with an (overlap) width of about 1 μm (= interval between the first and second outer edges), for example. It extends on the surface of the scribe line area 102. The interlayer insulating film 121 is provided with a contact hole 126 and the like reaching the N ⁺ type diffusion layer 117 and the like. On the surface of the interlayer insulating film 121, a tungsten silicide wiring 1
30 are provided. Tungsten silicide wiring 1
Reference numeral 30 denotes an N ⁺ type diffusion layer 1 via a contact hole 126 or the like.
17 and so on.

The surface of the interlayer insulating film 121, including the tungsten silicide wiring 130, is covered with a (second) interlayer insulating film 131 having a third outer edge formed of a rectangle. The insulating film 131 is, for example, 1 μm
Of the order of width (= interval between the second and third outer edges)
^It has a form that directly covers the surface of ⁺ type diffusion layer 114 and extends on the surface of scribe line region 102 (the overlap width between interlayer insulating film 131 and scribe line region 102 (= first and The distance between the third outer edges is, for example, about 2 μm). In the interlayer insulating film 131, a contact hole 135 penetrating through the interlayer insulating film 131 and the interlayer insulating film 121 and reaching the P ⁺ type diffusion layers 115 and 116b and the like.
And a contact hole 136 reaching the N ⁺ type diffusion layers 117, 118 a, 119 a and the like, and a contact hole 137 reaching the gate electrode 112. Further, although not shown, a contact hole penetrating only the interlayer insulating film 131 and reaching the tungsten silicide wiring 130 is provided.

On the surface of the interlayer insulating film 131, a first gold
Tungsten (or aluminum alloy)
Gold) (first) upper metal wirings 140, 142,
143, 144, a rectangular inner edge and a fourth
(First) common wire having outer peripheral edges
An electric wire 141a is provided. Common discharge line 141a
And (not directly connected to) the upper metal wiring 140
Is about 30 μm, for example, and the upper metal wiring
The minimum interval of 140, 142, 143, 144 etc. is, for example,
The upper metal wirings 142, 143,
The line width of 144 is, for example, about 10 μm. Upper layer metal distribution
Line 140 is contact hole 136 or contact hole
137 through N⁺ Type diffusion layer 117 or
Is connected to the gate electrode 112 and the like. Upper metal wiring
142 is N through the contact hole 136⁺ Diffusion layer 1
18a, and further connected to the common discharge line 141a.
Have been. The upper metal wiring 143 is formed in the contact hole 13.
P through 5⁺ Connected to the diffusion layer 115, and
It is connected to the through discharge line 141a. Upper layer metal wiring 14
4 is a contact hole 136 or a contact hole 135
Through N ⁺ Type diffusion layer 119a or P⁺ 
It is connected to the mold diffusion layer 116b.

The common discharge line 141a has a line width of, for example, about 8 μm, and has a width of, for example, about 4 μm (= the interval between the third and fourth outer edges), and the surface of the P ⁺ type diffusion layer 114 is It extends over the surface of the scribe line area 102 with a direct covering appearance. That is, the common discharge line 141a
Of the common discharge line 141a and the interlayer insulating film 131 (= the inner edge of the scribe line region 102) is, for example, about 6 μm. The distance between the edge and the third outer edge is, for example, about 4 μm.
The overlap width (= interval between the inner edge and the first outer edge) between the common discharge line 141a and the field insulating film 108 (via 1 and 121) is, for example, about 2 μm.

The common discharge line 141a and the upper metal wiring 1
The interlayer insulating film 131 including the layers 40, 142, 143, 144 and the like is covered with a third interlayer insulating film. The third interlayer insulating film directly covers the upper surface and side surfaces of the common discharge line 141a and the upper metal wires 140, 142, 143, and 144, and covers the (first) silicon oxide film 151 that covers the surface of the interlayer insulating film 131. (Similar to the first example of the first embodiment), the SOG films 152a and 152b left on the side surfaces of the upper layer wiring 140 and the like, and the SOG film 152
It is composed of a stacked film of the (second) silicon oxide film 153 covering the silicon oxide film 151 including the layer a and the like. In the third interlayer insulating film, a contact hole 155 reaching the P ⁺ type diffusion layer 116a and the like, a contact hole 156 reaching the N ⁺ type diffusion layer 117 or the N ⁺ type diffusion layers 118b and 119b and the like, A contact hole 157 is provided to reach each of 112, tungsten silicide wiring 130, upper metal wirings 140, 144, and the like.

On the surface of the third interlayer insulating film, an input / output signal connection terminal 160a made of a second metal material, for example, an aluminum alloy, and a ground potential (V _SS ) connection terminal 160
b and a connection terminal such as a power supply potential (V _DD ) connection terminal 160b, a ground line 161 and a power supply line 162, and (second)
Common discharge line 163 and (second) upper metal wiring 164
a, 164b, 164c, 165, etc. are provided. Some upper metal wirings 165 are directly connected to the common discharge line 163. The line width of the common discharge line 163 is, for example, about 8 μm, and the upper metal wirings 164a, 164b,.
The line width between 164c and the upper metal wiring 165 directly connected to the common discharge line 163 is, for example, about 10 μm. The common discharge line 163 is provided almost directly above the common discharge line 141a via the third interlayer insulating film. The size of the input / output signal connection terminal 160a and the like is, for example, about 100 μm square, and the line width of the ground line 161 and the power supply line 162 is 10 μm.
As described above, the interval between the input / output signal connection terminal 160a and the like and the common discharge line 141 is, for example, about 90 μm.

In this embodiment, unlike the second conventional semiconductor device, the upper metal wiring 165 directly connected to the common discharge line 163 is connected to the upper metal wiring 144 via the contact hole 157, and furthermore, , Or via a contact hole 136 or a contact hole 135, respectively, to the N ⁺ type diffusion layer 119a or the P ⁺ type diffusion layer 116b. In this embodiment, the upper metal wiring of the same layer adjacent to the upper metal wiring 165 directly connected to the common discharge line 163 is the upper metal wiring 164b or the upper metal wiring 164c.
It is. For this reason, these adjacent distances are sufficiently wide (for example, wider than 10 μm), and are suitable for further miniaturization of the semiconductor device.

Signal connection terminals such as input / output signal connection terminal 160a are connected to upper metal wiring 164 directly connected thereto.
a and the N ⁺ -type diffusion layer 118 b via the contact hole 156. I / O signal connection terminal 1
A voltage clamp element as a first protection element and a first protection diode as a second protection element are connected in parallel between a signal connection terminal such as 60a and the common discharge line 141, respectively. Voltage clamp element is N ⁺ type diffusion layer 1
Consists lateral parasitic NPN transistor comprising 18a and the N ⁺ -type diffusion layer 118b, a first protection diode comprises an N ⁺ -type diffusion layer 118b and the P ⁺ -type diffusion layer 115.

Each ground potential connection terminal 160b is
The upper metal wiring 164b connected to the N ⁺ -type diffusion layer 118b via the upper metal wiring 164a and the contact hole 156 directly connected thereto, and directly connected thereto.
P ⁺ -type diffusion layer 116a through the contact hole 155
It is connected to the. Each ground potential connection terminal 160
b and a common discharge line 141, a voltage clamp element as a first protection element and a first protection diode as a second protection element are connected in parallel, respectively, and further, each ground potential connection terminal 160b A second protection diode, which is a third protection element, is connected between the second protection diode and the common discharge line 163. The second protection diode is N ⁺
And a P ⁺ -type diffusion layer 116a.

Each power supply potential connection terminal 160c is
The upper metal wiring 164c is connected to the N ⁺ -type diffusion layer 118b via the upper metal wiring 164a and the contact hole 156 directly connected to the upper metal wiring 164c.
N ⁺ type diffusion layer 119b through the contact hole 156
It is connected to the. Each power supply potential connection terminal 160
A voltage clamp element serving as a first protection element and a first protection diode serving as a second protection element are connected in parallel between c and the common discharge line 141, respectively. A third protection diode, which is a fourth protection element, is connected to each of the discharge lines 163. The third protection diode includes an N ⁺ -type diffusion layer 119b and a P ⁺ -type diffusion layer 116b (further, a P ⁺ -type diffusion layer 115).

An input buffer and an output buffer are connected to the input / output signal connection terminal 160a. Illustration of the input buffer is omitted. The output buffer comprises a first N-channel MOS transistor and a load MOS transistor (comprising a second N-channel MOS transistor).
N of one of source and drain of load MOS transistor
⁺ Type diffusion layer 117 and gate electrode 112 are connected to power supply line 162 (for example, via upper metal interconnection 140).
The distance between the upper metal wiring 140 and the common discharge line 141 is, for example, about 30 μm. The other N ⁺ type diffusion layer 117 of the source / drain of the load MOS transistor and N serving as the drain of the first N-channel MOS transistor
⁺ Type diffusion layer 117 is connected to input / output signal connection terminal 160a (for example, via upper metal wiring 165), and gate electrode 112 of the first N-channel MOS transistor is connected (for example, via tungsten silicide wiring 130).
An N ⁺ type diffusion layer 117 connected to an internal circuit and serving as a source of a first N-channel MOS transistor is connected to a ground line 161 (for example, via an upper metal wiring 165).

The first example of the second embodiment is as follows.
The third embodiment has the same effects as the first embodiment of the first embodiment. As an application example of the present embodiment, the first
Similarly to the application example of the first embodiment of the present embodiment, the common discharge line 141aa may be used instead of the common discharge line 141a.

As the first common discharge line composed of the first outer peripheral wiring of the second embodiment, the common discharge line 14 of the second example of the first embodiment or the application example thereof is used.
1b or the common discharge line 141ba can be employed.

FIG. 15, which is a schematic plan view of a semiconductor device,
Referring to FIG. 16, which is a schematic cross-sectional view of the semiconductor device taken along the line AA, EE, and GG in FIG. As in the third embodiment, the common discharge line 141c is provided.

The common discharge line 141c and the upper metal interconnection 1 (in the vicinity of the corner of the semiconductor element formation region 103)
40, a portion close to the upper metal wiring 14 (belonging to the protection element of the power supply potential connection terminal 160c, for example, located at a position distant from the corner of the semiconductor element formation region 103).
Similarly, the U-shaped portion formed by the common discharge lines 2 and 143 and the common discharge line 141c is left on the side surface of the first upper-layer metal interconnection, as in the third example of the first embodiment. SO
The G film becomes the SOG film 152a. Therefore, the present embodiment has the same effect as the third embodiment of the first embodiment.

In the first embodiment of the present invention, the first
The object of the present invention has been achieved by devising the shape of the outer peripheral wiring composed of the upper metal wiring. The object of the present invention according to the third embodiment of the present invention is achieved by devising the shape of a lower interlayer insulating film which is a base of the first upper metal wiring.

FIG. 17, which is a schematic plan view of a semiconductor device,
Referring also to FIG. 18, which is a schematic cross-sectional view of the semiconductor device taken along the line AA, DD, and HH in FIG. 17, the semiconductor device according to the first example of the third embodiment of the present invention is as follows. It is configured as follows. In FIG. 17, the silicon nitride film 109a is hatched for easy understanding, and in FIG. 18, the gate oxide film 111 and the SOG film 152 are shown in FIG.
a and the hatching of the SOG film 152b are omitted.

On the surface of a P-type silicon substrate 101, a scribe line region 102 including a (first) P ⁺ -type diffusion layer 114 and a semiconductor element formation region 103 are provided. The semiconductor element formation region 103 includes an element isolation region 10 including an active region 104 and a field insulating film 108.
5 and is defined by the first outer edge of the field insulating film 108 which is a rectangle. The depth of the diffusion layer of the P ⁺ type diffusion layer 114 is, for example, about 250 nm, and a half of the line width of the scribe line region 102 (belonging to one semiconductor element formation region 103) is, for example, 50 μm.
It is about. The field insulating film 108 is formed by, for example, selective oxidation and has a thickness of, for example, about 250 nm. An N-type well such as an N-type well 106 is provided in the semiconductor element formation region 103. N-type well 1
Reference numeral 06 denotes a P-channel MOS transistor (constituting a CMOS transistor), which has a junction depth of, for example, about 1 to 2 μm.

The surface of the field insulating film 108 near the corner of the semiconductor element formation region 103 is directly covered with the (first) silicon nitride film 109a. This silicon nitride film 109a extends over the surface of scribe line region 102 via pad oxide film 107. The thickness of the pad oxide film 107 is, for example, about 5 nm, and the thickness of the silicon nitride film 109a is, for example, about 20 nm. Field oxide film 108, scribe line region 102
Silicon nitride film 109 for (P ⁺ type diffusion layer 114)
The overlap width of “a” is, for example, 5.5 μm,
It is about 0.5 μm.

In the active region on the surface of the N-type well 106,
P constituting a P-channel MOS transistor⁺ Diffusion layer
113 and the like are provided. Semiconductor element formation region 103
Active region provided on the surface of P-type silicon substrate 101
An N-channel MOS transistor 104 is formed.
N⁺ Diffusion layer 117, (second) P constituting a protection element
⁺ Type diffusion layer 115, (first) N constituting a protection element⁺ 
Forming the diffusion layer 118a and the protection element (second)
N⁺ A mold diffusion layer 118b and the like are provided. P ⁺ Mold diffusion
The depth of the diffusion layer of the layer 115 is, for example, about 0.25 μm.
, P⁺ The junction depth of the mold diffusion layer 113 is, for example, 0.25.
μm, and N⁺ Type diffusion layers 117, 118a, 11
The depth of the junction 8b is, for example, about 0.2 μm.

The P channel MOS transistor has a P ⁺ type diffusion layer 113, a gate oxide film 111 and a gate electrode 11.
2 and the N-channel MOS transistor is N
It is composed of a ⁺ type diffusion layer 117, a gate oxide film 111 and a gate electrode 112. The thickness of the gate oxide film 111 is, for example, about 8 nm. The gate electrode 112
For example, it has a tungsten polycide structure in which a tungsten silicide (WSi ₂ ) film having a thickness of about 100 nm is laminated on an N ⁺ type polycrystalline silicon film (not shown in the drawing) having a thickness of 100 nm. The gate lengths of the N-channel and P-channel MOS transistors are, for example, about 0.4 μm and 0.5 μm.

The surface of the semiconductor element forming region 103 including the MOS transistor and the like is covered with a (first) interlayer insulating film 122 having a second outer edge. The interlayer insulating film 122 is preferably made of only a silicon oxide-based insulating film, and has a thickness of, for example, about 300 nm. For example, the interlayer insulating film 122 is formed by laminating a BPSG film reflowed on a silicon oxide film. The portion of the interlayer insulating film 122 other than on the surface of the silicon nitride film 109a has an overlap width of, for example, about 1 μm (= the interval between the first and second outer edges) and the surface of the P ⁺ type diffusion layer 114. With a form that directly covers
It extends on the surface of the scribe line area 102.

The interlayer insulating film 122 in the portion where the silicon nitride film 109a exists covers the surface of the silicon nitride film 109a with an overlap width of about 1 μm, for example. In the portion where the silicon nitride film 109a exists, there is a portion of the field insulating film 108 that is not covered by the interlayer insulating film 122. Part of field insulating film 1
The width of 08 is, for example, about 4.5 μm (= the distance between the second outer edge and the first outer edge in this portion).

The interlayer insulating film 122 includes (this interlayer insulating film 1
22), contact holes 125, 126 and the like reaching the P ⁺ type diffusion layer 113, the N ⁺ type diffusion layer 117 and the like are provided. On the surface of the interlayer insulating film 122, for example, 1
A tungsten silicide wiring 130 (a lower wiring) having a thickness of about 00 nm is provided. The tungsten silicide wiring 130 is connected to the P ⁺ type diffusion layer 113 and N ⁺ through contact holes 125 and 126, respectively.
It is connected to the mold diffusion layer 117 and the like.

Including tungsten silicide wiring 130
The surface of the interlayer insulating film 122 has a third outer edge.
(The second) interlayer insulating film 132.
The interlayer insulating film 132 is formed only of a silicon oxide based insulating film.
It preferably has a thickness of, for example, about 400 nm,
BPSG film reflowed on silicon oxide film is laminated
The structure. Except on the surface of the silicon nitride film 109a
The width of the interlayer insulating film 132 at the portion where
(= Spacing between the second and third outer edges) ⁺ Mold diffusion
Scribes directly over the surface of layer 114,
Extending on the surface of the line region 102 (interlayer insulating film 13
2 and the scribe line area 102 overlap width (=
The distance between the first and third outer edges is, for example, about 2 μm.
Degrees).

The interlayer insulating film 132 has a width of about 1 μm, for example, and directly covers the surface of the silicon nitride film 109a. The overlap width between the interlayer insulating film 132 and the silicon nitride film 109a is, for example, about 2 μm. In the portion where the silicon nitride film 109a exists, the interlayer insulating film 1
There is a portion of the field insulating film 108 that is not covered by 32. The width of the field insulating film 108 in a portion not covered by the interlayer insulating film 132 is, for example, about 3.5 μm (= the distance between the third outer edge and the first outer edge in this portion). is there.

As the interlayer insulating film 132, the interlayer insulating film 132
And the N ⁺ type diffusion layer 11 penetrating through the interlayer insulating film 122.
A contact hole 136 reaching 7, 118a, etc., a contact hole 137 reaching the gate electrode 112, and a contact hole (not shown) reaching the P ⁺ type diffusion layer 113 are provided. Although not shown, the interlayer insulating film 1 is not shown.
Tungsten silicide wiring 130 penetrating only 32
Is provided.

On the surface of the interlayer insulating film 132, (first) upper metal wirings 140, 142 made of tungsten (or aluminum alloy) as a first metal material are formed.
143 and a fourth inner rectangular edge and a fourth rectangular shape.
And a common discharge line 141 (which is an outer peripheral wiring). At this time, although not shown, a barrier film formed by laminating a titanium nitride (TiN) film on a tinta (Ti) film is provided at the bottom of the upper metal wiring. Common discharge line 141 and upper metal wiring 140,1
Reference numerals 42 and 143 are made of, for example, a tungsten film having a thickness of about 400 nm (or an aluminum alloy film having a thickness of, for example, about 600 nm). The minimum distance between the common discharge line 141 and the upper metal wiring 140 (not directly connected thereto) is, for example, about 30 μm.
The minimum spacing between the upper metal wirings 142 and 143 is, for example, about 0.5 μm, and the line width of the upper metal wirings 142 and 143 is, for example, 10 μm.
It is about μm. The upper metal wiring 140 is connected to the N ⁺ -type diffusion layer 117, the gate electrode 112, and the like via the contact hole 136, the contact hole 137, and the like, respectively. The upper metal wiring 142 is formed in the contact hole 1
It is connected to the N ⁺ -type diffusion layer 118 a through the common discharge line 141. The upper metal wiring 143 is connected to the P ⁺ type diffusion layer 1 through the contact hole 135.
15 and further to the common discharge line 141.

The line width of the common discharge line 141 (= the distance between the fourth outer edge and the inner edge) is, for example, about 8 μm. The common discharge line 141 in the portion where the silicon nitride film 109a is not provided has a width of about 4 μm (= the interval between the third and fourth outer edges) and directly covers the surface of the P ⁺ type diffusion layer 114. And extends on the surface of the scribe line region 102. The overlap width between the common discharge line 141 and the scribe line region 102 (= the distance between the first and fourth outer edge portions) in this portion is, for example, about 6 μm, and the overlap width between the common discharge line 141 and the interlayer insulating film 132 is approximately 6 μm. The overlap width (= interval between the inner edge and the third outer edge) is, for example, about 4 μm, and the overlap width (via the interlayer insulating films 132 and 122) between the common discharge line 141 and the field insulating film 108 is set. The overlap width (= interval between the inner edge and the first outer edge) is, for example, about 2 μm.

In the portion where the silicon nitride film 109a exists, the common discharge line 141 directly covers the surface of the silicon nitride film 109a with an overlap width of about 2.5 μm, for example. The common discharge line 14 is formed on the silicon nitride film 109a.
For example, there is a portion that is not covered by either 1 or the interlayer insulating film 132 at 1.5 μm (= interval between the inner edge and the third outer edge at this portion).

The height of the upper surface at the inner edge of the common discharge line 141 where the silicon nitride film 109a exists is:
Common discharge line 14 in a portion without silicon nitride film 109a
1 compared to the height of the upper surface at the inner edge of the semiconductor device 1 at least by a value corresponding to “the thickness of the interlayer insulating film 122” + “the thickness of the interlayer insulating film 132” − “the thickness of the silicon nitride film 109a”. Is low. Since the common discharge line 141 extends to the surface of the interlayer insulating film 132 and the surface of the silicon nitride film 109a, the adhesion of the common discharge line 141 to the base is also ensured. In addition, the common discharge line 141 extends over the entire circumference along the first outer edge, and the scribe line region 102
Is directly connected to the surface of the semiconductor device in order to make the protection elements belonging to each function equally under a sufficiently low contact resistance with respect to ESD at any connection terminal.

The common discharge line 141 and the upper metal wiring 14
The interlayer insulating film 131 including the layers 0, 142, 143 and the like is covered with a third interlayer insulating film. The third interlayer insulating film includes a common discharge line 141 and upper metal wires 140 and 14.
2,143 directly cover the upper surface and side surfaces, and cover the surface of the interlayer insulating film 131 (first) silicon oxide film 151.
And 152a, 1 left on the side surface of the upper wiring 140 and the like.
52b (details will be described later, but in this embodiment, the SOG corresponding to the SOG film 252A remaining in the conventional semiconductor device is used.
G film does not remain).
It is composed of a laminated film with the (second) silicon oxide film 153 covering the silicon oxide film 151 including 2b. The thickness of the silicon oxide film 151 just above the upper metal wirings 140, 142, 143, etc. or the upper surface of the common discharge line 141 is, for example, 20.
0 nm, and the silicon oxide film 151 is directly covered with the interlayer insulating film 131 by the silicon oxide film 151.
Is, for example, about 300 nm. The thickness of the silicon oxide film 153 is, for example, about 400 nm. In the third interlayer insulating film, a contact hole 155 reaching the P ⁺ -type diffusion layer 113 and the like, and a contact hole 156 reaching the N ⁺ -type diffusion layer 117 and the N ⁺ -type diffusion layer 118b and the like, respectively.
, Gate electrode 112, tungsten silicide wiring 1
A contact hole 157 that reaches each of the upper metal wiring 30 and the upper metal wiring 30 is provided.

On the surface of the third interlayer insulating film, connection terminals (bonding pads) 160 and input / output signal connection terminals 160a made of, for example, an aluminum alloy as a second metal material, a ground line 161 and a power supply Line 162
And (second) upper metal wirings 164a, 165 and the like. The line width of the upper metal wiring 164a is, for example, 1
It is about 0 μm. The thickness of the second upper metal wiring is, for example, about 600 nm, and the size of the connection terminal 160, the input / output signal connection terminal 160a, etc. is, for example, 100 μm.
□, and the line width of the ground line 161 and the power line 162 is 1
The distance between the connection terminal 160, the input / output signal connection terminal 160a, etc. and the common discharge line 141 is, for example, 90 μm.
It is about μm.

Connection terminal 160, input / output signal connection terminal 16
0a and the like are the upper metal wirings 16 directly connected to them.
4a and the contact hole 156 are connected to the N ⁺ type diffusion layer 118b. A voltage clamp element as a first protection element and a protection diode as a second protection element are connected in parallel between the connection terminal 160, the input / output signal connection terminal 160a and the like and the common discharge line 141, respectively. . The voltage clamp element is an N ⁺ type diffusion layer 118
The protection diode includes an N ⁺ -type diffusion layer 118b and a P ⁺ -type diffusion layer 115. The protection diode includes a lateral parasitic NPN transistor including a and an N ⁺ -type diffusion layer 118b.

An input buffer and an output buffer are connected to the input / output signal connection terminal 160a. The input buffer is composed of CMOS transistors, and the N
The N ⁺ -type diffusion layer 117 and the P ⁺ -type diffusion layer 113 serving as the source of the channel and P-channel MOS transistors are connected to the ground line 161 and the power supply line 162 (for example, via the upper metal wiring 140 and the upper metal wiring 165). , N-channel, P-channel MOS transistor gate electrode 11
2 is connected to the input / output signal connection terminal 160a (for example, via the upper metal wiring 140). The distance between the upper metal wiring 140 (connecting the gate electrode 112 and the input / output signal connection terminal 160a) and the common discharge line 141 is, for example, about 30 μm. N-channel, P-channel MOS
N ⁺ type diffusion layer 117 serving as the drain of the transistor, P
⁺ Type diffusion layer 113 is connected to an internal circuit (for example, via tungsten silicide wiring 130).

The output buffer is a first N-channel MO.
It comprises an S transistor and a load MOS transistor (comprising a second N-channel MOS transistor). One of the N ⁺ type diffusion layer 117 of the source and the drain of the load MOS transistor and the gate electrode 112 are connected to the power supply line 162 (for example, via the upper metal wiring 165). The distance between the upper metal wiring 165 and the common discharge line 141 is, for example, about 30 μm. The other N ⁺ type diffusion layer 117 of the source / drain of the load MOS transistor and the first N
The N ⁺ type diffusion layer 117 serving as the drain of the channel MOS transistor is provided (for example, via the upper metal wiring 140).
The gate electrode 112 of the first N-channel MOS transistor is connected to the internal circuit (for example, via the tungsten silicide wiring 130), and is connected to the input / output signal connection terminal 160a, and becomes the source of the first N-channel MOS transistor. ⁺ Type diffusion layer 117 (for example, upper metal layer 1
265) (via H.265).

Referring to FIG. 19, which is a schematic cross-sectional view of the manufacturing process of the semiconductor device along the line HH in FIG. 17, and FIGS. 17 and 18, the first embodiment of the third embodiment will be described. A method for manufacturing a semiconductor device according to an embodiment will be described.

First, an N-type well 106 is formed in a required region on the surface of a P-type silicon substrate 101. A pad oxide film 107 having a thickness of, for example, about 5 nm is formed on the entire surface by thermal oxidation. Further, a silicon nitride film (not shown) is formed on the entire surface by a vapor phase growth method, and after the silicon nitride film is patterned, the silicon nitride film is subjected to, for example, 250
A field insulating film 108 having a thickness of about nm is formed. As a result, the semiconductor element formation region 103, the active region 104, and the element isolation region 105 are defined. After the removal of the silicon nitride film, a silicon nitride film (not shown in the drawing) of, for example, about 20 nm is formed on the entire surface again by the vapor phase growth method. This silicon nitride film is patterned by using the photoresist film pattern 171 as a mask, and the (first) silicon nitride film 109a is formed remaining (FIG. 19A).

Next, the photoresist film pattern 171 is removed. After the pad oxide film 107 is removed using the silicon nitride film 109a as a mask, 8 nm is formed by thermal oxidation.
A gate oxide film 111 having a thickness of about the same is formed. An N ⁺ -type polycrystalline silicon film having a thickness of about 100 nm and a thickness of 1
A tungsten silicide film of about 00 nm is formed, and the laminated conductor film is patterned to form a gate electrode 112. Using the gate electrode 112, the field insulating film 108, and the like as a mask, a P-type impurity is introduced to form P ⁺ -type diffusion layers 113, 114, 115, and the like. Thereby, the scribe line area 102 is defined. Similarly, introduction of N-type impurities and the like are performed, and N ⁺
Formed diffusion layers 117, 118a, 118b, etc. are formed [FIG. 19 (b), FIG. 17, FIG. 18].

For example, a silicon oxide film and a BPSG film are formed on the entire surface by a vapor phase growth method or the like, and the BPSG film is reflowed. The photoresist film pattern 172 is used as a mask for the stacked silicon oxide-based insulating film, for example, octafluorocyclobutane (C ₄ F).
₈ ) and anisotropic etching (the silicon oxide is etched with high selectivity to silicon and silicon nitride) using carbon monoxide (CO),
An interlayer insulating film 122 made of a silicon oxide based insulating film having a thickness of about 300 nm is formed.
19, contact holes 125 and 126 are formed, and an opening is also formed in the scribe line region 102 [FIG.
(C), FIGS. 17 and 18].

Next, a tungsten silicide film having a thickness of about 100 nm is formed on the entire surface, and is patterned to form a tungsten silicide wiring 130. A silicon oxide film (not shown in the figure) and a BPSG film (not shown in the figure) are sequentially deposited on the entire surface by a vapor phase growth method, and reflow is performed on the BPSG film. The laminated silicon oxide insulating film is subjected to the same anisotropic etching using the photoresist film pattern 173 as a mask to form an interlayer insulating film 132 having a thickness of about 400 nm. Interlayer insulating film 132
Contact holes 135, 136, 137 and the like are formed. At this time, an opening is also formed in the scribe line region 102 [FIG. 19D, FIG. 17, FIG. 18].

Thereafter, a tungsten film having a thickness of, for example, about 400 nm is formed on the entire surface (after a titanium film and a titanium nitride film, not shown) are formed, and the tungsten film is patterned, and the upper metal wiring 140 and the upper metal are formed. Wiring 14
2, upper metal wiring 143, common discharge line 141, and the like are formed. Subsequently, a silicon oxide film 151 of, for example, about 300 nm is formed on the entire surface by a vapor deposition method. Thereafter, an SOG film (not shown in the figure) is formed by a spin coating method. Whether the SOG film is organic or inorganic is selected depending on the purpose. This SO
Even if the spin coating of the G film is performed on the semiconductor devices connected in a wafer state, since the common discharge lines 141 at the corners of the respective semiconductor element forming regions 103 have the above-described structure, the SOG film is scribed. The flow into the line region 102 is performed smoothly, and the thickness of the SOG film is not as large as that of the SOG film 252 as seen in the conventional semiconductor device. .

Next, a heat treatment is performed to remove the solvent of the SOG film. Subsequently, the SOG film is etched back by anisotropic etching on the silicon oxide film. By this etch back, the upper metal wiring 14
0, 142, 143 and most of the side surfaces of the common discharge line 141 have SOG (having an extremely narrow width).
The film 152a is left. (In a conventional semiconductor device, 25
The upper metal wiring 142, the common discharge line 141, and the upper metal wiring 143 are also formed in a U-shape, for example, at a portion away from the corner, and the common discharge line 141 is The SOG film 1 (having a relatively wide tail) is formed only in the region belonging to the second portion.
52b remains. In addition, in this etch back, the thickness of the spin-coated SOG film is small, so that it is easy to set a shorter etching time. It becomes easier to make it thinner.

Subsequently, a silicon oxide film 153 having a thickness of about 400 nm is formed on the entire surface by a vapor phase growth method, and the formation of the third interlayer insulating film is completed. Contact holes 155, 156, 157 and the like penetrating the third interlayer insulating film and the like are formed. In this embodiment, the SOG films 152a, 152
Since only 52b is left, exposure of the SOG film to the side surfaces of the contact holes 155, 156, 157 and the like is avoided. An aluminum alloy film of about 600 nm is formed on the entire surface. This aluminum film is patterned to form a connection terminal 160, an input / output signal connection terminal 160a, a ground line 161, a power supply line 162, upper metal wires 164a and 165, etc. [FIGS.
8]. Although illustration is omitted, a surface protection film is thereafter formed, an opening is provided in the surface protection film, the wafer is diced, and further, the semiconductor device is completed by packaging.

According to the first example of the third embodiment, the inner edge of the common discharge line is provided on the second interlayer insulating film or the (first) silicon nitride film. Therefore, the adhesion of the common discharge line is not impaired.
Further, S (which constitutes a part of the third interlayer insulating film) on the side surface of the contact hole provided in the third interlayer insulating film.
Since the exposure of the OG film is avoided, in the semiconductor device according to the present embodiment, even if an organic SOG film is used, it is easy to suppress an increase in the contact resistance at the bottom of the contact hole, and the inorganic SOG film is used. Even when a film is employed, it is possible to avoid corrosion of the second upper metal wiring (provided on the surface of the third interlayer insulating film). If this embodiment is applied to a semiconductor device in which connection terminals (bonding pads) are provided in a semiconductor element formation region near a scribe line region, these connection terminals are connected (for ESD).
This is extremely effective in suppressing a decrease in the function of the protection element.

FIG. 20, which is a schematic plan view of a semiconductor device,
FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line DD in FIG.
1, the semiconductor device according to the second example of the third embodiment differs from the first example of the third embodiment in that the second silicon nitride film 109b And the interlayer insulating film 12 is replaced with the interlayer insulating film 12
3,133 are provided. It should be noted that FIG. 20 also shows silicon nitride films 109a and 109b for easy understanding.
21 is hatched, and in FIG. 21 (gate oxide film 111 and) SOG to avoid complication of the drawing.
The hatching of the film 152a is omitted.

The silicon nitride film 109b is connected to the connection terminal 16
0, upper metal wirings 142, 1 constituting protection elements belonging to respective connection terminals such as input / output signal connection terminal 160a.
It is provided at a position corresponding to a “U” -shaped portion formed by 43 and the common discharge line 141. These silicon nitride films 109b also extend over the surface of scribe line region 102 via pad oxide film 107, and form field oxide film 10b.
8. The overlap width of the silicon nitride film 109b with respect to the scribe line region 102 (P ⁺ type diffusion layer 114) is, for example, about 5.5 μm and 0.5 μm, respectively.

The positional relationship between the interlayer insulating film 123 and the interlayer insulating film 133 with respect to the silicon nitride films 109a and 109b is the same as that of the first embodiment in the third embodiment.
This is the same as the positional relationship between the interlayer insulating film 122 and the interlayer insulating film 132 with respect to the silicon nitride film 109a in the embodiment. The positional relationship of the common discharge line 141 with respect to the silicon nitride film 109b is the same as the positional relationship of the common discharge line 141 with respect to the silicon nitride film 109a. Therefore, the upper metal wiring 14 in the silicon nitride film 109b is formed.
2 and 143 and the common discharge line 141, the SOG film (not the SOG film 152 b) remaining on the side surface of the first upper metal wiring in these portions is formed. 152a.

The second embodiment has the same effects as the second embodiment of the first embodiment. In addition,
The position where the second silicon nitride film 109b is provided is not limited to the above position, and the semiconductor element formation region 10
The position may be any position away from the corner portion of No. 3.

In the third embodiment, a first silicon nitride film or the like is provided on a field insulating film at a corner of a semiconductor element forming region, and a lower interlayer insulating film serving as a base for a first upper metal wiring is provided. By devising the shape of the film, SO
This solves the problem of the semiconductor device caused by the spin coating of the G film.

The first and second examples of the third embodiment relate to a semiconductor device comprising a CMOS transistor on the surface of a P-type silicon substrate, and the element isolation region has a LOCOS type field insulation. This is because the outer peripheral wiring is made of a common discharge. However, the second embodiment is not limited to the first and second embodiments, but may be an N-type silicon substrate or another semiconductor substrate, and may be an N-channel MOS transistor, a P-channel MOS transistor, a bipolar transistor, or the like. The present invention can be applied to a semiconductor device composed of a transistor or a BiCMOS transistor.
The present invention is also applicable to a semiconductor device having a (shallow trench isolation) structure.

Further, in the first and second examples of the third embodiment, the connection terminal is formed in the semiconductor element formation region (the longitudinal edge of the semiconductor element formation region) as in the latest DRAM. Center located along the center line
The present invention can also be applied to a bonding type semiconductor device. It should be noted that also in the first and second embodiments, specific materials used in the detailed description thereof except that the first and second interlayer insulating films are made of a silicon oxide based insulating film. , Numerical values, etc. are not limited to these.

In the fourth embodiment of the present invention, the (first) outer peripheral wiring composed of the first upper metal wiring and the first upper wiring formed on the surface of the upper interlayer insulating film covering the first upper metal wiring are provided. This is an application of the technical concept of the third embodiment described above to a semiconductor device having a second outer peripheral wiring composed of two upper metal wirings.

FIG. 22, which is a schematic plan view of a semiconductor device,
Referring to FIG. 23 which is a schematic cross-sectional view of the semiconductor device taken along the line AA, GG and HH in FIG. 22, the semiconductor device according to the first example of the fourth embodiment of the present invention is as follows. It is configured as follows. In FIG. 22, the silicon nitride film 109a is hatched for easy understanding, and the gate oxide film 111 and the SOG film 152a are also hatched in FIG.
And the hatching of the SOG film 152b is omitted.

On the surface of P-type silicon substrate 101, scribe line region 102 including (first) P ⁺ -type diffusion layer 114 and semiconductor element formation region 103 are provided. The semiconductor element formation region 103 includes an active region 204 and an element isolation region 10 including a field insulating film 108.
5 and is defined by the first outer edge of the field insulating film 108 which is a rectangle. In the semiconductor element formation region 103, a first N-type well 106a,
An N-type well such as the second N-type well 106b is provided.

In the active region on the surface of the N-type well (not shown)
Is a P-channel MOS transistor.⁺ Mold expansion
A scattering layer is provided. P of the semiconductor element formation region 103
Region 10 provided on the surface of a silicon substrate 101
4 includes an N channel MOS transistor.⁺ 
Diffusion layer 117, (second) P constituting a protection element⁺Type
Diffusion layer 115, (first) N constituting protection element⁺ Mold expansion
(Second) N constituting dispersion layer 118a and protection element⁺ 
A mold diffusion layer 118b and the like are provided. N-type well 10
A protection element is formed in the active region 104 provided in 6a.
(Third) P ⁺ Mold diffusion 116a and (third) N⁺ 
A mold diffusion layer 119a is provided. P-type silicon substrate
A region including a boundary with 101 and N-type well 106b
In the active region 104 and the N-type well 106b.
The (fourth) N⁺ Diffusion layer
119b and (fourth) P⁺ Mold diffusion layer 116b
It is provided.

The surface of field insulating film 108 near the corner of semiconductor element forming region 103 is directly covered with (first) silicon nitride film 109a. This silicon nitride film 109a extends over the surface of scribe line region 102 via pad oxide film 107. The thickness of the pad oxide film 107 is, for example, about 5 nm, and the thickness of the silicon nitride film 109a is, for example, about 20 nm. Field oxide film 108, scribe line region 102
Silicon nitride film 109 for (P ⁺ type diffusion layer 114)
The overlap width of “a” is, for example, 5.5 μm,
It is about 0.5 μm.

For example, an N-channel MOS transistor includes an N ⁺ type diffusion layer 117, a gate oxide film 111, and a gate electrode 112.

The surface of the semiconductor element formation region 103 including the MOS transistor and the like is covered with a (first) interlayer insulating film 122 having a second outer edge. The interlayer insulating film 122 is preferably made of only a silicon oxide-based insulating film, and has a thickness of, for example, about 300 nm. For example, the interlayer insulating film 122 is formed by laminating a BPSG film reflowed on a silicon oxide film. The portion of the interlayer insulating film 122 other than on the surface of the silicon nitride film 109a has an overlap width of, for example, about 1 μm (= the interval between the first and second outer edges) and the surface of the P ⁺ type diffusion layer 114. With a form that directly covers
It extends on the surface of the scribe line area 102.

The interlayer insulating film 122 in the portion where the silicon nitride film 109a exists covers the surface of the silicon nitride film 109a with an overlap width of about 1 μm, for example. In the portion where the silicon nitride film 109a exists, there is a portion of the field insulating film 108 that is not covered by the interlayer insulating film 122. The width of the field insulating film 108 in this portion is, for example, about 4.5 μm (= the distance between the second outer edge portion and the first outer edge portion in this portion).
It is.

The surface of the semiconductor element forming region 103 including the MOS transistor and the like is covered with a (first) interlayer insulating film 122 having a second outer edge. The interlayer insulating film 122 is preferably made of only a silicon oxide-based insulating film, and has a thickness of, for example, about 300 nm. For example, the interlayer insulating film 122 is formed by laminating a BPSG film reflowed on a silicon oxide film. The portion of the interlayer insulating film 122 other than on the surface of the silicon nitride film 109a has an overlap width of, for example, about 1 μm (= the interval between the first and second outer edges) and the surface of the P ⁺ type diffusion layer 114. With a form that directly covers
It extends on the surface of the scribe line area 102.

The interlayer insulating film 122 in the portion where the silicon nitride film 109a exists covers the surface of the silicon nitride film 109a with an overlap width of about 1 μm, for example. In the portion where the silicon nitride film 109a exists, there is a portion of the field insulating film 108 that is not covered by the interlayer insulating film 122. Part of field insulating film 1
The width of 08 is, for example, about 4.5 μm (= the distance between the second outer edge and the first outer edge in this portion).

The N ⁺ type diffusion layer 117 is formed in the interlayer insulating film 122.
And the like are provided. On the surface of the interlayer insulating film 122, a tungsten silicide wiring 130 is provided. The tungsten silicide wiring 130 is connected to the N ⁺ type diffusion layer 117 and the like via the contact hole 126 and the like.

Including tungsten silicide wiring 130
The surface of the interlayer insulating film 122 has a third outer edge.
(The second) interlayer insulating film 132.
The interlayer insulating film 132 is formed only of a silicon oxide based insulating film.
It preferably has a thickness of, for example, about 400 nm,
BPSG film reflowed on silicon oxide film is laminated
The structure. Except on the surface of the silicon nitride film 109a
The width of the interlayer insulating film 132 at the portion where
(= Spacing between the second and third outer edges) ⁺ Mold diffusion
Scribes directly over the surface of layer 114,
Extending on the surface of the line region 102 (interlayer insulating film 13
2 and the scribe line area 102 overlap width (=
The distance between the first and third outer edges is, for example, about 2 μm.
Degrees).

The interlayer insulating film 132 has a width of about 1 μm, for example, and directly covers the surface of the silicon nitride film 109a. The overlap width between the interlayer insulating film 132 and the silicon nitride film 109a is, for example, about 2 μm. In the portion where the silicon nitride film 109a exists, the interlayer insulating film 1
There is a portion of the field insulating film 108 that is not covered by 32. The width of the field insulating film 108 in a portion not covered by the interlayer insulating film 132 is, for example, about 3.5 μm (= the distance between the third outer edge and the first outer edge in this portion). is there.

As the interlayer insulating film 132, the interlayer insulating film 132
And the P ⁺ type diffusion layer 11 penetrating through the interlayer insulating film 123.
A contact hole 135 reaching 5, 116b, etc., a contact hole 136 reaching N ⁺ type diffusion layers 117, 118a, 119a, etc., and a contact hole 137 reaching the gate electrode 112 are provided. Further, although not shown, a contact hole penetrating only the interlayer insulating film 132 and reaching the tungsten silicide wiring 130 is provided.

On the surface of the interlayer insulating film 132, (first) upper metal wirings 140, 142 made of tungsten (or aluminum alloy) as a first metal material are provided.
143, 144, a rectangular inner edge and a fourth
And a (first) common discharge line 141, which is an outer peripheral wiring having an outer edge portion of the above. The minimum distance between the common discharge line 141 and the upper metal wiring 140 (not directly connected thereto) is, for example, about 30 μm.
The minimum distance between the upper metal wirings 142, 143, 144 is, for example, about 0.5 μm.
The line width of 144 is, for example, about 10 μm. The upper metal wiring 140 is connected to the N ⁺ -type diffusion layer 117, the gate electrode 112, and the like via the contact hole 136, the contact hole 137, and the like, respectively. The upper metal wiring 142 is connected to the N ⁺ type diffusion layer 1 through the contact hole 136.
18a, and further connected to a common discharge line 141. The upper metal wiring 143 is provided in the contact hole 135.
Are connected to the P ⁺ -type diffusion layer 115 via the common discharge line 141. Upper layer metal wiring 144
Is connected to the N ⁺ -type diffusion layer 119a or the P ⁺ -type diffusion layer 116b through the contact hole 136 or the contact hole 135, respectively.

The width of the common discharge line 141 (= the distance between the fourth outer edge and the inner edge) is, for example, about 8 μm. The common discharge line 141 in the portion where the silicon nitride film 109a is not provided has a width of about 4 μm (= the interval between the third and fourth outer edges) and directly covers the surface of the P ⁺ type diffusion layer 114. And extends on the surface of the scribe line region 102. The overlap width between the common discharge line 141 and the scribe line region 102 (= the distance between the first and fourth outer edge portions) in this portion is, for example, about 6 μm, and the overlap width between the common discharge line 141 and the interlayer insulating film 132 is approximately 6 μm. The overlap width (= interval between the inner edge and the third outer edge) is, for example, about 4 μm, and the overlap width (via the interlayer insulating films 132 and 122) between the common discharge line 141 and the field insulating film 108 is set. The overlap width (= interval between the inner edge and the first outer edge) is, for example, about 2 μm.

In the portion where the silicon nitride film 109a exists, the common discharge line 141 directly covers the surface of the silicon nitride film 109a with an overlap width of about 2.5 μm, for example. The common discharge line 14 is formed on the silicon nitride film 109a.
For example, there is a portion that is not covered by either 1 or the interlayer insulating film 132 at 1.5 μm (= interval between the inner edge and the third outer edge at this portion).

The height of the upper surface at the inner edge of the common discharge line 141 where the silicon nitride film 109a exists is:
Common discharge line 14 in a portion without silicon nitride film 109a
1 compared to the height of the upper surface at the inner edge of the semiconductor device 1 at least by a value corresponding to “the thickness of the interlayer insulating film 122” + “the thickness of the interlayer insulating film 132” − “the thickness of the silicon nitride film 109a”. Is low. Since the common discharge line 141 extends to the surface of the interlayer insulating film 132 and the surface of the silicon nitride film 109a, the adhesion of the common discharge line 141 to the base is also ensured. In addition, the common discharge line 141 extends over the entire circumference along the first outer edge, and the scribe line region 102
Is directly connected to the surface of the semiconductor device in order to make the protection elements belonging to each function equally under a sufficiently low contact resistance with respect to ESD at any connection terminal.

Common discharge line 141 and upper metal wiring 14
0, 142, 143, 144, etc.
32 is covered with a third interlayer insulating film. The third interlayer insulating film includes the common discharge line 141 and the upper metal wiring 14.
0, 142, 143, and 144 directly cover the upper and side surfaces of the interlayer insulating film 132, and the (first) silicon oxide film 151 (the first silicon oxide film 151 of the third embodiment).
A stacked film of the SOG films 152a and 152b left on the side surfaces of the upper layer wiring 140 and the like and the (second) silicon oxide film 153 covering the silicon oxide film 151 including the SOG film 152a and the like). Consists of The third interlayer insulating film has a contact hole 1 reaching the P ⁺ type diffusion layer 116a and the like.
55 and the N ⁺ -type diffusion layer 117 or the N ⁺ -type diffusion layer 11
8b, contact holes 15 reaching 119b, etc.
6 and a contact hole 157 reaching the gate electrode 112, the tungsten silicide wiring 130 or the upper metal wirings 140 and 144, respectively.

On the surface of the third interlayer insulating film, an input / output signal connection terminal 160a and a ground potential (V _SS ) connection terminal 160 made of, for example, an aluminum alloy as a second metal material are provided.
b and a connection terminal such as a power supply potential (V _DD ) connection terminal 160b, a ground line 161 and a power supply line 162, and (second)
Common discharge line 163 and (second) upper metal wiring 164
a, 164b, 164c, 165, etc. are provided. Some upper metal wirings 165 are directly connected to the common discharge line 163. The line width of the common discharge line 163 is, for example, about 8 μm, and the upper metal wirings 164a, 164b,.
The line width between 164c and the upper metal wiring 165 directly connected to the common discharge line 163 is, for example, about 10 μm. The common discharge line 163 is provided almost directly above the common discharge line 141 via the third interlayer insulating film. The size of the input / output signal connection terminal 160a and the like is, for example, about 100 μm square, the line width of the ground line 161 and the power supply line 162 is 10 μm or more, and the distance between the input / output signal connection terminal 160a and the like and the common discharge line 141 is For example, it is about 90 μm.

Also in this embodiment, unlike the second conventional semiconductor device, the upper metal wiring 165 directly connected to the common discharge line 163 is connected to the upper metal wiring 144 via the contact hole 157. Are connected to the N ⁺ type diffusion layer 119a or the P ⁺ type diffusion layer 116b through the contact hole 136 or the contact hole 135, respectively. In this embodiment, the upper metal wiring of the same layer adjacent to the upper metal wiring 165 directly connected to the common discharge line 163 is the upper metal wiring 164b or the upper metal wiring 164c.
It is. For this reason, these adjacent distances are sufficiently wide (for example, wider than 10 μm), and are suitable for further miniaturization of the semiconductor device.

Signal connection terminals such as input / output signal connection terminal 160a are connected to upper metal wiring 164 directly connected thereto.
a and the N ⁺ -type diffusion layer 118 b via the contact hole 156. I / O signal connection terminal 1
A voltage clamp element as a first protection element and a first protection diode as a second protection element are connected in parallel between a signal connection terminal such as 60a and the common discharge line 141, respectively. Voltage clamp element is N ⁺ type diffusion layer 1
Consists lateral parasitic NPN transistor comprising 18a and the N ⁺ -type diffusion layer 118b, a first protection diode comprises an N ⁺ -type diffusion layer 118b and the P ⁺ -type diffusion layer 115.

Each of the ground potential connection terminals 160b is
The upper metal wiring 164b connected to the N ⁺ -type diffusion layer 118b via the upper metal wiring 164a and the contact hole 156 directly connected thereto, and directly connected thereto.
P ⁺ -type diffusion layer 116a through the contact hole 155
It is connected to the. Each ground potential connection terminal 160
b and a common discharge line 141, a voltage clamp element as a first protection element and a first protection diode as a second protection element are connected in parallel, respectively, and further, each ground potential connection terminal 160b A second protection diode, which is a third protection element, is connected between the second protection diode and the common discharge line 163. The second protection diode is N ⁺
And a P ⁺ -type diffusion layer 116a.

Each power supply potential connection terminal 160c is
The upper metal wiring 164c is connected to the N ⁺ -type diffusion layer 118b via the upper metal wiring 164a and the contact hole 156 directly connected to the upper metal wiring 164c.
N ⁺ type diffusion layer 119b through the contact hole 156
It is connected to the. Each power supply potential connection terminal 160
A voltage clamp element serving as a first protection element and a first protection diode serving as a second protection element are connected in parallel between c and the common discharge line 141, respectively. A third protection diode, which is a fourth protection element, is connected to each of the discharge lines 163. The third protection diode includes an N ⁺ -type diffusion layer 119b and a P ⁺ -type diffusion layer 116b (further, a P ⁺ -type diffusion layer 115).

An input buffer and an output buffer are connected to the input / output signal connection terminal 160a. Illustration of the input buffer is omitted. The output buffer comprises a first N-channel MOS transistor and a load MOS transistor (comprising a second N-channel MOS transistor).
N of one of source and drain of load MOS transistor
⁺ Type diffusion layer 117 and gate electrode 112 are connected to power supply line 162 (for example, via upper metal interconnection 140).
The distance between the upper metal wiring 140 and the common discharge line 141 is, for example, about 30 μm. The other N ⁺ type diffusion layer 117 of the source / drain of the load MOS transistor and N serving as the drain of the first N-channel MOS transistor
⁺ Type diffusion layer 117 is connected to input / output signal connection terminal 160a (for example, via upper metal wiring 165), and gate electrode 112 of the first N-channel MOS transistor is connected (for example, via tungsten silicide wiring 130).
An N ⁺ type diffusion layer 117 connected to an internal circuit and serving as a source of a first N-channel MOS transistor is connected to a ground line 161 (for example, via an upper metal wiring 165).

The first example of the fourth embodiment is as follows.
The third embodiment has the same effects as the first embodiment.

FIG. 24 which is a schematic plan view of a semiconductor device,
FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line GG of FIG.
5, the semiconductor device according to the second example of the fourth embodiment differs from the first example of the fourth embodiment in that the second silicon nitride film 109b And the interlayer insulating film 12 is replaced with the interlayer insulating film 12
3,133 are provided. In FIG. 24, silicon nitride films 109a and 109b are also provided for easy understanding.
In order to avoid complication in FIG. 25, the gate oxide film 111 and the SOG
The hatching of the film 152a is omitted.

The silicon nitride film 109b has a “U” -shaped portion formed by the upper metal wirings 142 and 143 constituting the protection elements belonging to the respective connection terminals such as the input / output signal connection terminal 160a and the common discharge line 141. Is provided at a position corresponding to. These silicon nitride films 109b also extend over the surface of scribe line region 102 via pad oxide film 107, and are formed of silicon nitride film 109b with respect to field oxide film 108 and scribe line region 102 (P ⁺ type diffusion layer 114). The overlap width is also, for example, 5.
They are about 5 μm and about 0.5 μm.

The positional relationship between the interlayer insulating film 123 and the interlayer insulating film 133 with respect to the silicon nitride films 109a and 109b is the same as that of the first embodiment in the fourth embodiment.
This is the same as the positional relationship between the interlayer insulating film 122 and the interlayer insulating film 132 with respect to the silicon nitride film 109a in the embodiment. The positional relationship of the common discharge line 141 with respect to the silicon nitride film 109b is the same as the positional relationship of the common discharge line 141 with respect to the silicon nitride film 109a. Therefore, the upper metal wiring 14 in the silicon nitride film 109b is formed.
2 and 143 and the common discharge line 141, the SOG film (not the SOG film 152 b) remaining on the side surface of the first upper metal wiring in these portions is formed. 152a.

The second embodiment has the same effects as the second embodiment of the third embodiment. In addition,
The position where the second silicon nitride film 109b is provided is not limited to the above position, and the semiconductor element formation region 10
The position may be any position away from the corner portion of No. 3.

It is also possible to combine the technical idea of the first embodiment with the technical idea of the third embodiment. The technical concept of the fifth embodiment of the present invention is based on such a combination.

FIG. 26, which is a schematic plan view of a semiconductor device,
Referring to FIG. 27 which is a schematic cross-sectional view of the semiconductor device taken along the line DD and the line HH in FIG. 26, the gist of the configuration of the semiconductor device according to one example of the fifth embodiment of the present invention is as follows. It is as follows. Also in FIG. 26, the silicon nitride films 109a and 109b are hatched,
In FIG. 27 (gate oxide film 111 and) SOG
The hatching of the film 152a is omitted.

On the surface of the field insulating film 108 near the corner of the semiconductor element forming region 103, (first
) Silicon nitride film 109c is provided,
0, the first U-shaped portion corresponding to the "U" -shaped portion formed by the (first) upper metal wirings 142 and 143 and the (first) common discharge line 141d which constitute the protection element of the input / output signal connection terminal 106a. A (second) silicon nitride film 109d is provided in the vicinity of the outer edge of the first silicon nitride film.

The second outer edge of the (first) interlayer insulating film 124 is provided so as to directly cover the surfaces of the silicon nitride films 109c and 109d. , 109d are provided so as to cover the surface of the scribe line region 102 directly. Cover the surface of the interlayer insulating film 124 (second)
The third outer edge of the interlayer insulating film 134 is also provided so as to directly cover the surface of the silicon nitride films 109c and 109d, and the silicon nitride films 109c and
In a portion without 109d, the scribe line region 102 is provided so as to directly cover the surface thereof.

The first common discharge line 141d (first outer peripheral wiring made of a first metal material) provided along the entire outer periphery along the first outer edge is a rectangular first discharge line. 4 and has a scribe line area 10 around the entire circumference.
2 are directly connected. Silicon nitride film 109c,
The inner edge of the common discharge line 141d at the portion 109d is provided to have a portion that directly covers the surfaces of the silicon nitride films 109c and 109d. The common discharge lines 141 are provided on the surfaces of the silicon nitride films 109c and 109d.
There are portions that are not covered by d and the interlayer insulating film 134, respectively. The inner edge of the portion without the silicon nitride films 109c and 109d is provided on the surface of the interlayer insulating film 134. The line width of the common discharge line 141d is smaller than in FIG.

As is apparent from such a structure, in the present embodiment, the only SOG film 152a left on the side surface of the first upper metal interconnection is the SOG film 152a.

The fifth embodiment is not limited to the above embodiment. In the fifth embodiment, the silicon nitride film 109d may not be provided (however, in this case, the SOG film 152b is left). Further, in the above-described embodiment, the distance between the fourth outer edge and the first outer edge is increased in a portion where the silicon nitride films 109c and 109d are provided, and the (first) common portion in these portions is increased. The line width of the discharge line and the portion without the silicon nitride film (first
) Can be made equal to the line width of the common discharge line.

The sixth embodiment and the sixth embodiment of the present invention apply the fifth embodiment of the semiconductor device having the second common discharge shallow formed by the second outer peripheral wiring made of the second metal material. It is.

FIG. 28, which is a schematic plan view of a semiconductor device,
Referring to FIG. 29 which is a schematic cross-sectional view of the semiconductor device taken along the line GG and the line HH in FIG. 28, the gist of the configuration of the semiconductor device according to one example of the sixth embodiment of the present invention is as follows. It is as follows. Also in FIG. 28, the silicon nitride films 109a and 109b are hatched,
In FIG. 29, (gate oxide film 111 and) SOG
The hatching of the film 152a is omitted.

On the surface of the field insulating film 108 near the corner of the semiconductor element formation region 103,
(First) upper metal wirings 142, 143 and a (first) common discharge line 141d which form protection elements for connection terminals such as input / output signal connection terminals 106a. The (second) silicon nitride film 1 is located near the first outer edge corresponding to the “U” -shaped portion.
09d is provided.

The second outer edge of the (first) interlayer insulating film 124 is provided so as to directly cover the surfaces of the silicon nitride films 109c and 109d. , 109d are provided so as to cover the surface of the scribe line region 102 directly. Cover the surface of the interlayer insulating film 124 (second)
The third outer edge of the interlayer insulating film 134 is also provided so as to directly cover the surface of the silicon nitride films 109c and 109d, and the silicon nitride films 109c and
In a portion without 109d, the scribe line region 102 is provided so as to directly cover the surface thereof.

The first common discharge line 141d (the first outer peripheral wiring made of the first metal material), which is provided along the entire outer periphery along the first outer edge portion, is formed of a rectangular shape. 4 and has a scribe line area 10 around the entire circumference.
2 are directly connected. Silicon nitride film 109c,
The inner edge of the common discharge line 141d at the portion 109d is provided to have a portion that directly covers the surfaces of the silicon nitride films 109c and 109d. The common discharge lines 141 are provided on the surfaces of the silicon nitride films 109c and 109d.
There are portions that are not covered by d and the interlayer insulating film 134, respectively. The inner edge of the portion without the silicon nitride films 109c and 109d is provided on the surface of the interlayer insulating film 134. The line width of the common discharge line 141d is smaller than in FIG.

As is apparent from such a structure, in the present embodiment, the only SOG film left on the side surface of the first upper metal interconnection is the SOG film 152a.

The sixth embodiment is not limited to the above embodiment. In the fifth embodiment, the silicon nitride film 109d may not be provided (however, in this case, the SOG film 152b is left). Further, in the above-described embodiment, the distance between the fourth outer edge and the first outer edge is increased in a portion where the silicon nitride films 109c and 109d are provided, and the (first) common portion in these portions is increased. The line width of the discharge line and the portion without the silicon nitride film (first
) Can be made equal to the line width of the common discharge line.

[0198]

As described above, in the semiconductor device of the present invention, at least in the vicinity of the corner of the rectangular semiconductor element formation region, (the second interlayer insulating film is laminated on at least the first interlayer insulating film). Of the upper surface at the inner edge of the outer peripheral wiring (consisting of the first upper metal wiring and directly connected to the scribe line region over the entire circumference) provided on the surface of the lower interlayer insulating film (of the laminated structure). The height can be minimized.

Therefore, according to the present invention, the degree of remaining of the SOG film constituting a part of the upper interlayer insulating film is controlled,
S on the side surface of the contact hole provided in the upper interlayer insulating film
The exposure of the OG film is avoided, and the increase of the contact resistance and the suppression of the corrosion of the second upper metal wiring provided on the surface of the upper interlayer insulating film in this contact hole are facilitated.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a first example of the first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the first example of the first embodiment, taken along line AA and BB in FIG. 1;

FIG. 3 is a schematic cross-sectional view of the first example of the first embodiment, and is a schematic cross-sectional view taken along line DD of FIG. 1;

FIG. 4 is a schematic cross-sectional view of the manufacturing process of the first example of the first embodiment, and is a schematic cross-sectional view of the manufacturing process along line AA in FIG. 1;

FIG. 5 is a schematic plan view of a main part of an application example of the first embodiment of the first embodiment.

FIG. 6 is a schematic plan view of a second example of the first embodiment.

FIG. 7 is a schematic sectional view of the second example of the first embodiment, and is a schematic sectional view taken along line DD of FIG.

FIG. 8 is a schematic plan view of a main part of an application example of the second example of the first embodiment.

FIG. 9 is a schematic plan view of a third example of the first embodiment.

FIG. 10 is a schematic cross-sectional view of the third example of the first embodiment, taken along line AA and EE in FIG. 9;

FIG. 11 is a schematic plan view of a main part of an application example of the third example of the first embodiment.

FIG. 12 is a schematic plan view of a first example of the second embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view of the first example of the second embodiment, showing the AA line, the FF line and the GG line of FIG. 12;
FIG. 3 is a schematic sectional view taken along a line.

FIG. 14 is a schematic sectional view of the first example of the second embodiment, and is a schematic sectional view taken along line CC of FIG.

FIG. 15 is a schematic plan view of a second example of the second embodiment.

FIG. 16 is a schematic sectional view of the second example of the second embodiment, taken along the line AA, EE and GG in FIG.
FIG. 3 is a schematic sectional view taken along a line.

FIG. 17 is a schematic plan view of a first example of the third embodiment of the present invention.

18 is a schematic cross-sectional view of the first example of the third embodiment, taken along line AA, DD and HH in FIG.
FIG. 3 is a schematic sectional view taken along a line.

FIG. 19 is a schematic cross-sectional view of the manufacturing process of the first example of the third embodiment, and is a schematic cross-sectional view of the manufacturing process along line HH in FIG. 17;

FIG. 20 is a schematic plan view of a second example of the third embodiment.

21 is a schematic cross-sectional view of the second example of the third embodiment and a schematic cross-sectional view taken along line DD of FIG. 20.

FIG. 22 is a schematic plan view of a first example of the fourth embodiment of the present invention.

FIG. 23 is a schematic sectional view of the first example of the fourth embodiment, taken along line AA, line GG and line HH in FIG.
FIG. 3 is a schematic sectional view taken along a line.

FIG. 24 is a schematic plan view of a second example of the fourth embodiment.

FIG. 25 is a schematic sectional view of the second example of the fourth embodiment, and is a schematic sectional view taken along line GG of FIG. 24.

FIG. 26 is a schematic plan view of an example of the fifth embodiment of the present invention.

FIG. 27 is a schematic cross-sectional view of the example of the fifth embodiment, taken along line DD and HH in FIG. 26.

FIG. 28 is a schematic plan view of an example of the sixth embodiment of the present invention.

FIG. 29 is a schematic cross-sectional view of the example of the sixth embodiment, taken along line GG and HH in FIG. 28.

FIG. 30 is a circuit diagram of a first protection circuit of the semiconductor device.

FIG. 31 is a schematic plan view of a first conventional semiconductor device.

FIG. 32 is a schematic cross-sectional view of the manufacturing process of the first conventional semiconductor device, and is a schematic cross-sectional view of the manufacturing process along line AA in FIG. 31;

FIG. 33 is a schematic sectional view of the first conventional semiconductor device, taken along line BB of FIG. 31;

FIG. 34 is a circuit diagram of a second protection circuit of the semiconductor device.

FIG. 35 is a schematic plan view of a second conventional semiconductor device.

FIG. 36 is a schematic sectional view of the second conventional semiconductor device, taken along the line AA in FIG. 35.

FIG. 37 is a schematic cross-sectional view of the second conventional semiconductor device, taken along the line CC in FIG. 35.

[Explanation of symbols]

101, 201 P-type silicon substrate 102, 202 Scribe line area 103, 203 Semiconductor element formation area 104, 204 Active area 105, 205 Element isolation area 106, 106a, 106b, 206, 206a, 20
6b N-type well 107 pad oxide film 109a, 109b, 109c, 109d silicon nitride film 111, 211 gate oxide film 112, 212 gate electrode 113, 114, 115, 116a, 116b, 21
3, 214, 215, 216a, 216b P ⁺ type diffusion layers 117, 118a, 118b, 119a, 119b, 2
17, 218a, 218b, 219a, 219b N
⁺ Type diffusion layer 121, 122, 123, 124, 131, 132, 1
33, 134, 221, 321 Interlayer insulating films 125, 126, 135, 136, 137, 155, 1
56,157,225,226,235,236,23
7, 255, 256, 257 contact hole 130,
230 Tungsten silicide wiring 140, 142, 143, 144, 164a, 164
b, 164c, 165, 240, 242, 243, 26
4a, 264b, 264c, 265, 266 Upper metal wiring 141, 141a, 141aa, 141b, 141b
a, 141c, 141ca, 141d, 163, 24
1,263 Common discharge line 151,153,251,253 Silicon oxide film 152,152a, 152b, 252,252A, 25
2a, 252b SOG film 160, 260 Connection terminal 160a, 260a Input / output signal connection terminal 160b, 260b Ground potential connection terminal 160c, 260c Power supply potential connection terminal 161,261 Ground line 162,262 Power supply line 171,172,173 Photoresist film pattern

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/04 H01L 21/3205 H01L 21/822 H01L 21/8234 H01L 27/088

Claims (33)

(57) [Claims] A first P-type silicon substrate has a first P-type silicon substrate.
^A scribe line region including a ⁺ -type diffusion layer and an active region
And an element isolation region including a field insulating film.
And a semiconductor element region formed in a rectangular shape.
The active region is defined by at least a first and a second N ⁺ -type extension defined by a first outer edge of the edge membrane.
A diffusion layer and a second P ⁺ -type diffusion layer, and a first protective element.
The voltage clamp element, which is the first N ⁺ -type diffusion layer,
And a second N ⁺ type diffusion layer, and the second protection element
Certain protection diodes include the second N ⁺ type diffusion layer and the second
It comprises a P ⁺ type diffusion layer, wherein the semiconductor element region is covered by the first interlayer insulating film,
The first interlayer insulating film has a second outer edge, and the second interlayer insulating film has a second outer edge.
Outer edge directly covers the surface of the scribe line area.
The first interlayer insulating film is covered with a second interlayer insulating film,
The second interlayer insulating film has a third outer edge, and the third interlayer insulating film has a third outer edge.
Outer edge directly covers the surface of the scribe line area
A first metal material is provided on the surface of the second interlayer insulating film.
First upper metal wiring and common discharge line (CDL)
Is provided, and the common discharge line is provided through the first upper metal wiring.
The first N ⁺ -type diffusion layer and the second P ⁺ -type diffusion layer
And at least a part of the common discharge line is
Along the first outer edge, the common discharge line has a fourth outer edge and an inner edge.
And the fourth outer edge is a surface of the scribe line area.
And the first outer edge is provided in a manner to directly cover the first outer edge.
The inner edge at the portion provided along the edge is the
Provided so as to directly cover the surface of the second interlayer insulating film.
And the common discharge line extends along the first outer edge.
The inner edge at the portion provided by the second outer
Front provided between a side edge and said third outer edge
A first portion near a corner of the semiconductor element forming region;
And a portion provided along the first outer edge portion.
An inner edge is formed on the first interlayer insulating film via the second interlayer insulating film .
At least a second portion provided on the interlayer insulating film;
And, an upper surface of the first upper metal interconnection, and the common discharge line and
The second interlayer insulating film including a side surface is a third interlayer insulating film
And the third interlayer insulating film is aligned with the first upper metal wiring.
Upper and side surfaces of a common discharge line and the second interlayer insulating film
A first silicon oxide film directly covering the surface of the first silicon oxide film;
The first upper metal interconnection and the silicon oxide film of
An SOG film remaining on the side of the common discharge line, and the SOG film
And a second silicon oxide film covering the first silicon oxide film.
And a second metal material on the surface of the third interlayer insulating film.
Second upper metal wiring and connection terminals (bonding
Pad), and the connection terminal is connected to the second upper metal layer
Connected to the second N ⁺ type diffusion layer through a wiring .
Ri, the second, outer edges of the third and fourth A semiconductor device characterized by each a rectangular. 2. In a position distant from the first portion, the inner edge portion at a portion provided along the first outer edge portion is connected to the second outer edge portion and the second outer edge portion. 2. The semiconductor device according to claim 1 , wherein the common discharge line has a third portion provided between the common discharge line and the outer edge of the common discharge line. 3. 3. A semiconductor wherein said connection terminals are provided at a predetermined interval on a surface of said third interlayer insulating film on said semiconductor element formation region near said first outer edge. The device, wherein the third portion of the common discharge line is connected to a first upper metal wiring connected to the first N ⁺ -type diffusion layer and to the second P ⁺ -type diffusion layer. 3. The semiconductor device according to claim 2 , wherein said semiconductor device is provided between said first upper metal wiring. Wherein said second and third rectangular outer edges, respectively, said fourth outer edge of the third of the first part
Outer distance between the edges is wider claim than the distance between the outer edge portion of the third outer edge of the fourth in the second portion excluding the vicinity of the first portion of the 2. The semiconductor device according to 1 . 5. A position apart from the first portion, the said inner edge is the second outer edge portion of the first portion provided along the outer edge the The common discharge line has a third portion provided between the third outer edge and the fourth outer edge of the third and third portions. The distance between the third portion of the second portion excluding the vicinity of the first and third portions is equal to the distance from the edge portion.
Wider 請 than the distance between the outer edge and the outer edge of said fourth
The semiconductor device according to claim 4 . 6. A semiconductor, wherein said connection terminals are provided on a surface of said third interlayer insulating film on said semiconductor element formation region near said first outer edge with a predetermined interval. The device, wherein the third portion of the common discharge line is connected to a first upper metal wiring connected to the first N ⁺ type diffusion layer and the second P ⁺ diffusion layer.
6. The semiconductor device according to claim 5, wherein the semiconductor device is provided between the first upper metal wiring connected to the ⁺ type diffusion layer. 7. The first P-type silicon substrate has a first P-type silicon substrate.
^A scribe line region including a ⁺ -type diffusion layer; and a semiconductor element region including an active region and an element isolation region including a field insulating film. The semiconductor element region is formed of a rectangular field. The surface of the field insulating film is defined directly by a first outer edge of the insulating film and near a corner of the semiconductor element forming region, and covers the surface of the scribe line region via a pad oxide film. A first silicon nitride film is provided, and at least a first and a second N ⁺ -type diffusion layer and a second P ⁺ -type diffusion layer are provided in the active region, and a voltage clamp serving as a first protection element is provided. The device includes the first N ⁺ -type diffusion layer and the second N ⁺ -type diffusion layer, and the protection diode serving as the second protection device includes the second N ⁺ -type diffusion layer and the second N ⁺ -type diffusion layer.
Comprises a P ⁺ type diffusion layer, wherein the semiconductor element region in the first region excluding the silicon nitride film is covered with the first interlayer insulating film, the first interlayer insulating film nitriding the first Directly covers a portion of the surface of the silicon film, the first interlayer insulating film has a second outer edge, and the second outer edge covers the surface of the first silicon nitride film. The first scribe line region is provided so as to cover directly the surface of the scribe line region in a region except for the first silicon nitride film, and the first interlayer insulating film is covered by a second interlayer insulating film. The second interlayer insulating film directly covers a part of the surface of the first silicon nitride film, the second interlayer insulating film has a third outer edge, and the third interlayer insulating film has a third outer edge. The outer edge directly covers the surface of the first silicon nitride film, and is located in a region excluding the first silicon nitride film. A first upper metal wiring made of a first metal material and a common discharge line are provided on the surface of the second interlayer insulating film. Wherein the common discharge line is connected to the first N ⁺ -type diffusion layer and the second P ⁺ -type diffusion layer via the first upper metal wiring, respectively, and at least one of the common discharge lines A portion is provided along the first outer edge, the common discharge line has a fourth outer edge and an inner edge, and the fourth outer edge is The first silicon nitride film is provided so as to directly cover the surface of the scribe line region, and the inner edge at a portion provided along the first outer edge is provided by the first silicon nitride film. Directly covers the surface of the first silicon nitride film in the defined region, and is directly in contact with the third outer edge. And intersects with the second outer edge portion via the second interlayer insulating film, and further includes a portion where the first silicon nitride film does not exist. An upper surface and side surfaces of the first upper metal wiring and the common discharge line, and a part of the surface of the silicon nitride film provided so as to cover the surface of the first interlayer insulating film via an interlayer insulating film; The second interlayer insulating film is covered with a third interlayer insulating film, and the third interlayer insulating film is formed on the upper and side surfaces of the first upper metal wiring and the common discharge line and the second interlayer insulating film. A first silicon oxide film directly covering the surface of the interlayer insulating film and a part of the surface of the first silicon nitride film; and the first upper metal wiring and the first silicon oxide film via the first silicon oxide film. An SOG film remaining on the side surface of the common discharge line; and an SOG film including the SOG film. A second silicon oxide film covering the first silicon oxide film, and a second upper metal wiring and a connection terminal made of a second metal material are provided on a surface of the third interlayer insulating film. , The connection terminal is connected to the second N layer via the second upper metal wiring.
A semiconductor device which is connected to a ⁺ type diffusion layer. And wherein said fourth outer edges, said first and the said inner edge at a portion that is provided along the outer edge, a semiconductor according to claim 7, wherein each of the rectangular apparatus. 9. A second silicon nitride film which directly covers the surface of the field insulating film and covers the surface of the scribe line region via a pad oxide film at a position distant from the first silicon nitride film. A part of the surface of the second silicon nitride film is directly covered by the first and second interlayer insulating films, respectively;
9. The device according to claim 8 , wherein the inner edge portion at a portion provided along the first outer edge portion is provided so as to directly cover the surface of the second silicon nitride film. Semiconductor device. 10. A semiconductor, wherein said connection terminals are provided on a surface of said third interlayer insulating film on said semiconductor element forming region near said first outer edge with a predetermined interval. The device, wherein the second silicon nitride film has a first upper metal interconnect connected to the first N ⁺ -type diffusion layer and a first upper metal interconnect connected to the second P ⁺ -type diffusion layer. 10. The semiconductor device according to claim 9 , wherein the semiconductor device is provided in a region including a portion sandwiched between the upper metal wiring. 11. The fourth outer edge is rectangular.
The overlap width between the common discharge line and the first silicon nitride film at a portion where the inner edge directly covers the surface of the first silicon nitride film is such that the inner edge is the second width. 8. The semiconductor device according to claim 7 , wherein an overlap width between the common discharge line and the first silicon nitride film at a portion intersecting an outer edge is smaller. 12. A position away from the first silicon nitride film directly covering the surface of the field insulating film, a second silicon nitride film over the pad oxide film covering the surface of the scribe line region A part of the surface of the second silicon nitride film is directly covered by the first and second interlayer insulating films, respectively;
The inner edge at a portion provided along the first outer edge is provided so as to directly cover the surface of the second silicon nitride film; The overlap width of the common discharge line and the second silicon nitride film in a portion directly covering the surface of the second silicon nitride film is such that the inner edge crosses the second outer edge. 12. The semiconductor device according to claim 11 , wherein an overlap width between the common discharge line and the second silicon nitride film in a portion where the common discharge line overlaps is smaller. 13. A semiconductor, wherein said connection terminals are provided on a surface of said third interlayer insulating film on said semiconductor element formation region near said first outer edge with a predetermined interval. The device, wherein the second silicon nitride film has a first upper metal interconnect connected to the first N ⁺ -type diffusion layer and a first upper metal interconnect connected to the second P ⁺ -type diffusion layer. 13. The semiconductor device according to claim 12 , wherein the semiconductor device is provided in a region including a portion sandwiched between the upper metal wiring. 14. The space between the first outer edge and the fourth outer edge at a portion where the inner edge directly covers the surface of the first silicon nitride film, A distance between the first outer edge and the fourth outer edge at a position distant from the first silicon nitride film, wherein the inner edge is the first silicon nitride film. The overlap width of the common discharge line and the first silicon nitride film in a portion directly covering the surface of the first silicon nitride film is such that the inner edge is the second outer edge on the first silicon nitride film. 8. The semiconductor device according to claim 7 , wherein an overlap width between said common discharge line and said first silicon nitride film at a portion intersecting with said first silicon nitride film is narrower. 15. A second silicon nitride film directly covering the surface of the field insulating film and covering the surface of the scribe line region via a pad oxide film at a position distant from the first silicon nitride film. A part of the surface of the second silicon nitride film is directly covered by the first and second interlayer insulating films, respectively;
The inner edge at a portion provided along the first outer edge is provided so as to directly cover the surface of the second silicon nitride film; The first outer edge portion at a portion directly covering the surface of the second silicon nitride film and the fourth outer edge portion;
Of the first silicon nitride film at a position away from the first silicon nitride film and the second silicon nitride film.
The common discharge line at a portion where the inner edge directly covers the surface of the second silicon nitride film; The width of the overlap with the second silicon nitride film is larger than the width of the overlap between the common discharge line and the second silicon nitride film at a portion where the inner edge crosses the second outer edge. The semiconductor device according to claim 14 , wherein the width is reduced. 16. A semiconductor wherein said connection terminals are provided on a surface of said third interlayer insulating film on said semiconductor element forming region near said first outer edge with a predetermined interval. The device, wherein the second silicon nitride film has a first upper metal interconnect connected to the first N ⁺ -type diffusion layer and a first upper metal interconnect connected to the second P ⁺ -type diffusion layer. 16. The semiconductor device according to claim 15 , wherein the semiconductor device is provided in a region including a portion sandwiched between the upper metal wiring. 17. A semiconductor element region including a scribe line region including a first P ⁺ type diffusion layer and an element isolation region including an active region and a field insulating film on a surface of a P-type silicon substrate. Wherein the semiconductor element region is defined by a first outer edge of the field insulating film having a rectangular shape, and the semiconductor element region is provided with at least first and second N-type wells; The active region is provided with at least first and second N ⁺ -type diffusion layers and a second P ⁺ -type diffusion layer, and a voltage clamp element serving as a first protection element is provided in the first N ⁺ -type diffusion layer. and it comprises a second N ⁺ -type diffusion layer, the first protective diode is a second protection element comprises a second of the N ⁺ -type diffusion layer and the second P ⁺ -type diffusion layer, The active region provided in the first N-type well has a P ⁺ -type diffusion and third N ⁺ -type diffusion layer is provided in the second protective diode is a third protection element consists P ⁺ -type diffusion and third N ⁺ -type diffusion layer of the third in said silicon substrate and a second N-type well and the active region provided in the N-type well of the active region and the second which is provided in a region including the boundary of the fourth N ⁺ -type diffusion layer a fourth P ⁺ -type diffusion layer is provided respectively, a third protection diode is a fourth protection element consists fourth P ⁺ type diffusion and the fourth N ⁺ -type diffusion layer, the first The semiconductor element region is covered with an interlayer insulating film,
The first interlayer insulating film has a second outer edge, and the second interlayer insulating film has a second outer edge.
Is provided so as to directly cover the surface of the scribe line region, the first interlayer insulating film is covered by a second interlayer insulating film,
The second interlayer insulating film has a third outer edge, and the third interlayer insulating film has a third outer edge.
Is provided so as to directly cover the surface of the scribe line region, and a first upper metal interconnection made of a first metal material is provided on a surface of the second interlayer insulating film. And a first common discharge line is provided, at least a portion of the first common discharge line is provided along the first outer edge, and the first common discharge line is a fourth outer edge An end portion and an inner edge portion, the fourth outer edge portion is provided so as to directly cover the surface of the scribe line region, and is provided along the first outer edge portion. The inner edge of the provided portion is provided so as to directly cover the surface of the second interlayer insulating film, and the first common discharge line is provided with the first outer edge. The inner edge of the portion provided along the portion is the second edge.
A first portion near a corner of the semiconductor element formation region provided between the outer edge of the semiconductor device and the third outer edge, and provided along the first outer edge. The inner edge of the first portion through the second interlayer insulating film.
At least a second portion provided on the first interlayer insulating film, and the second interlayer insulating film includes a third portion including a top surface and a side surface of the first upper metal wiring and the first common discharge line. The third interlayer insulating film directly covers the upper surface and side surfaces of the first upper metal wiring and the first common discharge line and the surface of the second interlayer insulating film. A first silicon oxide film;
An SOG film left on the side of the first upper metal wiring and the common discharge line via the first silicon oxide film;
A second silicon oxide film including an OG film and covering the first silicon oxide film; and a second common insulating film made of a second metal material on a surface of the third interlayer insulating film. An electric wire, a plurality of second upper metal wirings made of the second metal material, a signal connection terminal, a ground potential (V _cc ) connection terminal, and a power supply potential (V _DD ) connection terminal; At least a portion of the common discharge line is provided along the first outer edge, and the first common discharge line is connected to the first N ⁺ type diffusion through the first upper metal wiring. is connected to each of said the layer second P ⁺ -type diffusion layer, the second common discharge line, through the second upper metal interconnect and the first upper metal wiring, the third, respectively N
⁺ -Type diffusion layer and connected to the fourth P ⁺ -type diffusion layer, the signal connecting terminal is connected to said second N ⁺ -type diffusion layer through the second upper metal wiring, the ground potential connection The terminals are respectively connected to the second N layer via the second upper metal wiring.
⁺ Power diffusion layer and the third P ⁺ -type diffusion layer, and the power supply potential connection terminal is connected to the second N ⁺ -type diffusion layer and the fourth A semiconductor device connected to an N ⁺ type diffusion layer. 18. The semiconductor device according to claim 17 , wherein each of said second, third and fourth outer edges is rectangular. 19. A position distant from said first portion, wherein said inner edge portion at a portion provided along said first outer edge portion is connected to said second outer edge portion and said second outer edge portion. 19. The semiconductor device according to claim 17 , wherein the first common discharge line has a third portion provided between the first common discharge line and the outer edge of the third common discharge line. 20. At least a part of the signal connection terminal, the ground potential connection terminal, and the power supply potential connection terminal are provided at predetermined intervals on the semiconductor element formation region near the first outer edge. A semiconductor device provided on a surface of the third interlayer insulating film, wherein the third portion of the first common discharge line is connected to the first N ⁺ type diffusion layer. 20. The semiconductor device according to claim 19 , wherein the semiconductor device is provided between the first upper metal wiring and the first upper metal wiring connected to the second P ⁺ -type diffusion layer. 21. The second outer edge and the third outer edge each have a rectangular shape, and the third outer edge and the fourth edge in the first portion.
Outer distance between the edges is wider claim than the distance between the outer edge portion of the third outer edge of the fourth in the second portion excluding the vicinity of the first portion of the 18. The semiconductor device according to item 17 . 22. At a position apart from the first portion, the inner edge at a portion provided along the first outer edge is connected to the second outer edge and the second outer edge. The first common discharge line has a third portion provided between the third outer edge portion and the third outer edge portion in the first and third portions. The distance between the outer edge of the second portion and the third edge of the second portion excluding the vicinity of the first and third portions is
Wider 請 than the distance between the outer edge and the outer edge of said fourth
22. The semiconductor device according to claim 21 . 23. At least a part of the signal connection terminal, the ground potential connection terminal, and the power supply potential connection terminal are provided on the semiconductor element formation region near the first outer edge with a required interval. A semiconductor device provided on a surface of the third interlayer insulating film, wherein the third portion of the first common discharge line is connected to the first N ⁺ type diffusion layer. 23. The semiconductor device according to claim 22 , wherein said semiconductor device is provided between said upper metal wiring and said first metal wiring connected to said second P ⁺ type diffusion layer. 24. A semiconductor comprising a scribe line region including a first P ⁺ -type diffusion layer and an element isolation region including an active region and a field insulating film on a surface of a P-type silicon substrate. An element region, wherein the semiconductor element region is defined by a first outer edge of the field insulating film having a rectangular shape, and the semiconductor element region has at least first and second N-type wells. , said active region and at least first and second N ⁺ -type diffusion layer and the second P ⁺ -type diffusion layer is provided, the voltage clamping element is a first protective element of said 1 N ⁺
Comprises a diffusion layer and a second N ⁺ -type diffusion layer, the first protective diode is a second protection element comprises a second of the N ⁺ -type diffusion layer and the second P ⁺ -type diffusion layer in result, the in the active region provided on the first N-type well it is provided a third P ⁺ -type diffusion and third N ⁺ -type diffusion layer, a second protective a third protection element A diode comprising the third P ⁺ -type diffusion layer and the third N ⁺ -type diffusion layer; an active region provided in a region including a boundary between the silicon substrate and the second N-type well; A fourth N ⁺ -type diffusion layer and a fourth P ⁺ -type diffusion layer are respectively provided in the active region provided in the N-type well, and the third protection diode, which is the fourth protection element, is provided in the active region. consists of four P ⁺ type diffusion and the fourth N ⁺ -type diffusion layer, at the corner portion near the semiconductor element forming region, wherein A first silicon nitride film which directly covers the surface of the field insulating film and covers the surface of the scribe line region via a pad oxide film; and the semiconductor element region in a region excluding the first silicon nitride film is provided. Is covered with a first interlayer insulating film, the first interlayer insulating film directly covers a part of the surface of the first silicon nitride film, and the first interlayer insulating film is formed on a second outer edge portion. Wherein the second outer edge directly covers the surface of the first silicon nitride film, and directly covers the surface of the scribe line region in a region excluding the first silicon nitride film. Wherein the first interlayer insulating film is covered by a second interlayer insulating film, and the second interlayer insulating film directly covers a part of the surface of the first silicon nitride film; The second interlayer insulating film has a third outer edge, and the third outer insulating film has a third outer edge. The edge is provided so as to directly cover the surface of the first silicon nitride film and to directly cover the surface of the scribe line region in a region excluding the first silicon nitride film; On the surface of the second interlayer insulating film, a first upper layer metal wiring made of a first metal material and a first common discharge line are provided, and at least a part of the first common discharge line is the first common discharge line. The first common discharge line has a fourth outer edge and an inner edge, and the fourth outer edge has a scribe line area. The inner edge portion of the portion provided along the first outer edge portion is a region where the first silicon nitride film is provided. And directly covering the surface of the first silicon nitride film and directly contacting the third outer edge. Intersecting with each other and intersecting with the second outer edge portion via the second interlayer insulating film, and further provided at a portion where the first silicon nitride film is absent. An upper surface and a side surface of the first upper metal wiring and a first common discharge line and a surface of the silicon nitride film, the first upper metal wiring and the first common discharge line being provided so as to cover a surface of the first interlayer insulating film via an insulating film; The second interlayer insulating film, including a part thereof, is covered with a third interlayer insulating film, and the third interlayer insulating film is formed on an upper surface of the first upper metal wiring and a first common discharge line and A first silicon oxide film directly covering a side surface, a surface of the second interlayer insulating film, and a part of a surface of the first silicon nitride film, and the first silicon oxide film via the first silicon oxide film; Film remaining on the side surfaces of the upper metal wiring and the common discharge line, and the SOG film A second common discharge line made of a second metal material on a surface of the third interlayer insulating film, the second common discharge line comprising: A plurality of second upper metal wirings, a signal connection terminal, a ground potential connection terminal, and a power supply potential connection terminal, each of which is made of the second metal material; The first common discharge line is provided along an outer edge of the first N ⁺ -type diffusion layer and the second P ⁺ -type diffusion layer via the first upper metal wiring. And the second common discharge line is connected to the third N line via the second upper metal wiring and the first upper metal wiring, respectively.
⁺ -Type diffusion layer and connected to the fourth P ⁺ -type diffusion layer, the signal connecting terminal is connected to said second N ⁺ -type diffusion layer through the second upper metal wiring, the ground potential connection A terminal is connected to the second N ⁺ -type diffusion layer and the third P ⁺ -type diffusion layer via the second upper metal wiring, respectively, and the power supply potential connection terminal is connected to the second upper metal wiring. Wherein the semiconductor device is connected to the second N ⁺ -type diffusion layer and the fourth N ⁺ -type diffusion layer, respectively. 25. A said fourth outer edges, said inner edge at said first portion disposed along the outer edge portion, a semiconductor of claim 24 wherein each a rectangular apparatus. 26. A second silicon nitride film which covers the surface of the field insulating film directly and covers the surface of the scribe line region via a pad oxide film at a position distant from the first silicon nitride film. A part of the surface of the second silicon nitride film is directly covered by the first and second interlayer insulating films, respectively;
26. The device according to claim 25 , wherein the inner edge portion at a portion provided along the first outer edge portion is provided so as to directly cover the surface of the second silicon nitride film. Semiconductor device. 27. At least a part of the signal connection terminal, the ground potential connection terminal, and the power supply potential connection terminal are provided on the semiconductor element forming region near the first outer edge with a required interval. A semiconductor device provided on a surface of the third interlayer insulating film, wherein the second silicon nitride film is connected to a first upper metal wiring connected to the first N ⁺ type diffusion layer; 27. The semiconductor device according to claim 26 , wherein the semiconductor device is provided in a region including a portion sandwiched between the first upper metal wiring connected to the second P ⁺ type diffusion layer. 28. The fourth outer edge is rectangular.
The overlap width of the first common discharge line and the first silicon nitride film in a portion where the inner edge directly covers the surface of the first silicon nitride film is such that the inner edge is 25. The semiconductor device according to claim 24 , wherein an overlap width between the first common discharge line and the first silicon nitride film at a portion intersecting with a second outer edge is smaller. 29. A second silicon nitride film directly covering the surface of the field insulating film and covering the surface of the scribe line region via a pad oxide film at a position distant from the first silicon nitride film. A part of the surface of the second silicon nitride film is directly covered by the first and second interlayer insulating films, respectively;
The inner edge at a portion provided along the first outer edge is provided so as to directly cover the surface of the second silicon nitride film; The overlap width between the first common discharge line and the second silicon nitride film in a portion directly covering the surface of the second silicon nitride film is such that the inner edge is the second outer edge. 29. The semiconductor device according to claim 28 , wherein an overlap width between the first common discharge line and the second silicon nitride film at a portion intersecting the portion is narrower. 30. At least a part of the signal connection terminal, the ground potential connection terminal, and the power supply potential connection terminal are provided on the semiconductor element forming region near the first outer edge with a required interval. A semiconductor device provided on a surface of the third interlayer insulating film, wherein the second silicon nitride film is connected to a first upper metal wiring connected to the first N ⁺ type diffusion layer; 30. The semiconductor device according to claim 29 , wherein the semiconductor device is provided in a region including a portion sandwiched between the first upper metal wiring connected to the second P ⁺ type diffusion layer. 31. A distance between the first outer edge and the fourth outer edge at a portion where the inner edge directly covers the surface of the first silicon nitride film is equal to the distance between the first outer edge and the fourth outer edge. A distance between the first outer edge and the fourth outer edge at a position distant from the first silicon nitride film, wherein the inner edge is the first silicon nitride film. The overlap width between the first common discharge line and the first silicon nitride film in the portion directly covering the surface of the first silicon nitride film is the same as that in the portion where the inner edge crosses the second outer edge. 25. The semiconductor device according to claim 24 , wherein an overlap width between the first common discharge line and the first silicon nitride film is smaller. 32. A second silicon nitride film directly covering the surface of the field insulating film and covering the surface of the scribe line region via a pad oxide film at a position apart from the first silicon nitride film. A part of the surface of the second silicon nitride film is directly covered by the first and second interlayer insulating films, respectively;
The inner edge at a portion provided along the first outer edge is provided so as to directly cover the surface of the second silicon nitride film; The first outer edge portion at a portion directly covering the surface of the second silicon nitride film and the fourth outer edge portion;
Of the first silicon nitride film at a position away from the first silicon nitride film and the second silicon nitride film.
The common discharge line at a portion where the inner edge directly covers the surface of the second silicon nitride film; The width of the overlap with the second silicon nitride film is larger than the width of the overlap between the common discharge line and the second silicon nitride film at a portion where the inner edge crosses the second outer edge. 32. The semiconductor device according to claim 31, which is narrowed. 33. At least a part of the signal connection terminal, the ground potential connection terminal, and the power supply potential connection terminal are provided on the semiconductor element forming region near the first outer edge with a required interval. A semiconductor device provided on a surface of the third interlayer insulating film, wherein the second silicon nitride film is connected to a first upper metal wiring connected to the first N ⁺ type diffusion layer; 33. The semiconductor device according to claim 32 , wherein the semiconductor device is provided in a region including a portion sandwiched between the first upper metal wiring connected to the second P ⁺ -type diffusion layer.