JP3200862B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to an array structure of memory cells in a semiconductor memory device.

[0002]

2. Description of the Related Art FIGS. 11 and 1 show an example of a MOS type SRAM in which a memory cell includes a pair of transfer transistors, a pair of driving transistors, and a pair of load resistors.
With reference to FIG. 2 and FIG. 13, a description will be given of an arrangement of memory cells in a conventional semiconductor memory device. FIG.
FIGS. 12 and 13 are schematic plan views showing the electrical connection relationship between the memory cell and the bit line, the ground wiring, and the power supply wiring.

A P-well (not shown) is provided on the surface of an N-type silicon substrate (not shown), and an element formation region 211 is formed on the surface thereof surrounded by a field oxide film (not shown). A gate oxide film (not shown) is provided on the surface of the element forming region 211. On the field oxide film and the gate oxide film, word lines 221 and 222 and a gate electrode 22 made of a first layer of N ⁺ type polycrystalline silicon film are formed.
3 are provided. In the element formation region 211, an N ⁺ diffusion layer (not shown) is formed in a region that does not intersect with the word lines 221 and 222 and the gate electrode 223. The transfer transistors T21a and T22a are formed by the word line 221 and the element formation region 211, and the transfer transistors T21b and T22b are formed by the word line 222 and the element formation region 211.

[0004] Transfer transistors T21a, T
21b there is provided a contact hole 242 for electrical connection between the bit line 231 to the N ⁺ diffusion layer shared, transfer transistor T22a, the N ⁺ diffusion layer T22b share electrical connection between the bit line 232 Contact hole 243 is provided. The bit lines 231 and 232 made of an aluminum film form a pair and have an opposite phase relationship. A drive transistor T is provided immediately below the bit line 231.
23a and T23b are provided, and drive transistors T24a and T24b are provided immediately below the bit line 232. The driving transistors T23a and T24a and the driving transistors T23b and T24b are flip-flop coupled via the direct contact holes 241 respectively. The N ⁺ diffusion layer of the transfer transistor T21a on which the contact hole 242 is not provided is connected to the gate electrode 223 of the driving transistor T23a and the N ⁺ diffusion layer of the drain side of the driving transistor T24a. The N ⁺ diffusion layer on the side not provided is connected to the gate electrode 223 of the driving transistor T24a and the N ⁺ diffusion layer on the drain side of the driving transistor T23a,
The N ⁺ diffusion layer of the transfer transistor T21b on the side where the contact hole 242 is not provided is connected to the gate electrode 223 of the drive transistor T23b and the N ⁺ diffusion layer of the drain side of the drive transistor T24b. The N ⁺ diffusion layer on the side not provided is connected to the gate electrode 223 of the driving transistor T24b and the N ⁺ diffusion layer on the drain side of the driving transistor T23b (FIG. 11).

A ground wiring 233 made of an aluminum film is provided adjacent to and parallel to the left side of the bit line 231. The ground wiring 233 is connected to the second layer N ⁺ -type polycrystalline silicon films 225a and 225b through the contact holes 245.
Is electrically connected to Polycrystalline silicon film 225a
Is a driving transistor T23 through a contact hole 244.
a, are electrically connected to the N ⁺ diffusion layer on the source side of T24a. Similarly, the polycrystalline silicon film 225b is connected to the driving transistors T23b and T2 via the contact holes 244.
4b is electrically connected to the N ⁺ diffusion layer on the source side [FIG. 12].

A power supply line 234 made of an aluminum film is provided adjacent to and parallel to the left side of the ground line 233. Power supply wiring 234 is electrically connected to third N ⁺ -type polycrystalline silicon film 226 via contact hole 247. The polycrystalline silicon film 226 is connected to the second-layer high-resistance polycrystalline silicon film 227. The polycrystalline silicon film 227 is electrically connected to the gate electrodes 223 of the driving transistors T23a, T24a, T23b, T24b via the contact holes 246. The polycrystalline silicon film 227 functions as a load resistance of each drive transistor [FIG. 13]. Although not shown, memory cells are also arranged in a region adjacent to the left side of the power supply wiring 234.

As described above, the word lines 221 and 22 are located in the wiring region including the ground wiring 233 and the power supply wiring 234.
2. Although the polycrystalline silicon films 225a, 225b, and 226 are formed, the element formation region 211, the gate electrode 22
No 3 is formed. Therefore, the pattern continuity of the element formation region 211 and the gate electrode 223 is interrupted in the wiring region.

[0008]

In the above-mentioned conventional semiconductor memory device, the widths of various patterns in the portion where memory cells are continuously arranged have dimensions similar to the target values. However, in the area adjacent to the wiring area,
Due to a phenomenon called a loading effect, the width of the pattern is likely to deviate from a target value. At the stage where the photoresist film is developed with the developing solution in the portion adjacent to the wiring region, the width of the photoresist becomes large. On the other hand, when the etching is performed using the photoresist film as a mask, the width of the pattern of the element forming region, the gate electrode, and the like becomes narrower. At present, the phenomenon at the development stage is dominant.

If described in accordance with the conventional example, for example, the gate width and the gate length of the transistors T21a and T23a are larger than the gate width and the gate length of the transistors T22a and T24a. Regarding the transfer transistors T21a and T22a, the effect of the semiconductor element characteristics on the semiconductor memory device characteristics due to such a phenomenon is small. However, the driving transistor T23a,
Since T24a is flip-flop coupled, the effect of the difference in semiconductor element characteristics on the characteristics of the semiconductor memory device is large and significant. That is, there is a problem that inversion of stored data is likely to occur.

[0010]

In a semiconductor memory device according to the present invention, a pseudo memory cell (hereinafter, referred to as a dummy cell) is provided in a wiring region including a ground wiring and a power supply wiring. Preferably, the dummy cell has an electrical connection point with a ground wiring and a word line. Preferably, the pattern of the element formation region in the dummy cell is the same as the pattern of the element formation region in the memory cell. When a MOS transistor is included in an element forming the memory cell, the pattern of the gate electrode in the dummy cell is preferably the same as the pattern of the gate electrode in the memory cell.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 to 8 are diagrams for explaining a first embodiment of the present invention. This embodiment relates to a MOS SRAM in which a memory cell includes a pair of transfer transistors, a pair of drive transistors, and a pair of load resistors. FIG. 1 is a schematic plan view showing an arrangement of memory cells and dummy cells and a portion applied to a ground potential. FIG. 2 is a circuit diagram showing two bits of memory cells and two bits of dummy cells. FIG. 3 is a schematic plan view showing an electrical connection relationship between a memory cell and a pair of bit lines. FIG. 4 is a schematic plan view showing an electrical connection relationship between the memory cell and the dummy cell and the ground wiring. FIG. 5 is a schematic plan view showing the electrical connection between the memory cell and the power supply wiring. Figure 6
FIGS. 7 and 8 are cross-sectional views taken along line AA ′, line BB ′, and line BB ′ in FIGS. 1, 3, 4, and 5.

First, the arrangement of memory cells and dummy cells will be described with reference to FIGS. A pair of bit lines 13
Memory cells 101a and 101b are located below 1 and 132.
Are provided below the wiring area where the ground wiring 133 and the power supply wiring 134 are provided.
2b and the like are provided. The pair of bit lines 131 and 132 are in an opposite phase relationship. Bit lines 131, 132,
The ground wiring 133 and the power supply wiring 134 are provided in parallel, and the word lines 121 and 122 are provided substantially orthogonal thereto. The wiring area in which the ground wiring and the power supply wiring are provided is formed by providing a void in the memory cell every several bits in a direction parallel to the bit line. Although not shown, a region adjacent to the left side of the ground wiring 133 also
A memory cell is provided.

The memory cell 101a includes a pair of transfer transistors T11a and T12a and a pair of flip-flop coupled drive transistors T13a and T1.
4a and a pair of load resistors. Similarly, the memory cell 101b includes a pair of transfer transistors T11b and T12b and a pair of drive transistors T1
3b, T14b, and a pair of load resistors.
The dummy cell 102a includes pseudo transistors (hereinafter, referred to as dummy transistors) D11a, D12a, and D13.
a and D14a. Similarly, the dummy cell 102b includes dummy transistors D11b, D12
b, D13b, and D14b.

Referring to FIG. 1, FIG. 2, FIG. 4, and FIG. 6, portions of memory cells and dummy cells to which a ground potential has been applied (element forming region 111 and gate electrode 123 in FIG. Are applied to the ground potential).

A P well 1 is formed on the surface of the N-type silicon substrate 113.
14, a field oxide film 115 is provided on its surface.
, An element formation region 111 is formed. A gate oxide film 116 is provided on the surface of the element forming region 111. Field oxide film 115 and gate oxide film 116
On the upper side, word lines 121 and 122, a gate electrode 123, and a dummy gate electrode 124 made of a first layer N ⁺ type polycrystalline silicon film are provided. Element formation region 1
11, the word lines 121 and 122, the gate electrode 1
An N ⁺ diffusion layer 112 is formed in a region 23 that does not intersect with the dummy gate electrode 124.

The word line 121 and the N ⁺ diffusion layer 112 form transfer transistors T11a and T12a and dummy transistors D11a and D12a.
The word line 122 and the N ⁺ diffusion layer 112 form transfer transistors T11b and T12b and dummy transistors D11b and D12b. The driving transistor T is formed by the gate electrode 123 and the N ⁺ diffusion layer 112.
13a, T14a, T13b, and T14b are formed, and the dummy transistors D13a, D14a, D13b, and D14 are formed by the dummy gate electrode 124 and the N ⁺ diffusion layer 112.
b is formed. In this embodiment, for example, the pattern of the element formation region 111 and the dummy gate electrode 124 in the dummy cell 102a and the pattern of the element formation region 111 and the gate electrode 123 in the memory cell 101a are mirror-image-symmetric. Dummy cell 102
The pattern of the element formation region 111 and the pattern of the dummy gate electrode 124 in FIG. 5A are the same as the pattern of the element formation region 111 and the gate electrode 123 in the memory cell on the right of the memory cell 101a. Dummy cell 102b
A similar relationship holds between the memory cell 101b and the memory cell 101b.

The ground wiring 133 made of an aluminum film includes a dummy transistor D13a and a dummy transistor D1.
1a, the dummy transistor D11b, the dummy transistor D13b, and the like. Dummy cell 10
2a, the ground wiring 133 is connected to the contact hole 149.
Is electrically connected to the dummy gate electrode 124 of the dummy transistor D13a through the contact hole 148, and the dummy transistor D11a and the dummy transistor D
11b is connected to the N ⁺ diffusion layer 112 shared by the N ⁺ diffusion layer 112b.
Since the dummy transistor D13a has the direct contact hole 141 in the channel region, the dummy gate electrode 124 and the source and drain N ⁺ diffusion layers 112 are short-circuited and fixed to the ground potential.
N ⁺ diffusion layer 1 of drain of dummy transistor D14a
12, the dummy gate electrode 124 is fixed to the ground potential via the direct contact hole 141. Direct contact hole 141 of dummy transistor D13a, N ⁺ diffusion layer 11 of source of dummy transistor D13a
2. The N ⁺ -type polycrystalline silicon film 125a of the second layer is electrically connected to the ground wiring 133 via the contact hole 144. N ⁺ of the source of the dummy transistor D14a
Since diffusion layer 112 is electrically connected to polycrystalline silicon film 125a through contact hole 144, it is also fixed at the ground potential. The dummy cell 102b has the same configuration, and is connected to the ground wiring 133 by connecting a direct contact hole 141 provided in the channel region of the dummy transistor D13b, an N ⁺ -type polycrystalline silicon film 125b of the second layer, Contact hole 144, 1
49 are interposed.

In the memory cell 101a, the drive transistors T13a and T1 are provided by the interposition of the second layer N ⁺ type polycrystalline silicon film 125a and the contact hole 144.
The N ⁺ diffusion layer 112 of the source of 4a is electrically connected to the ground wiring 133. Similarly, in the memory cell 101b, the driving transistor T is formed by the interposition of the second layer N ⁺ type polycrystalline silicon film 125b and the contact hole 144.
The N ⁺ diffusion layers 112 of the sources of 13b and T14b are electrically connected to the ground wiring 133.

Next, the connection between the memory cell 101a and the bit lines 131 and 132 and the connection between the memory cell 101b and the bit lines 131 and 132 will be described with reference to FIGS. The bit lines 131 and 132 are made of an aluminum film. The bit line 131 is provided above the drive transistor T13a, the transfer transistor T11a, the transfer transistor T11b, and the drive transistor T13b, and the bit line 132 is provided above the drive transistor T14.
a, transfer transistor T12a, transfer transistor T12b, drive transistor T14b
It is provided on the upper part. The bit line 131 is connected to the transfer transistor T11a and the transfer transistor T11b via a contact hole 142 provided in the N ⁺ diffusion layer 112 shared by the transfer transistor T11a and the transfer transistor T11b.
And electrically connected to. Similarly, the bit line 132 is connected to the transfer transistor T12a and the transfer transistor T12 via a contact hole 143 provided in the N ⁺ diffusion layer 112 shared by the transfer transistor T12a and the transfer transistor T12b.
12b. Drive transistor T13
a, T14a is realized by the interposition of the direct contact hole 141.

Next, the connection between the memory cells 101a and 101b and the power supply wiring 134 will be described with reference to FIGS. The power supply wiring 134 is made of an aluminum film.
The power supply wiring 134 includes a dummy transistor D14a, a dummy transistor D12a, a dummy transistor D12b,
It is provided above the dummy transistor D14b and the like. Power supply wiring 134, dummy transistor D14a, dummy transistor D12a, dummy transistor D12
b, a dummy transistor D14b, etc., a third layer N ⁺ -type polycrystalline silicon film 126 is interposed. Power supply wiring 134 and polycrystalline silicon film 126 are electrically connected via contact hole 147. The polycrystalline silicon film 126 is connected to a third-layer high-resistance polycrystalline silicon film 127. The gate electrodes 123 of the driving transistors T13a, T14a, T13b, and T14b are connected to the polycrystalline silicon film 127 via the contact holes 146. The polycrystalline silicon film 127 functions as a load resistance of these drive transistors. Polycrystalline silicon film 127
The method for forming the film will be described. After depositing a third-layer high-resistance polycrystalline silicon film on the entire surface and patterning the same, a silicon nitride film 117 covering only the portion where the polycrystalline silicon film 127 is to be formed is deposited. Thereafter, N-type impurities are introduced only into portions not covered with the silicon nitride film 117 to form polycrystalline silicon films 126 and 127.

In the present embodiment, the pattern of the element formation region and the dummy gate electrode of the dummy cell provided under the wiring region is the same as the relationship between the pattern of the element formation region and the gate electrode pattern between right and left adjacent memory cells. In addition, since there is a mirror image relationship with the pattern of the element formation region and the gate electrode of the adjacent memory cell, the continuity of these patterns can be avoided. Therefore, the effect of the micro loading effect is reduced. Further, since the connection of the dummy transistors constituting the dummy cell is as described above, at least one terminal of each dummy transistor is fixed to the ground potential.

FIG. 9 and FIG. 10 are views for explaining a second embodiment of the present invention. FIG. 9A is a schematic plan view for explaining the present embodiment, and FIG. 9B is a circuit diagram for explaining the present embodiment. FIG. 10 is a cross-sectional view taken along line DD ′ in FIG.

In the present embodiment, as shown in FIG. 9, a memory cell includes a pair of load resistors and a pair of drive transistors T13.
c, T14c and a pair of transfer transistors T1
1c and T12c. The connection between the transistors is the same as in the first embodiment. Dummy cells are dummy transistors D11c, D12c, D13c,
D14c, and their connections are the same as in the first embodiment. The difference between the present embodiment and the first embodiment is that, as shown in FIGS.
This is in the method of connection with the N ⁺ type polycrystalline silicon film 125c. That is, the ground wiring 133 is
5, and is connected to the polycrystalline silicon film 125c. The polycrystalline silicon film 125c has a contact hole 144
Through the N ^{+ of the} dummy transistors D13c and D14c.
N ^{+ which} is connected to the diffusion layer 112 and becomes a source of the driving transistors T13c and T14c through the contact hole 144
It is connected to the diffusion layer 112. The circuit connection in the dummy cell is similar to that of the first embodiment.
A direct contact hole 141 is formed in the channel region 13c.
This is realized by providing

In this embodiment, since the number of intervening parts between the ground wiring 133 and the sources of the driving transistors T13c and T14c is smaller than that in the first embodiment, the contact resistance between the ground wiring and the memory cell is the first. Is reduced as compared with the embodiment of FIG.

The first and second embodiments are examples in which the present invention is applied to an SRAM using MOS transistors.
The present invention can be applied to other semiconductor memory devices, for example, DRAM, SRAM using bipolar transistors, SRAM using Bi-CMOS, mask ROM, non-volatile memory, and the like.

[0026]

As described above, in the semiconductor memory device of the present invention, a dummy cell having at least an element forming region having the same shape as that of a memory cell is provided below a wiring region including a ground wiring and a power supply wiring. In addition, it is possible to reduce the micro-loading effect in which the dimensions of the elements constituting the memory cell in the portion adjacent to the wiring region deviate from the target value. For example, in an SRAM constituted by MOS transistors, it is effective to prevent occurrence of inversion of stored data due to an increase in gate length and gate width of a driving transistor particularly in a portion adjacent to a wiring region, which has been conventionally seen.

[Brief description of the drawings]

FIG. 1 is a schematic plan view for explaining a first embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a first embodiment of the present invention.

FIG. 3 is a schematic plan view for explaining the first embodiment of the present invention.

FIG. 4 is a schematic plan view for explaining the first embodiment of the present invention.

FIG. 5 is a schematic plan view for explaining the first embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining the first embodiment of the present invention, which is taken along line AA ′ in FIGS. 1, 3, 4, and 5;
FIG.

FIG. 7 is a cross-sectional view for explaining the first embodiment of the present invention, which is taken along line BB ′ in FIGS. 1, 3, 4, and 5;
FIG.

FIG. 8 is a cross-sectional view for explaining the first embodiment of the present invention, which is taken along line CC ′ in FIGS. 1, 3, 4, and 5;
FIG.

FIGS. 9A and 9B are diagrams for explaining a second embodiment of the present invention. FIG. 9A is a schematic plan view, and FIG. 9B is a circuit diagram.

FIG. 10 is a cross-sectional view for explaining a second embodiment of the present invention, and is a cross-sectional view taken along line DD ′ in FIG. 9A.

FIG. 11 is a schematic plan view for explaining a conventional semiconductor memory device.

FIG. 12 is a schematic plan view for explaining a conventional semiconductor memory device.

FIG. 13 is a schematic plan view for explaining a conventional semiconductor memory device.

[Explanation of symbols]

101a, 101b, 101c, 201a, 201b
Memory cell 102a, 102b, 102c Dummy cell 111, 211 Element formation region 112 N ⁺ diffusion layer 113 N-type silicon substrate 114 P well 115 Field oxide film 116 Gate oxide film 117 Silicon nitride film 121, 122, 221, 222 Word line 123, 223 Gate electrode 124 Dummy gate electrode 125a, 125b, 125c, 126, 127, 22
5a, 225b, 226, 227 Polycrystalline silicon film 131, 132, 231, 232 Bit line 133, 233 Ground wiring 134, 234 Power supply wiring 141, 241 Director contact hole 142, 143, 144, 145, 146, 146, 1
47,148,149,242,243,244,24
5,246,247 Contact hole

Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/11 (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/8244 G11C 11/412 H01L 21/82 H01L 21 / 822 H01L 27/04 H01L 27/11

Claims (7)

(57) [Claims] A memory cell, bit lines, a ground wiring and a power supply wiring substantially parallel to the bit line, and a word line substantially orthogonal to the bit line are arranged in a lattice pattern. A semiconductor memory device in which a wiring area of the ground wiring and the power supply wiring is formed in a gap of the memory cell provided for every predetermined number of bits in a predetermined direction, a pseudo memory is provided in the wiring area of the ground wiring and the power supply wiring. A semiconductor memory device having cells. 2. The semiconductor memory device according to claim 1, wherein said pseudo memory cell has an electrical connection point with said ground wiring and said word line. 3. The semiconductor memory device according to claim 2, wherein one end of an element forming said pseudo memory cell has an electrical connection point with said ground wiring. 4. The semiconductor memory device according to claim 2, wherein the shape of the element forming region of said pseudo memory cell is substantially the same as the shape of the element forming region of said memory cell. 5. The semiconductor memory device according to claim 3, wherein the shape of the element forming region of the pseudo memory cell is substantially the same as the shape of the element forming region of the memory cell. 6. An element constituting the memory cell is a MOS.
5. The semiconductor memory device according to claim 4, wherein the shape of the gate electrode of the pseudo memory cell is substantially the same as the shape of the gate electrode of the memory cell. 7. An element constituting the memory cell is a MOS.
6. The semiconductor memory device according to claim 5, wherein the shape of the gate electrode of the pseudo memory cell is substantially the same as the shape of the gate electrode of the memory cell.