JP3200846B2 - Hybrid encoder - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an encoder for detecting a rotation angle by a digital signal.

[Prior Art] It is well known that there are an increment type and an absolute type as encoders for detecting a rotation angle of a rotating shaft with an n-bit digital signal.

That is, the increment type encoder includes a disk directly connected to the rotating shaft and having concentric slits formed at equal intervals, and a light emitting element and a light receiving element installed on both sides of the disk.

When the rotation shaft rotates, the disk also rotates, and the light receiving element outputs a number of pulses proportional to the rotation angle.

Therefore, it is possible to detect the rotation angle of the rotating shaft by counting the pulses with a counter.

However, in this type of encoder, since the absolute value of the rotation angle of the rotating shaft is held in the counter, information is lost when the power of the counter is turned off.

On the other hand, in the case of an absolute type encoder, a disk is provided directly connected to the rotating shaft and has a pattern of slits corresponding to each bit on concentric circles of the number corresponding to the number of bits. It has a light emitting element and a light receiving element installed.

When the rotation shaft rotates, the disk also rotates, and a logic signal corresponding to each bit is output from the light receiving element, so that the rotation angle of the rotation shaft can be directly known.

However, in the encoder of this type, if the detection accuracy is increased, the pattern formed on the disk becomes complicated, so that not only the size of the disk is increased, but also the cost is increased. If the rotation speed is further increased, the output signal of the lower bit has a relatively higher frequency, and thus erroneous detection occurs due to the influence of the frequency characteristics of the signal processing circuit.

In order to solve these problems, the upper m bits of the n-bit detection signal are detected by an absolute value,
A hybrid encoder that detects the lower (nm) bits by an increment value has been proposed (Japanese Patent Laid-Open No. 1-30).
No. 5316).

[Problems to be Solved by the Invention] However, in the hybrid encoder, since the lower bits use the increment value of the counter, if a count error occurs in the counter, it is output as a detection error as it is.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and has an object to generate a signal corresponding to one digit below the least significant digit (the (m + 1) th bit) of an m-bit absolute value represented by gray code formation. It is another object of the present invention to provide a hybrid encoder capable of forcibly correcting a counter value of a counter at the time of rising and falling of a timing generated based on a pattern further formed on a disk.

[Means for Solving the Problem] A configuration of a hybrid encoder for solving the above problem is shown in FIG.

High-order m bits (1 <m <n) of the n-bit digital signal value output as the detected value of the rotation angle of the rotation axis
The disk 100 having a pattern formed concentrically to output the number of pulses proportional to the rotation angle of the rotating shaft while outputting the rotation angle of the absolute value and reading the pattern formed on the disk 100 Reading means 101, signal processing means 102 for outputting the absolute value of the rotation angle read by the reading means 101 in a binary code, and counting means 103 for counting the pulses output from the reading means 101
And a pattern further formed on the disk 100 so as to generate a signal corresponding to the one digit below the least significant digit (the (m + 1) th bit) of the m-bit absolute value expressed in the gray code format. A timing signal generating means 104 for generating a timing signal, and two-phase pulses mutually shifted by a quarter period based on a pattern for outputting a number of pulses to the disk 100 in proportion to the rotation angle of the rotating shaft. And an increment value correction means (106) for calculating a correction value for calculating a correction value determined from the output of the timing signal generation means 104 and the output of the two-phase pulse generation means 105.

[Operation] In the hybrid encoder configured as described above, even if there is a pulse count error in the counter, the counter value of the counter is replaced with a correction value determined from the timing signal and the two-phase pulse at regular intervals. This prevents the output including the error from continuing for a predetermined period.

Embodiment An optical hybrid encoder which is an embodiment of the present invention will be described below with reference to the drawings.

This hybrid encoder has a rotation angle of 2 ¹⁵
= 32768 divisions and outputs a 15-bit digital signal. The upper 8 bits are detected as an absolute signal, and the lower 8 bits are detected as an increment signal.

Then, the absolute value and the increment value are combined using the least significant digit of the duplicated absolute value and the most significant digit of the increment value to obtain a 15-bit output.

2 and 3 are a side sectional view and an enlarged view of a Y part of the hybrid encoder according to this embodiment, which are housed in a housing 1 composed of a main body 11 and a cover 12. FIG.

A shaft 3 having a coupling 2 protrudes from the cover 12 at the outer end of the housing 1, and the shaft 3 is supported by a bearing 13 attached to the cover 12, and is coupled to the object whose rotation angle is to be measured. Connected via

A disk 4 is attached to the tip of the shaft 3 in the housing 1 and rotates together with the rotating shaft.

The disk 4 has an absolute pattern for outputting an absolute value of the rotation angle as described later,
An increment pattern for outputting a pulse corresponding to the rotation of the rotating shaft, and 1 of the least significant digit of an m-bit absolute value expressed in a gray code format for synthesizing an absolute signal and an increment signal
A timing signal generation pattern corresponding to the next lower digit (the (m + 1) th bit) is formed.

A plurality of light-emitting elements 5 and light-receiving elements 6 corresponding to the absolute pattern, the increment pattern, the timing signal generation pattern, and the light amount correction track are provided on both sides of the disk 4.

A fixed slit 7 is provided between the disk 4 and the light receiving element 6.
Is fixedly installed on the housing 1.

Further, a circuit board 8 on which an electronic circuit for executing signal processing described later is mounted is housed in the housing 1.

The output from the housing 1 of the hybrid encoder is transmitted via the cable 20 to the hybrid encoder conversion device 30.
Is transmitted to

FIG. 4 is a view showing a pattern formed on the disk 4.

That is, an increment pattern 41 composed of slits arranged at equal intervals is formed on the outermost periphery of the disk 4.

The fixed slit 7 is provided with two slits for one increment pattern 41. The light receiving element 6 corresponding to each slit is provided with two slits of A phase and B phase shifted from each other by a quarter period. One increment pulse is output.

A timing signal generation pattern 42 corresponding to the digit immediately below the least significant digit (the ninth digit) of the 8-bit absolute value expressed in the gray code format for synthesizing the absolute signal and the increment signal is provided inside thereof. It is formed.

Absolute signal generation patterns 44A-44H for generating an 8-bit rotation angle absolute signal are formed inside the first light quantity correction track 43A formed inside.

A second light quantity correction track 43B is also formed between the absolute signal generation patterns 44D and 44E.

In this embodiment, it is assumed that the absolute signal generation pattern is formed so as to output a digital signal represented by a gray code.

FIG. 5 is a diagram showing functions of a circuit board 8 housed in the housing 1 for signal processing and a hybrid encoder conversion device 30 connected to the circuit board 8 via a cable 20.

That is, in order to make the amount of light emitted from the light emitting element group 5 constant on the circuit board 8, the amount of light passing through the two light amount correction tracks 43A and 43B is detected by the corresponding light receiving element in the light receiving element group 6, and the light emitting element A light amount correction function 81 for adjusting the amount of light emitted from the five groups, an amplifier function 82 for amplifying a signal received by the light receiving element group 6, a parallel-serial for converting an 8-bit parallel signal detected by an absolute pattern into a serial signal Line driver receiver function 84 for adjusting the state of signals transmitted to and received from hybrid encoder conversion function 30 via signal conversion function 83 and cable 20
Is included.

The hybrid encoder conversion device 30 includes a cable 20
, A line driver receiver function 301 for adjusting the state of a signal transmitted to and received from the circuit board 8 via the interface, a serial-parallel signal conversion function 302 for converting an absolute signal transmitted in a serial signal format into a parallel signal, an increment pattern Counting the pulses detected by the above and rising of the timing signal according to the present invention,
Alternatively, an increment counter 303 that reads a correction value at the time of falling, an increment value latch function 304 for latching the output of the counter 303, and a rotation expressed in an 8-bit parallel gray code format output from the serial-parallel signal conversion function 302. The absolute value of the angle is converted to an absolute value represented by an 8-bit parallel binary code, and the absolute value other than the least significant digit of the absolute value is determined by the most significant digit of the increment value detected overlapping with the least significant digit of the absolute value Data processing function 305 for correcting the value, data latch function 306 for latching the 15-bit absolute value of the rotation angle as the final output, and serial-parallel signal conversion function 302, increment value latch function 304, and data latch Control function 306 Control signal generating function 307
Is included.

The control signal is transmitted from the terminal 211 to the terminal 201 via the cable 20, the absolute value converted into a serial signal is transmitted from the terminal 202 to the terminal 212, and the timing signal is transmitted to the terminal 20.
From 3 to terminal 213, the two-phase increment pulse is applied to terminal 20.
3 and 204 to the terminals 213 and 214 respectively.

As the increment pulse, two pulses (A-phase pulse and B-phase pulse) shifted by a quarter period from each other are used to determine the rotation direction.

Further, the timing signal is a pattern further formed on the disk 100 so as to generate a signal corresponding to the next lower digit (the (m + 1) th bit) of the m-bit absolute value expressed in the gray code format. Generated based on

FIG. 6 is a functional diagram for correcting the increment value according to the present invention, and FIG. 7 is a timing diagram for correcting the increment value.

FIG. 8 shows a truth table for determining the correction value of the increment value according to the present invention.

That is, in the present invention, the increment counter 303
Is a correction timing signal generator 3031 that generates a correction value read signal to the up / down counter 3034 at the time of rising and falling of the timing signal, and determines the rotation direction from the A-phase pulse and the B-phase pulse. A normal / reverse discrimination unit 3032 that outputs a logic signal “0” and outputs a logic signal “1” if the rotation direction is a reverse direction, and an exclusive OR operation unit that calculates the exclusive OR of the A-phase pulse and the B-phase pulse 3033,
For example, the B-phase pulse counts up when the output of the forward / reverse determining unit 3032 is a logical signal “0”, counts down when the output is a logical signal “1”, and generates a correction timing signal.
The initial value read signal from 3031 digits of output 2 ⁰ of exclusive-OR operation unit 3033 each time it is generated, the B-phase pulse 2 ¹ digit, the output of the normal rotation reverse rotation determination section 3032 2 ² 2 to ⁶ digits,
Composed timing signals digit 2 ^7, the up-down counter 3034 to read as respective initial values.

The timing signal is generated as a waveform having the same period as the eighth digit of the absolute value of the 8-bit rotation angle expressed in the binary code format and a quarter-phase advanced waveform. Since it is adjusted so as to rise or fall during one cycle of the two-phase pulse, it is possible to determine the absolute value of the increment value of the rotation angle from the timing signal and the two-phase pulse when the timing signal rises or falls. It becomes possible.

That is, the timing signal is
Becomes 2 ⁷ digits, the output of the normal rotation reverse rotation determination section 3032 is set from 2 ⁶ digits of the up-down counter 3034 to 2 ² digits.

One of the four types of values determined from the increment pulses 2 phase shift of a quarter period phase is output correction timing signal for 2 ¹ digit and 2 ⁰ digit of the up-down counter 3034 Is set in accordance with the timing of

For example the count miss occurs as shown in the timing diagram of Figure 7A at time t ₁ in the forward rotation, A-phase pulse at time t ₂ is the logic signal "1" B-phase pulses to the state of the logic signal "0" There, the correction timing signal rises to "1" from a logic signal "0", the logic signal "1" to 2 ⁷ digit of the up-down counter 3034 according to the sixth digit of the truth table of Figure 9, 2 ⁶ logic signal to the 2 ² digits from the digit "0", 2 ¹ of a logic signal "0" for the figures, in the 2 ⁰ digit is included in the room rate readings logic signal "1", the up-down counter Output is "1, 0, 0, 0, 0, 0, 0,
Corrected to 1 ".

FIG. 9 shows the A-phase B-phase pulse and the timing signal detection waveform,
FIG. 4 is a waveform diagram illustrating a waveform of a correction timing signal.

In other words, the correction timing signal generator that generates the correction timing signal from the timing signal may be adjusted so that the correction timing signal rises or falls somewhere in one cycle of the A-phase and B-phase pulses whose waveforms are shaped. Therefore, the adjustment accuracy does not need to be high, and the rising and falling hysteresis can be made large, and a large noise margin can be obtained.

[Effect of the Invention] According to the present invention, even if a count error occurs in the increment counter, the value of the counter is corrected at regular intervals, so that accumulation of errors in the counter can be prevented.

The rising and falling edges of the timing signal waveform directly read from the disk may be gentler than those of the two-phase pulse, and the pattern can be produced with a high degree of precision or is economically advantageous.

Further, since the correction timing signal generator may set the threshold value so that the correction timing signal rises or falls during one cycle of the two-phase pulse, not only the adjustment is easy but also a large noise margin can be taken. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention, FIG. 2 is a side sectional view of a hybrid encoder according to the present invention, FIG. 3 is an enlarged view of a Y portion of the hybrid encoder according to the present invention, and FIG. FIG. 5 is a diagram schematically illustrating a pattern of a disk included in an encoder housing, FIG. 5 is a diagram illustrating a circuit board included in a hybrid encoder housing and a signal processing function of a hybrid encoder converter, and FIG. FIG. 7 is a functional diagram for correcting an increment value, FIG. 7 is a timing chart of an operation for correcting an increment value according to the present invention, FIG. 8 is a truth table for determining a corrected value of the increment value according to the present invention, FIG. 9 is a waveform diagram showing the waveform of each signal. In the figure, 100 ... disk, 101 ... reading means, 102 ... signal processing means, 103 ... counting means, 104 ... timing signal generating means, 105 ... two-phase pulse generating means, 106 ... increment value correction means.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-305316 (JP, A) JP-A-1-305317 (JP, A) JP-A-1-153910 (JP, A) JP-A-63- 117214 (JP, A) JP-A-1-23107 (JP, A) JP-A-1-79619 (JP, A) JP-A-1-305314 (JP, A) (58) Fields investigated (Int. ^7, DB name) G01D 5/245 G01D 5/249 G01D 5/36

Claims (1)

(57) [Claims] An upper m bits (1) of an n-bit digital signal value output as a detection value of a rotation angle of a rotation axis.
A disk (100) having a concentric pattern to output a rotation angle of <m <n) as an absolute value and to output a number of pulses proportional to the rotation angle of the rotation shaft; Reading means (101) for reading a pattern formed thereon; signal processing means (102) for outputting an absolute value of the rotation angle read by the reading means (101) in a binary code; A counting means (103) for counting the pulses output from the reading means (101), one of the least significant digits of the m-bit absolute value expressed in Gray code format Based on the pattern further formed on the disc (100) so as to generate a signal corresponding to the lower digit (the (m + 1) th bit) A timing signal generating means (104) for generating a timing signal in accordance with a pattern for outputting a number of pulses proportional to the rotation angle of a rotating shaft formed on the disk (100). A two-phase pulse generating means (105) for generating two-phase pulses having a shifted periodic phase; a correction value determined from an output of the timing signal generating means (104) and an output of the two-phase pulse generating means (105); A hybrid encoder comprising an increment value correcting means (106) for calculating.