JP3200022B2 - Design method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit for efficiently performing a circuit failure check by scanning in and out.

[0002]

2. Description of the Related Art To perform a scan test as a failure test of a semiconductor integrated circuit, a scan chain is formed by connecting scan registers, which are storage elements having a scan test function, to each other. Inside, it is necessary to design a semiconductor integrated circuit so as to function as a shift register.

[0003] In the operation of connecting two scan registers in the process of connecting the scan registers to each other to form a scan chain, if the preceding scan register has two output terminals of positive logic and inverted logic, it is conventionally used. One of the conventional methods is to always connect only the positive logic output terminal of the preceding scan register to the scan data input terminal of the subsequent scan register, or always connect only the inverted logic output terminal of the preceding scan register to the subsequent scan register. There is a method of connecting to the scan data input terminal of the register.

As another conventional method, when one of the two output terminals of positive logic and inverted logic of the preceding scan register is not connected, the unconnected output terminal is scanned by the subsequent scan register. If the two output terminals are all connected to other elements, the positive logic output terminal or the inverted logic output terminal is always connected to the scan data input terminal of the subsequent scan register. There is a way.

Hereinafter, a conventional method for designing a semiconductor integrated circuit device will be described with reference to the drawings.

FIG. 20 is a circuit diagram showing a scan register. 20, reference numeral 10 denotes a scan register for performing a failure test by a scan method, 11 denotes a data input terminal to which data during normal operation is input, 12 denotes a scan data input terminal to which scan data in a scan operation mode is input, 13 is a clock input terminal for synchronizing the scan register 10, 14 is an input switching terminal for inputting a signal for switching between the normal mode and the scan operation mode,
Reference numeral 15 denotes a positive logic output terminal that outputs data having the same value as the data input to the data input terminal 11 or the scan data input terminal 12, and 16 denotes a value obtained by inverting the data input to the data input terminal 11 or the scan data input terminal 12. Is an inverted logic output terminal that outputs the data of When "0" and "1" are input to the input terminal 14, the scan register 10 synchronizes the data input to the data input terminal 11 and the scan data input terminal 12 with the positive logic output terminal 15 in synchronization with the clock signal. At the same time, a signal obtained by inverting the signal of the positive logic output terminal 15 is output to the inverted logic output terminal 16.

Hereinafter, for the sake of convenience, a scan register 10 used in each drawing has a scan data input terminal 12 of SI, a positive logic output terminal 15 of Q, and an inverted logic output terminal 1 of Q.
6 as NQ, these scan data input terminals SI,
Only the positive logic output terminal Q and the inverted logic output terminal NQ will be displayed.

FIG. 25 is a flowchart showing a wiring process in a conventional method for designing a semiconductor integrated circuit. FIG.
In SZ1, SZ1 designates a connection order of scan registers, SZ2 selects a pair of scan registers adjacent to each other as a scan chain, and SZ3 determines whether there is an unconnected output terminal in the scan register. Step SZ4 is a step of selecting a positive logic output terminal when there is no unconnected output terminal. Step SZ5 is a step of selecting an unconnected output terminal when there is an unconnected output terminal. Step SZ6 is selected. Connecting an output terminal and a scan data input terminal of a subsequent scan register,
SZ7 indicates a step of determining whether or not processing has been completed for all pairs of scan registers in the scan chain.

FIG. 21 is a circuit diagram showing a semiconductor integrated circuit before wiring scan registers. In FIG. 21, reference numeral 20B denotes a formation area for forming a semiconductor integrated circuit before generation of a scan chain; 21 to 25, scan registers constituting a shift register during a scan test;
Reference numeral 2 denotes an AND gate that outputs "1" only when both input signals are "1", inverters 33 to 35 output an inverted signal of the input signal, and 36 inputs a scan test signal. A scan-in terminal 37 is a scan-out terminal for outputting a scan test signal.
The inverted logic output terminal NQ of the scan register 22 and the positive logic output terminal Q of the scan register 25 are not used in the normal operation mode and are not connected.

FIG. 26 is a circuit diagram showing the semiconductor integrated circuit shown in FIG. 21 subjected to the arrangement and wiring processing shown in FIG. In FIG. 26, reference numeral 20A denotes an arrangement / wiring area for arranging the semiconductor integrated circuit after the generation of the scan chain, and the position and size of each element and wiring reflect actual hardware. 21 to 37 are denoted by the same reference numerals as the components shown in FIG. 41Z is a wire connecting the scan register 21 and the scan register 22; 42Z is a wire connecting the scan register 22 and the scan register 23; 43Z is a scan register 23
44Z is a line connecting the scan register 24 and the scan register 25, and 45Z is a line connecting the scan register 25 and the scan-out terminal 37.

A process in which scan registers are wired by sequentially performing the steps shown in FIG. 25 on the semiconductor integrated circuit before the scan chain generation shown in FIG. 21 will be described. First, in step SZ1, the connection order of each scan register is changed to scan register 21, scan register 22, scan register 23, scan register 24, scan register 25, and scan out terminal 37.
Specify to connect in order.

Next, in step SZ2, the first pair of the scan register 21 and the scan register 22 is selected.

Next, in step SZ3, the positive logic output terminal Q or the inverted logic output terminal NQ of the scan register 21
It is determined whether or not there is an unconnected terminal. Since there is no unconnected terminal, the process proceeds to step SZ4.

Next, after selecting the positive logic output terminal Q in step SZ4, in the next step SZ6, the selected positive logic output terminal Q and the scan data input terminal SI of the scan register 22 are connected by the wiring 41Z. .

Next, in step SZ7, since another pair of scan registers remains, the process returns to step SZ2.

Next, in step SZ2, a pair of the scan register 22 and the scan register 23 is selected, and
In the next step SZ3, since the inverted logic output terminal NQ of the scan register 22 is not connected, the process proceeds to step SZ5 to select the inverted logic output terminal NQ.

Next, in step SZ6, the selected inverted logic output terminal NQ and the scan data input terminal SI of the scan register 23 are connected by the wiring 42Z.

The same processing is performed on the remaining pairs of scan registers, and the positive logic output terminal Q of the scan register 23 and the scan data input terminal SI of the scan register 24 are connected by the wiring 43Z. Wiring 4
4Z connects the positive logic output terminal Q of the scan register 24 to the scan data input terminal SI of the scan register 25, and furthermore, the wiring 45Z connects the positive logic output terminal Q of the scan register 25 and the scan data input of the scan out terminal 37. The scan chain connection is completed by connecting the terminal SI.

[0019]

However, in the conventional method of designing a semiconductor integrated circuit, for example, the inverted logic output terminal NQ of the scan register 22 and the scan data input terminal SI of the scan register 23 shown in FIG. Is provided, the scan register 2
2 between the inverted logic output terminal NQ of the scan register 22 and the scan data input terminal SI of the scan register
Since the line 42Z is longer than the linear distance from the scan data input terminal SI, the line 42Z is longer than the line connecting the positive logic output terminal Q of the scan register 22 and the scan data input terminal SI of the scan register 23. There is a problem that the amount of wiring is increased.

Although the positive logic output terminal Q of the scan register 24 is connected to more elements than the inverted logic output terminal NQ, the connection between the scan register 24 and the scan register 25 does not take the fanout number into account. Since the positive logic output terminal Q of the scan register 24 is uniquely used, the load applied to the positive logic output terminal Q is further increased. However, there is a problem that the delay of the signal with respect to is significantly increased.

Furthermore, for example, one cycle time of the clock signal at the positive logic output terminal Q of the scan register 24 and the propagation of the signal along the path from the output terminal of the scan register 24 to the scan data input terminal SI of the scan register 25 When the design margin, which is the difference from the time, is very small, connecting the positive logic output terminal Q to the scan register 25 further reduces the design margin of the positive logic output terminal Q, so that signal propagation is within one clock. There was a possibility that a timing problem of not being able to fit in would occur.

In the above-described conventional method for designing a semiconductor integrated circuit, the time required for a clock signal to reach a clock input terminal of each scan register varies (= time skew).
However, there is a problem that a malfunction occurs when there is an error. Hereinafter, this problem will be described with reference to the drawings.

In FIG. 26, a macro cell A is used as a scan register 22, and scan registers 23 and 24 are used.
Assume that a macro cell B is used. Macrocell A
And the macro cell B are logically scan registers shown in FIG. The macro cell A has a delay value of 3 ns and 1 ns, respectively, of the signal input from the SI terminal to the Q terminal or the NQ terminal, and the macro cell B has a delay value of the signal input from the SI terminal to the Q terminal or the NQ terminal. They are 1 ns and 3 ns, respectively. Here, for the sake of convenience, the description will be made assuming that each wiring has no delay.

FIGS. 27 and 28 are timing charts showing signal changes at the terminals of scan registers 22, 23 and 24 in the circuit diagram according to the conventional semiconductor integrated circuit design method shown in FIG. 22. SI is the scan register 22
Of the scan data input terminal SI of FIG.
2. CK, 23. CK and 24. CK represents a signal change at the clock input terminals of the scan registers 22, 23, and 24, respectively. NQ, 23. NQ and 24. NQ indicates a signal change at the inverted logic output terminal NQ of each of the scan registers 22, 23, and 24. Q, 23. Q
And 24. Q represents scan registers 22, 23, respectively.
24 indicates a signal change of the 24 positive logic output terminals Q.

FIG. 27 is a timing chart in an ideal case where there is no variation in the time when the clock signal reaches the clock input terminals of the scan registers 22 to 24. Scan data input terminal 22. It is assumed that 1 → 0 → 1 is input to SI in synchronization with the clock signal from the Q terminal of the scan data 21 in the preceding stage. The NQ terminal of the scan register 22, the Q terminal of the scan register 23, and the Q terminal of the scan register 24
As for the terminal signal, data taken in with a delay of 1 ns after the input of each clock signal is output to the SI terminal of the subsequent scan register. Therefore, the input data is stored in the scan registers 22 and 2 for each clock signal.
3 and 24. After three clock cycles, the NQ terminal of the scan register 22 and the Q
The signals at the terminal and the Q terminal of the scan register 24 are 0, 1, 0, respectively.

FIG. 28 is a timing chart showing a case where the time when the clock signal reaches the scan register 23 is delayed by 2 ns from the time when the clock signal reaches the scan registers 22 and 24. At this time, the clock signal of the scan register 23 is input 1 ns later than the signal change of the signal input to the SI terminal of the scan register 23. It takes in a new signal that is the next signal after the signal. Therefore, the NQ terminal of the scan register 22 and the scan register 23 after three clock cycles
Since the signals at the Q terminal of the scan register 24 and the Q terminal of the scan register 24 are 0, 0, and 1, respectively, they differ from the expected values obtained in the ideal case of FIG. 27, and a malfunction occurs.

The first object of the present invention is to solve the above-mentioned conventional problem, and it is a first object of the present invention to prevent an increase in the amount of wiring when performing scan chain connection of a semiconductor integrated circuit. A second object is to prevent an increase in the number of clock signals, and a third object is to prevent the data from being destroyed due to variations in clock signals.

[0028]

[Means for Solving the Problems]

[0029]

[0030]

[0031]

The first aspect of the present invention achieves the first and second objects, and has a first aspect having a plurality of output terminals.
Design of a semiconductor integrated circuit for connecting one output terminal of the plurality of output terminals in the storage element of the first embodiment with the scan data input terminal of a second storage element having a scan data input terminal and having a scan test function. The output terminal of the first storage element and the second terminal.
A distance calculation step of calculating a linear distance on the substrate between the scan data input terminal of the storage element and a minimum value of the linear distance, and comparing the minimum value with a linear distance other than the minimum value Performing the distance comparison step, and the difference between the minimum value and a linear distance other than the minimum value is equal to or less than a predetermined value .
When there is an output terminal of the storage element, the difference between the output terminal of the first storage element that minimizes the linear distance and the minimum value of the linear distance is equal to or less than a predetermined value. A calculating step of calculating the number of fan-outs with the output terminal of the first storage element; and the output terminal having the minimum number of fan-outs among the output terminals of the first storage element calculated in the calculating step Is the scan data of the second storage element.
The minimum value and the maximum value.
The first method in which a difference from a linear distance other than a small value is equal to or less than a predetermined value.
When there is no output terminal of the storage element of
The smaller output terminal of the first storage element is connected to the second storage element.
Determine the terminal to connect to the scan data input terminal of the storage device
And a connection step of connecting the determined terminal to a scan data input terminal of the second storage element.

[0033] The arrangement of claim 1, the output of the first storage element and the output terminal of the first storage element linear distance on the substrate is minimized, the difference between the minimum value of the linear distance equal to or less than a predetermined value The number of fan-outs with the terminal is calculated, and among the calculated output terminals of the first storage element, the output terminal with the smallest number of fan-outs and the scan data input terminal of the second storage element are connected. Therefore, the wiring between the first and second storage elements is shortened, and an increase in the load capacitance of the circuit in the normal operation mode is avoided.

According to a second aspect of the present invention, the first and second objects are achieved, and a first type having a plurality of output terminals is provided.
Design of a semiconductor integrated circuit for connecting one output terminal of the plurality of output terminals in the storage element of the first embodiment with the scan data input terminal of a second storage element having a scan data input terminal and having a scan test function. The output terminal of the first storage element and the second terminal.
A distance calculation step of calculating a linear distance on the substrate between the scan data input terminal of the storage element and a minimum value of the linear distance, and comparing the minimum value with a linear distance other than the minimum value Performing the distance comparison step, and the difference between the minimum value and a linear distance other than the minimum value is equal to or less than a predetermined value .
When there is an output terminal of the storage element, the difference between the output terminal of the first storage element that minimizes the linear distance and the minimum value of the linear distance is equal to or less than a predetermined value. a capacity calculation step of calculating the load capacity with respect to the output terminal of the first memory element respectively, among the output terminals of said calculated in the capacity calculating step first memory element, said output terminal of said load capacitance is minimum Scan data of the second storage element
The minimum value and the maximum value.
The first method in which a difference from a linear distance other than a small value is equal to or less than a predetermined value.
When there is no output terminal of the storage element of
The smaller output terminal of the first storage element is connected to the second storage element.
Determine the terminal to connect to the scan data input terminal of the storage device
And a connection step of connecting the determined terminal to a scan data input terminal of the second storage element.

According to the second aspect of the present invention, the difference between the output terminal of the first storage element that minimizes the linear distance on the substrate and the minimum value of the linear distance is equal to or less than a predetermined value. , And the output terminal of the calculated first storage element having the minimum load capacity is connected to the scan data input terminal of the second storage element. In addition, the wiring between the second storage elements is shortened, and an increase in the load capacitance of the circuit in the normal operation mode is avoided.

[0036]

[0037]

According to a third aspect of the present invention, the first and second objects are achieved, and a first type having a plurality of output terminals is provided.
Design of a semiconductor integrated circuit for connecting one output terminal of the plurality of output terminals in the storage element of the first embodiment with the scan data input terminal of a second storage element having a scan data input terminal and having a scan test function. The output terminal of the first storage element and the second terminal.
A distance calculation step of calculating a wiring distance when the scan data input terminal of the storage element is wired, and determining a minimum value of the wiring distance, and calculating the minimum value and a wiring distance other than the minimum value. A distance comparison step for comparison, before the difference between the minimum value and a wiring distance other than the minimum value becomes equal to or less than a predetermined value.
In the case where there is an output terminal of the first storage element, the difference between the output terminal of the first storage element that minimizes the wiring distance and the minimum value of the wiring distance is equal to or less than a predetermined value. wherein the calculation step of the output terminal and the fan-out number calculating respective storage elements, among the output terminals of said first memory element calculated in the calculating step, the output terminal of the fan-out number is the smallest Scan of the second storage element
Terminal connected to the data input terminal
Before the difference between the distance and the wiring distance other than the minimum value becomes equal to or less than a predetermined value.
If there is no output terminal of the first storage element, the wiring distance
The output terminal of the first storage element with the minimum separation is
Terminal connected to the scan data input terminal of the second storage element
And a connection step of connecting the determined terminal and the scan data input terminal of the second storage element.

According to the third aspect of the present invention, the output terminal of the first storage element where the actual wiring distance is the minimum and the output terminal of the first storage element where the difference between the minimum value of the wiring distance and the minimum value are equal to or less than a predetermined value. Is calculated, and the output terminal of the calculated first storage element having the smallest fan-out number is connected to the scan data input terminal of the second storage element. In addition, the wiring between the first and second storage elements is reliably reduced, and an increase in the load capacitance of the circuit in the normal operation mode is avoided.

According to a fourth aspect of the present invention, the first and second objects are achieved, and a first type having a plurality of output terminals is provided.
Design of a semiconductor integrated circuit for connecting one output terminal of the plurality of output terminals in the storage element of the first embodiment with the scan data input terminal of a second storage element having a scan data input terminal and having a scan test function. The output terminal of the first storage element and the second terminal.
A distance calculation step of calculating a wiring distance when the scan data input terminal of the storage element is wired, and determining a minimum value of the wiring distance, and calculating the minimum value and a wiring distance other than the minimum value. A distance comparison step for comparison, before the difference between the minimum value and a wiring distance other than the minimum value becomes equal to or less than a predetermined value.
In the case where there is an output terminal of the first storage element, the difference between the output terminal of the first storage element that minimizes the wiring distance and the minimum value of the wiring distance is equal to or less than a predetermined value. A capacitance calculating step of calculating load capacitances with respect to an output terminal of the storage element, and among the output terminals of the first storage element calculated in the capacitance calculating step, the output terminal having the minimum load capacitance is set to the output terminal . Scanning of the second storage element
Terminal to be connected to the scan data input terminal.
The difference between the value and the wiring distance other than the minimum value is equal to or less than a predetermined value.
When there is no output terminal of the first storage element, the wiring
The output terminal of the first storage element whose distance is minimized is
An end connected to the scan data input terminal of the second storage element
And a connection step of connecting the determined terminal to the scan data input terminal of the second storage element.

According to the fourth aspect of the present invention, the difference between the output terminal of the first storage element at which the actual wiring distance is the minimum and the output terminal of the first storage element at which the difference between the minimum value of the wiring distance and the minimum value is equal to or smaller than a predetermined value is obtained. Calculate the load capacity and calculate the first
Of the output terminals of the storage element, the output terminal with the smallest load capacitance is connected to the scan data input terminal of the second storage element, so that the wiring between the first and second storage elements is reliably reduced. At the same time, an increase in the load capacity of the circuit in the normal operation mode is avoided.

According to a fifth aspect of the present invention, there is provided the second object, wherein one of the plurality of output terminals in the first storage element having a plurality of output terminals is connected to a scan data input terminal. The present invention is directed to a method of designing a semiconductor integrated circuit for connecting a scan data input terminal of a second storage element having a terminal and a scan test function, wherein the number of fan-outs of each output terminal of the first storage element is determined. A calculating step of calculating, among the output terminals of the first storage element, an output terminal of the first storage element that minimizes the fan-out number, and a scan data input terminal of the second storage element. And a connecting step of connecting.

According to the fifth aspect of the present invention, among the output terminals of the first storage element, the output terminal of the first storage element with the minimum fan-out number is connected to the scan data input terminal of the second storage element. Therefore, an increase in the load capacitance of the circuit in the normal operation mode is avoided.

A sixth aspect of the present invention achieves the first and second objects and has a first aspect having a plurality of output terminals.
Design of a semiconductor integrated circuit for connecting one output terminal of the plurality of output terminals in the storage element of the first embodiment with the scan data input terminal of a second storage element having a scan data input terminal and having a scan test function. A calculating step of calculating a fan-out number of each output terminal of the first storage element; and obtaining a minimum value of the fan-out number, and determining the minimum value and the fan numbers other than the minimum value. A comparing step of comparing the number of outs with the number of outs, and an output terminal of the first storage element in which a difference between the minimum value of the number of the fan outs and the number of fan outs other than the minimum is equal to or less than a predetermined value. The first fanout number,
A straight line on the substrate between the output terminal of the first storage element and the scan data input terminal of the second storage element, wherein the difference between the output terminal of the storage element and the minimum value of the number of fan-outs is equal to or less than a predetermined value. A distance calculation step of calculating distances,
Among the output terminals of the first storage element calculated in the distance calculation step, the output terminal with the minimum linear distance is set as the scan data input terminal of the second storage element.
Determine the terminal to be connected, the minimum value of the number of fan-out and
The difference between the fan-out number other than the minimum value and the
If there is no output terminal of the first storage element,
An output terminal of the first storage element having a small fan-out number
To the scan data input terminal of the second storage element.
And a connection step of connecting the determined terminal to the scan data input terminal of the second storage element.

According to the configuration of claim 6 , the output terminal of the first storage element which has the minimum fan-out number and the output terminal of the first storage element whose difference from the minimum value of the fan-out number is equal to or less than a predetermined value. And calculating a linear distance on the substrate between the scan data input terminal of the second storage element and the output terminal of the calculated first storage element having the minimum linear distance and the second storage element. Since the scan data input terminal of the element is connected, the wiring between the first and second storage elements is reduced, and the increase in the load capacitance of the circuit in the normal operation mode is avoided.

The invention according to claim 7 achieves the first and second objects, and has a first structure having a plurality of output terminals.
Design of a semiconductor integrated circuit for connecting one output terminal of the plurality of output terminals in the storage element of the first embodiment with the scan data input terminal of a second storage element having a scan data input terminal and having a scan test function. A calculating step of calculating a fan-out number of each output terminal of the first storage element; and obtaining a minimum value of the fan-out number, and determining the minimum value and the fan numbers other than the minimum value. A comparing step of comparing the number of outs with the number of outs, and an output terminal of the first storage element in which a difference between the minimum value of the number of the fan outs and the number of fan outs other than the minimum is equal to or less than a predetermined value. The first fanout number,
In the case where the output terminal of the first storage element and the scan data input terminal of the second storage element whose difference between the output terminal of the storage element and the minimum value of the fan-out number is equal to or less than a predetermined value are connected. A distance calculation step of calculating a wiring distance, and among the output terminals of the first storage element calculated in the distance calculation step, the output terminal with the minimum wiring distance is set to the scan data of the second storage element. input
Determine the terminal to be connected to the terminal, and
The difference between the small value and the number of fanouts other than the minimum value is equal to or less than the predetermined value.
In the case where there is no output terminal of the lower first storage element,
The first storage element having the minimum fan-out number
An output terminal is a scan data input terminal of the second storage element.
And a connection step of connecting the determined terminal to the scan data input terminal of the second storage element.

According to the structure of claim 7 , the output terminal of the first storage element which has the minimum fan-out number and the output terminal of the first storage element whose difference from the minimum value of the fan-out number is equal to or less than a predetermined value. An actual wiring distance between the first storage element and the scan data input terminal of the second storage element is calculated, and among the calculated output terminals of the first storage element, an output terminal with the shortest wiring distance and a second storage element Is connected to the scan data input terminal, the wiring between the first and second storage elements is reliably reduced, and an increase in the load capacitance of the circuit in the normal operation mode is avoided.

[0048]

[0049]

An eighth aspect of the present invention achieves the second object, wherein one of the plurality of output terminals in the first storage element having a plurality of output terminals is connected to a scan data input terminal. A load capacitance for each output terminal of the first storage element is calculated for a method of designing a semiconductor integrated circuit connecting the scan data input terminal of the second storage element having a terminal and having a scan test function. Connecting the output terminal of the first storage element having the minimum load capacity among the output terminals of the first storage element to the scan data input terminal of the second storage element. And a connecting step to perform the connection.

According to the eighth aspect of the present invention, among the output terminals of the first storage element, the output terminal of the first storage element having the minimum load capacitance is connected to the scan data input terminal of the second storage element. Therefore, an increase in the load capacity of the circuit in the normal operation mode is avoided.

According to a ninth aspect of the present invention, the first and second objects are achieved, and a first aspect having a plurality of output terminals is provided.
Design of a semiconductor integrated circuit for connecting one output terminal of the plurality of output terminals in the storage element of the first embodiment with the scan data input terminal of a second storage element having a scan data input terminal and having a scan test function. A capacitance calculating step of calculating a load capacitance for each output terminal of the first storage element, obtaining a minimum value of the load capacitances, and determining the minimum value and a load capacitance other than the minimum value. a capacity comparing step of comparing the bets, the difference between the load capacity of the non-minimum and outermost minimum value of the load capacitance and the predetermined value or less
When there is an output terminal of the first storage element, the difference between the output terminal of the first storage element that becomes the minimum load capacitance and the minimum value of the load capacitance becomes equal to or less than a predetermined value. Calculating a linear distance between the output terminal of the storage element and the scan data input terminal of the second storage element on the substrate, and the output terminal of the first storage element calculated in the distance calculation step And the output terminal having the minimum linear distance is connected to the second storage element.
Determine the terminal to be connected to the can data input terminal,
The difference between the minimum value of the load capacity and the load capacity other than the minimum value is determined.
When there is no output terminal of the first storage element that is less than or equal to the value
Is the output of the first storage element having the minimum load capacity.
Input terminal is a scan data input terminal of the second storage element.
And the determined terminal is connected to the second terminal .
And a connection step of connecting the storage element to the scan data input terminal.

According to a ninth aspect of the present invention, the output terminal of the first storage element having the minimum load capacitance and the output terminal of the first storage element having a difference between the minimum value of the load capacitance and the output terminal of the first storage element have a predetermined value or less. And calculating a linear distance on the substrate between the scan data input terminal of the second storage element and the calculated output terminal of the first storage element. Since the scan data input terminal is connected, the wiring between the first and second storage elements is shortened, and an increase in the load capacitance of the circuit in the normal operation mode is avoided.

According to a tenth aspect of the present invention, the first and second objects are achieved, and one of the plurality of output terminals in a first storage element having a plurality of output terminals; The present invention is directed to a method of designing a semiconductor integrated circuit having a scan data input terminal and connecting the scan data input terminal in a second storage element having a scan test function, wherein a load capacitance for each output terminal of the first storage element is provided. A capacity calculation step of calculating the minimum value of the load capacity, and a capacity comparison step of comparing the minimum value with a load capacity other than the minimum value, and a minimum value of the load capacity and the minimum value. The difference from the load capacity other than the value is less than the specified value
When there is an output terminal of the first storage element, the difference between the minimum value of the output terminal of the first storage element and the minimum value of the load capacitance is equal to or less than a predetermined value. A distance calculation step of calculating a wiring distance when the output terminal of the first storage element is wired to the scan data input terminal of the second storage element; and a first storage element calculated in the distance calculation step. Of the output terminals, the output terminal with the shortest wiring distance is stored in the second storage
Determine the terminal to be connected to the scan data input terminal of the element
And a minimum value of the load capacity and a load capacity other than the minimum value.
Output terminal of the first storage element, wherein the difference between
In the case where there is no load capacity, the first load capacity becomes the minimum load capacity.
The output terminal of the storage element is connected to the scan data of the second storage element.
Determines a terminal to be connected to the data input terminal is for the configuration and a connection step of connecting the scan data input terminal of the determined terminal <br/> and the second storage element.

According to the tenth aspect , the output terminal of the first storage element having the minimum load capacitance and the output terminal of the first storage element having a difference between the minimum value of the load capacitance and the output terminal of the first storage element having the minimum value are equal to or less than a predetermined value. And calculating the actual wiring distance between the scan data input terminal of the second storage element and the calculated output terminal of the first storage element, the output terminal having the shortest wiring distance and the scan of the second storage element. Since the data input terminal is connected, the wiring between the first and second storage elements is reliably reduced, and an increase in the load capacitance of the circuit in the normal operation mode is avoided.

According to an eleventh aspect of the present invention, the second object is achieved, wherein one of the plurality of output terminals in the first storage element having a plurality of output terminals is connected to a scan data input terminal. The present invention is directed to a method of designing a semiconductor integrated circuit for connecting a scan data input terminal in a second storage element having a terminal and having a scan test function, wherein the drive capability of the output terminal of the first storage element is maximum. And a connection step of connecting the selected output terminal to the scan data input terminal of the second storage element.

According to the eleventh aspect , an output terminal having the maximum drive capability is selected from the output terminals of the first storage element, and the selected output terminal and the scan data input of the second storage element are selected. Since the terminals are connected, the delay time is shortened even with the same load capacitance.

According to a twelfth aspect of the present invention, in the configuration of the eleventh aspect , the connecting step determines whether or not an unconnected output terminal is present at an output terminal of the first storage element. And a step of selecting the output terminal having the maximum drive capability among the unconnected output terminals when there are any of the output terminals.

According to a thirteenth aspect of the present invention, the second object is achieved, wherein one of the plurality of output terminals in the first storage element having a plurality of output terminals is connected to a scan data input terminal. The present invention is directed to a method for designing a semiconductor integrated circuit having a terminal and a scan data input terminal in a second storage element having a scan test function, wherein one of the output terminals of the first storage element has a clock signal of one. When there is an output terminal having a design margin equal to or greater than a predetermined amount, which is a difference between a cycle time and a propagation time for a signal to propagate through a connection path from the output terminal of the first storage element to another storage element or an external output. Select the output terminal and
If there is no output terminal whose total margin exceeds the specified amount,
Select the output terminal that maximizes the design margin
It said output terminal and before Symbol becomes maximum was one in which a configuration that is provided with a connecting step of connecting the scan data input terminal of the second storage element.

According to the structure of the thirteenth aspect , since the output terminal of the output terminal of the first storage element that maximizes the design margin and the scan data input terminal of the second storage element are connected, the signal delay increases. Can be suppressed.
The invention of claim 14 achieves the second object.
The first storage element having a plurality of output terminals
An output terminal of the plurality of output terminals
Has scan data input terminal and scan test function
The scan data input terminal in the second storage element;
A method for designing a semiconductor integrated circuit for connecting
Of the output terminals of the first storage element, one of the clock signal
Cycle time and another output from the output terminal of the first storage element.
Signal propagates along the connection path to the storage element or external output
The above-mentioned output at which the design margin, which is the difference from the propagation time, is maximized.
Input terminal and scan data input terminal of the second storage element
And a connection step for connecting
You.

According to a fifteenth aspect of the present invention, the second object is achieved, wherein one of the plurality of output terminals in a first storage element having a plurality of output terminals is connected to a scan data input terminal. The present invention is directed to a method for designing a semiconductor integrated circuit that connects a scan data input terminal in a second storage element having a scan test function with a terminal, wherein each of the output terminals is connected to the output terminal of the first storage element. When the scan data input terminal of the second storage element is connected, the signal propagates through the connection path from the output terminal of the first storage element to another storage element or an external output during one cycle of the clock signal. A margin calculating step of calculating a design margin, which is a difference from the propagation time to be performed, and the first margin calculated in the margin calculating step.
Among the output terminals of the storage element, if there is an output terminal whose design margin is equal to or more than a predetermined amount , the output terminal is selected, and
When there is no output terminal for which the design margin exceeds a specified amount
Selects the output terminal that maximizes the design margin, and selects
It is an arrangement and a connecting step for connecting the scan data input terminal of said output terminals before Symbol second memory element to be-option maximum was.

According to the fifteenth aspect , when each output terminal of the first storage element is connected to the scan data input terminal of the second storage element, the output terminal of the first storage element is designed. The output terminal with the maximum margin is calculated, and among the calculated output terminals of the first storage element,
Since the output terminal having the largest design margin is connected to the scan data input terminal of the second storage element, signal delay can be minimized. In addition, claim 16
The invention achieves the second object and has a plurality of outputs.
The plurality of outputs at a first storage element having a force terminal
One of the terminals and the scan data input terminal
To the second storage element having a scan test function.
Collection that connects to the scan data input terminal
The present invention is directed to an integrated circuit design method, wherein
Output terminals of the second storage element
When connected to the scan data input terminal, the clock
The time of one cycle of the signal and the output end of the first storage element
Signal on the connection path from the element to another storage element or external output.
The design margin, which is the difference from the propagation time
Calculating a margin and calculating the margin
The output terminal of the first storage element calculated in
That is, the output terminal and the
Connect to the scan data input terminal of the second storage element
And a connecting step.

A seventeenth aspect of the present invention achieves the third object, and provides an output of one of the plurality of output terminals in a first storage element having a scan data input terminal and a plurality of output terminals. A method for designing a semiconductor integrated circuit for connecting a terminal and a scan data input terminal in a second storage element having a scan data input terminal and having a scan test function. And selecting an output terminal having a maximum delay value of a signal input from the scan data input terminal of the first storage element, and selecting the selected output terminal and the scan data input terminal of the second storage element. And a connection step for connecting

According to the configuration of claim 17 , the scan data of the output terminal of the first storage element and the scan data of the second storage element at which the delay value of the signal input from the scan data input terminal of the first storage element becomes maximum. Because the input terminal is connected,
Data is input to the scan data input terminal of the second storage element with a delay.

The invention according to claim 18 achieves the third object, and provides an output of one of the plurality of output terminals in a first storage element having a scan data input terminal and a plurality of output terminals. A method for designing a semiconductor integrated circuit for connecting a terminal and a scan data input terminal in a second storage element having a scan data input terminal and having a scan test function. When there is an output terminal in which the delay value of the signal input from the scan data input terminal of the first storage element is equal to or more than a predetermined amount, the output terminal is selected and the delay value is selected.
If there is no output terminal that exceeds a predetermined amount, the first storage
Delay of the signal input from the scan data input terminal of the device
A connection step of selecting an output terminal having the maximum extension value and connecting the selected output terminal to a scan data input terminal of the second storage element is provided.

According to the eighteenth aspect , the output terminal of the first storage element and the output terminal of the second storage element, wherein the delay value of the signal input from the scan data input terminal of the first storage element is equal to or more than a predetermined amount. Since the scan data input terminal is connected, data is input to the scan data input terminal of the second storage element with a delay.

[0067]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A method for designing a semiconductor integrated circuit according to a first embodiment of the present invention will be described with reference to the drawings.
FIG. 20 is a circuit diagram showing a scan register used also for explaining a conventional method of designing a semiconductor integrated circuit. Description of each terminal of the scan register 10 shown in FIG. 20 is omitted.
The scan register 10 used in each drawing has a scan data input terminal 12 of SI, a positive logic output terminal 1
5 is Q and the inverted logic output terminal 16 is NQ, and only these scan data input terminal SI, positive logic output terminal Q and inverted logic output terminal NQ are displayed.

FIG. 1 is a flowchart showing a method for designing a semiconductor integrated circuit according to the first embodiment of the present invention. In FIG. 1, SA1 is a step of designating the connection order of the scan register, SA2 is a step of arranging each element of the semiconductor integrated circuit, SA3 is a step of wiring other signal lines other than wiring for scan chain connection, SA4 is a step of selecting a pair of scan registers adjacent to each other in the scan chain, and SA5 is each output terminal and scan-out terminal of the preceding scan register on the scan-in terminal side among the pair of scan registers selected in SA4. Calculating a linear distance between the scan data input terminal of the subsequent scan register and the scan data input terminal of the semiconductor integrated circuit on the hardware serving as the substrate of the semiconductor integrated circuit; Select one output terminal with the shortest linear distance from the scan data input terminal SA7 is a step of determining the output terminal of the preceding scan register to be connected to the scan data input terminal of the subsequent scan register. SA8 is a step of determining whether or not the processing has been completed for all pairs of scan registers in the scan chain. The step of determining, SA9 is step S
This is a step of performing wiring processing between the output terminal of the preceding scan register and the scan data input terminal of the subsequent scan register determined in A7.

In step SA4, the pair of the last scan register and the scan-out terminal is also treated as a pair of scan registers in the scan chain. In step SA7, an output terminal that minimizes the linear distance selected in step SA6 is uniquely selected.

In the flowchart shown in FIG. 2, when there is an output terminal whose difference from the minimum value of the linear distance selected in step SA6 shown in FIG. 1 is within a certain value, the fan-out number of each terminal is further increased. An object of the present invention is to reduce the load capacitance as well as the wiring area by making the determination.
Therefore, the object is achieved by replacing the step SA7 shown in FIG. 1 with the flowchart shown in FIG. In FIG. 2, SA7a calculates a difference between a linear distance between an output terminal having a minimum linear distance from a scan data input terminal of a subsequent scan register and a linear distance between the other output terminals, among output terminals of a preceding scan register; SA7b is a step of judging whether there are a plurality of output terminals of the preceding scan register including the output terminal having the shortest linear distance, in which the difference between the linear distances calculated in step SA7a is equal to or smaller than a certain value α, SA7c Is a step of deciding to connect the output terminal of the preceding scan register with the shortest linear distance to the scan data input terminal of the succeeding scan register, and SA7d is connecting the output terminal of the preceding scan register satisfying the condition of step SA7b. Step SA7e of registering in a candidate list to be processed, SA7e calculates the fanout number of each output terminal in the candidate list. Step of calculating Re respectively, SA7f is a step for determining that an output terminal connected to the fanout is minimized to the scan data input terminal of the subsequent scan register. Here, the fixed value α that determines the width of the minimum straight line distance is 3 μm.

FIG. 21 is a circuit diagram showing a semiconductor integrated circuit before wiring scan registers. The circuit diagram of the semiconductor integrated circuit shown in FIG. 21 is a circuit diagram used when explaining a conventional method of designing a semiconductor integrated circuit, and therefore, description of each component will be omitted.

FIG. 22 is a circuit diagram obtained by performing the arrangement and wiring processing shown in FIG. 1 on the semiconductor integrated circuit shown in FIG. In FIG. 22, reference numeral 20A denotes an arrangement and wiring area for arranging and wiring the semiconductor integrated circuit when the scan chain is generated, and the position and size of each element and wiring reflect actual hardware. Reference numerals 21 to 25 denote scan registers constituting a shift register at the time of a scan test;
Reference numeral 2 denotes an AND gate that outputs "1" only when both input signals are "1", inverters 33 to 35 output an inverted signal of the input signal, and 36 inputs a scan test signal. A scan-in terminal 37 is a scan-out terminal for outputting a scan test signal.
41A is a wiring connecting the positive logic output terminal Q of the scan register 21 to the scan data input terminal SI of the scan register 22, and 42A is connecting the positive logic output terminal Q of the scan register 22 and the scan data input terminal SI of the scan register 23. The wiring to be connected, 43A, is connected to the inverted logic output terminal NQ of the scan register 23 and the scan register 24.
Connecting the scan data input terminal SI to
A is a wiring connecting the inverted logic output terminal NQ of the scan register 24 to the scan data input terminal SI of the scan register 25, and 45A is a wiring connecting the positive logic output terminal Q of the scan register 25 and the scan out terminal 37, respectively. is there.

A process in which scan registers are wired by sequentially performing the steps shown in FIGS. 1 and 2 on the semiconductor integrated circuit before the generation of the scan chain shown in FIG. 21 will be described. First, in step SA1, the connection order of the scan registers is designated so as to be connected in the order of scan register 21, scan register 22, scan register 23, scan register 24, scan register 25, and scan out terminal 37.

Next, in step SA2, after the scan registers 21 to 25, AND gates 26 to 32 and inverters 33 to 35 are arranged, in step SA3,
Wiring processing of each element other than the scan registers 21 to 25 is performed.

Next, in step SA4, a pair of scan registers 21 and 22 is first selected.

Next, in step SA5, the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 21
, The linear distance to the scan data input terminal SI of the scan register 22 is calculated, and the linear distance value of the positive logical output terminal Q is 100 μm and the linear distance value of the inverted logical output terminal NQ is 110 μm. Suppose.

Next, in step SA6, the positive logic terminal Q having the minimum linear distance is selected from the calculation result in step SA5, and in the next step SA7, each processing shown in FIG. 2 is sequentially executed.

First, in step SA7a shown in FIG.
The difference between each linear distance between the positive logical output terminal Q and the inverted logical output terminal NQ of the scan register 21 and the scan data input terminal of the scan register 22 and the minimum value of the linear distance is calculated, and 10 μm of the calculation result is obtained.

Next, in step SA7b, since the difference in the linear distance is larger than the fixed value α of 3 μm, the next processing step is determined as step SA7c.

In step SA7c, it is determined that the positive logic output terminal Q with the shortest linear distance is connected to the scan data input terminal SI of the scan register 22.

Next, the process returns to step SA8 shown in FIG. 1, and since there are four remaining scan register pairs, the process returns to step SA4.

Next, in step SA4, a pair of the scan register 22 and the scan register 23 is selected.

The following Table 1 shows on the board the positive logic output terminal Q and inverted logic output terminal NQ of the preceding scan register and the scan data input terminal SI of the subsequent scan register for each adjacent scan register. This is a list showing each linear distance, and the unit of the distance is μm.
For example, in the left column of [Table 1], the linear distance between the positive logic output terminal Q of the preceding scan register 21 and the scan data input terminal NQ of the subsequent scan register is 100 μm.
Is shown.

[0084]

[Table 1]

Hereinafter, each of the processes from step SA5 to step SA8 will be referred to as scan register 22 and scan register 23.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 22 as shown in [Table 1].
And scan data input terminal SI of scan register 23
Are 40 μm and 45 μm, respectively, and the difference between the linear distances is 5 μm, which is larger than the fixed value α of 3 μm. Therefore, the output terminal to be connected is determined as the positive logic output terminal Q having the minimum linear distance. I do.

Next, each processing from step SA5 to step SA8 is performed by the scan register 23 and the scan register 24.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 23 as shown in [Table 1].
And scan data input terminal SI of scan register 24
Are 40 μm and 35 μm, respectively, and the difference between the linear distances is 5 μm, which is larger than the fixed value α of 3 μm. Therefore, the output terminal to be connected is determined to be the inverted logic output terminal NQ that minimizes the linear distance. I do.

Next, when the processes from step SA5 to step SA8 are performed on the pair of scan registers 24 and 25,
As shown in Table 1, the linear distance between the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 24 and the scan data input terminal SI of the scan register 25 is
Since they are 60 μm and 61 μm, respectively, in step SA7b shown in FIG. 2, the difference in the linear distance is 1 μm, which is smaller than the fixed value α of 3 μm, so the next processing step is determined as step SA7d.

In step SA7d, after registering the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 24 in the candidate list to be connected, in step SA7e, the positive logic output terminal Q and the inverted logic output The number of each fan-out of the terminal NQ is calculated. Since the positive logic output terminal Q is connected to the two elements of the inverters 34 and 35, the number of fan-outs is two. On the other hand, since the inverted logic output terminal NQ is connected only to the AND gate 31, the number of fan-outs is one. Therefore, step SA
At 7e, it is determined that the output terminal NQ having the minimum fan-out number is connected to the scan data input terminal of the scan register 25.

Next, each processing from step SA5 to step SA8 is performed by the scan register 25 and the scan-out terminal 3
7, the positive logic output terminal Q and the inverted logic output terminal N of the scan register 25 as shown in [Table 1].
Since the linear distance between Q and the scanout terminal 37 is 40 μm and 45 μm, respectively, the difference between the linear distances is 5 μm.
m, which is larger than the constant value α of 3 μm, the output terminal to be connected is determined to be the positive logic output terminal Q having the shortest linear distance.

Next, when the flow proceeds to step SA8, since all the pairs of scan registers have been processed, the flow proceeds to step SA9. In step SA9, each wiring process is performed between the output terminal Q or NQ of the preceding scan register determined to be connected in step SA7 and the scan data input terminal SI or the scan out terminal 37 of the subsequent scan register. The wirings 41A to 41A-4 shown in FIG.
Generate scan chains connected by 5A.

The wiring 42A and the wiring 43A shown in FIG. 22 connected by the above arrangement and wiring processing are better than the wirings 42Z and 43Z corresponding to the case where the conventional semiconductor integrated circuit designing method shown in FIG. 26 is applied. Since the wiring length is shortened, the wiring area can be reduced.

Further, the scan register 24 is connected to the scan register 25 using the inverted logic output terminal NQ having a smaller fanout number than the positive logic output terminal Q, so that the scan register 24 performs a scan as compared with the case where the conventional method is applied. Since an increase in the load on the positive logic output terminal Q of the register 24 can be avoided, a significant increase in the delay time of the signal from the positive logic output terminal Q to the inverter 34 and the inverter 35 can be prevented.

In FIG. 1, when the process SA7 is not replaced with the processing flow shown in FIG. 2, the linear distance between the output terminal of the preceding scan register and the scan data input terminal of the subsequent scan register becomes the shortest. Since the terminals are connected to each other, the scan register 24 shown in FIG.
The scan chain connection is the same except that the inverted logic output terminal NQ of the scan register 25 is connected to the scan data input terminal SI of the scan register 25. Accordingly, the wiring length is shorter than the corresponding wirings 42Z and 43Z when the conventional design method shown in FIG. 26 is applied, so that the wiring area can be reduced.

FIG. 3 shows a method of selecting an output terminal with a small load in consideration of the fan-out number of each output terminal of the preceding scan register shown in FIG. 9 is a flowchart illustrating a method of calculating a load capacity and selecting an output terminal having a small load capacity. In FIG. 3, the same steps as those in FIG. S shown in FIG.
A7g is a step of calculating the load capacity for each output terminal in the candidate list to be connected, and SA7h is connecting the output terminal of the preceding scan register with the minimum load capacity to the scan data input terminal of the subsequent scan register. Is a step of determining In addition, the load capacitance for the output terminal in the present embodiment is the sum of the load capacitance of the input terminal of the element connected to the output terminal and the load capacitance of the connection wiring.

Hereinafter, a description will be given of a wiring method when the processing method shown in FIG. 3 is used instead of the step SA7 in FIG.

When a pair of the scan register 24 and the scan register 25 is selected in the step SA4 shown in FIG. 1, the difference in the linear distance becomes 1 μm in the step SA7a shown in FIG.

Next, in step SA7b, since the difference between the linear distances is equal to or smaller than the fixed value α of 3 μm, it is decided to proceed to step SA7d.

Next, in step SA7d, after registering the positive logic output terminal Q and the inverted logic output terminal NQ in the candidate list to be connected, in step SA7g, the positive logic output terminal Q and the inverted logic output terminal in the candidate list are registered. Calculate the load capacity for NQ. One positive logic output terminal Q is connected to the two elements of the inverter 34 and the inverter 35, and the total value of the load capacitance of the connection wiring and the load capacitance of the input terminals of the inverters 34 and 35 is 1.5 pF. Of the load capacitance of the inverted logic output terminal NQ is 0.5 pF
Becomes

Next, in step SA7h, the inverted logic output terminal NQ having the smallest load capacitance and the scan register 2
5 to be connected to the scan data input terminal SI. As a result, the final circuit diagram has the same connection as the scan chain connection shown in FIG.

Therefore, the wiring 42A and the wiring 43A shown in FIG. 22 correspond to the wiring 42Z and the wiring 43Z corresponding to the case where the conventional method of designing a semiconductor integrated circuit shown in FIG.
Therefore, the wiring length can be shortened, so that the wiring area can be reduced. The scan register 2 shown in FIG.
4 is connected to the scan data input terminal SI of the scan register 25 using the inverted logic output terminal NQ whose load capacity is smaller than the positive logic output terminal Q, so that the scan register 24 is compared with the case where the conventional design method is applied. Therefore, it is possible to prevent a significant increase in the delay time of the signal from the positive logic output terminal Q to the inverter 34 and the inverter 35.

In each of the embodiments of the present application including this embodiment, the description is made using a scan register having two output terminals of a positive logic output terminal Q and an inverted logic output terminal NQ. 3 having a scan data output terminal in addition to the output terminal Q and the inverted logic output terminal NQ
A similar effect is obtained for a scan register having one or more output terminals.

In this embodiment, the value of the constant value α is set to 3 μm. However, the same effect can be obtained by setting the value of α to an arbitrary value of 0 μm or more.

(Second Embodiment) Hereinafter, a method for designing a semiconductor integrated circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a flowchart showing a method for designing a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 4, steps SB1 to SB4, SB8 and S
B9 represents steps SA1 to SA4, SA described in FIG.
8 and SA9, and the corresponding steps have the same contents. SB5 is a step of calculating each wiring distance when each output terminal of the preceding scan register is connected to the scan data input terminal of the subsequent scan register, and SB6 is a step of calculating the following wiring among the output terminals of the preceding scan register. One output terminal with the shortest wiring distance from the scan data input terminal of the scan register
Step SB7 is a step of determining the output terminal of the preceding scan register to be connected to the scan data input terminal of the subsequent scan register. In step SB7, the output terminal of the preceding scan register selected in the previous step SB6 is set as a connection target.

The flowchart shown in FIG. 5 shows that if there is an output terminal whose difference from the minimum value of the wiring distance selected in step SB6 shown in FIG. An object of the present invention is to reduce the load capacitance as well as the wiring area by making the determination.
Therefore, the object is achieved by replacing the step SB7 shown in FIG. 4 with the flowchart shown in FIG. In FIG. 5, an SB 7a calculates a difference between a wiring distance between an output terminal having a minimum wiring distance to a scan data input terminal of a subsequent scan register among output terminals of a preceding scan register, and another output terminal. Process, SB7b
Is a step of determining whether or not there are a plurality of output terminals of the preceding scan register including the output terminal having the shortest wiring distance, in which the difference between the wiring distances calculated in step SB7a is equal to or smaller than the fixed value α, and SB7c A step of deciding to connect the output terminal of the preceding scan register with the shortest wiring distance to the scan data input terminal of the subsequent scan register, and SB7d connects the output terminal of the preceding scan register satisfying the condition of step SB7b SB7e is a step of calculating the number of fan-outs of each output terminal in the candidate list, and SB7f
Is a step of determining the connection of the output terminal having the minimum fan-out number to the scan data input terminal of the subsequent scan register. Here, the fixed value α for determining the width of the minimum wiring distance is 3 μm.

FIG. 23 is a circuit diagram obtained by performing the arrangement and wiring processing shown in FIGS. 4 and 5 on the semiconductor integrated circuit shown in FIG. In FIG. 23, reference numeral 20A denotes an arrangement and wiring area for arranging and wiring the semiconductor integrated circuit when the scan chain is generated, and the position and size of each element and wiring reflect actual hardware. Reference numerals 21 to 25 denote scan registers constituting a shift register at the time of a scan test.
6 to 32 are AND gates that output "1" only when both input signals are "1"; 33 to 35 are inverters that output inverted signals of the input signals; and 36 is a scan test signal. An input scan-in terminal 37 is a scan-out terminal for outputting a scan test signal. 41B is a wiring connecting the inverted logic output terminal NQ of the scan register 21 to the scan data input terminal SI of the scan register 22, and 42B is a wire connecting the positive logic output terminal Q of the scan register 22 and the scan data input terminal SI of the scan register 23. A wiring 43B connects the inverted logic output terminal NQ of the scan register 23 to the scan data input terminal SI of the scan register 24, and a wiring 44B connects the inverted logic output terminal NQ of the scan register 24 and the scan data input of the scan register 25. The wiring connecting the terminal SI and the wiring 45B connect the positive logic output terminal Q of the scan register 25 and the scan-out terminal 37, respectively.

A process in which the scan registers are wired by sequentially performing the steps shown in FIGS. 4 and 5 on the semiconductor integrated circuit before the generation of the scan chain shown in FIG. 21 will be described. First, in step SB1, the connection order of the scan registers is designated so as to connect in the order of scan register 21, scan register 22, scan register 23, scan register 24, scan register 25, and scan out terminal 37.

Next, in step SB2, the scan registers 21 to 25, the AND gates 26 to 32, and the inverters 33 to 35 are arranged, and in step SB3, wiring processing of each element other than the scan registers 21 to 25 is performed. Do.

Next, in step SB4, a pair of the scan register 21 and the scan register 22 is first selected.

Next, in step SB5, the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 21 are read.
, The wiring distance to the scan data input terminal SI of the scan register 22 is calculated, and the value of the wiring distance of the positive logic output terminal Q is 200 μm and the value of the wiring distance of the inverted logic output terminal NQ is 130 μm. Suppose.

Next, in step SB6, the inversion logic terminal NQ having the minimum wiring distance is selected from the calculation result in step SB5, and in the next step SB7, each processing shown in FIG. 5 is executed.

First, in step SB7a shown in FIG. 5, each wiring distance between the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 21 and the scan data input terminal of the scan register 22 and the minimum value of the wiring distance are determined. Is calculated to obtain a calculation result of 70 μm.

Next, in step SB7b, since the difference in the wiring distance is larger than the fixed value α of 3 μm, the next processing step is determined as step SB7c.

In step SB7c, it is determined that the inverted logic output terminal NQ having the shortest wiring distance is connected to the scan data input terminal SI of the scan register 22.

Next, the process returns to step SB8 shown in FIG. 4, and since there are four remaining scan register pairs, the process returns to step SB4.

Next, in step SA4, a pair of the scan register 22 and the scan register 23 is selected.

The following Table 2 shows on the substrate the positive logic output terminal Q and inverted logic output terminal NQ of the preceding scan register and the scan data input terminal SI of the subsequent scan register for each adjacent scan register. It is a list showing each wiring distance. Here, the unit of the wiring distance is μm.

[0117]

[Table 2]

Hereinafter, the processing from step SB5 to step SB8 will be referred to as scan register 22 and scan register 23.
Of the scan register 22, the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 22 as shown in [Table 2].
And scan data input terminal SI of scan register 23
Are 60 μm and 70 μm, respectively, so that the difference between the wiring distances is 10 μm and the constant value α is 3 μm.
Therefore, the output terminal to be connected is determined to be the positive logic output terminal Q that minimizes the wiring distance.

Next, the processing from step SB5 to step SB8 is performed by the scan register 23 and the scan register 24.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 23 as shown in [Table 2].
And scan data input terminal SI of scan register 24
Are 60 μm and 50 μm, respectively, so that the difference between the wiring distances is 10 μm and the constant value α is 3 μm.
Therefore, the output terminal to be connected is determined to be the inverted logic output terminal NQ that minimizes the wiring distance.

Next, each processing from step SB5 to step SB8 is performed by the scan register 24 and the scan register 25.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 24 as shown in [Table 2].
And scan data input terminal SI of scan register 25
Are 80 μm and 83 μm, respectively. Therefore, in step SB7b shown in FIG. 5, the difference in wiring distance is 3 μm, which is equal to the constant value α of 3 μm, so the next processing step is determined as step SB7d. .

In step SB7d, after registering the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 24 in the candidate list for connection, in step SB7e, the positive logic output terminal Q and the inverted logic output terminal in the candidate list are registered. The number of each fan-out of the terminal NQ is calculated. Since the positive logic output terminal Q is connected to the two elements of the inverters 34 and 35, the number of fan-outs is two. On the other hand, since the inverted logic output terminal NQ is connected only to the AND gate 31, the number of fan-outs is one. Therefore, step SB
At 7f, it is determined that the output terminal NQ having the smallest fan-out number is connected to the scan data input terminal of the scan register 25.

Next, the processing from step SB5 to step SB8 is performed by the scan register 25 and the scan-out terminal 3
7, the positive logic output terminal Q and the inverted logic output terminal N of the scan register 25 as shown in [Table 2].
Since the wiring distance between Q and the scan-out terminal 37 is 40 μm and 60 μm, respectively, the difference between the wiring distances is 20 μm.
μm, which is larger than the constant value α of 3 μm, so that the output terminal to be connected is connected to the positive logic output terminal Q that minimizes the wiring distance.
To decide.

Next, when the process proceeds to step SB8, all the pairs of scan registers have been processed, so that the process proceeds to step SB9 by judgment. In step SB9, each wiring process is performed between the output terminal Q or NQ of the preceding scan register determined to be connected in step SB7 and the scan data input terminal SI or the scan out terminal 37 of the subsequent scan register. Thus, a scan chain connected by the wirings 41B to 45B shown in FIG. 23 is generated.

The wirings 41B, 42B and 43B shown in FIG. 23 connected by the above arrangement and wiring processing.
Since the wiring length is shorter than that of the wiring 41Z, the wiring 42Z, and the wiring 43Z corresponding to the case where the conventional semiconductor integrated circuit design method shown in FIG. 26 is applied, the wiring area can be reduced.

Further, the scan register 24 is connected to the scan register 25 using the inverted logic output terminal NQ having a smaller fanout number than the positive logic output terminal Q, so that the scan register 24 is compared with the case where the conventional method is applied. Since an increase in the load on the positive logic output terminal Q of the register 24 can be avoided, a significant increase in the delay time of the signal from the positive logic output terminal Q to the inverter 34 and the inverter 35 can be prevented.

Further, as a feature of this embodiment, FIG.
The wiring distance of the wiring 41B shown in FIG.
Since the wiring distance of the wiring 41A shown in FIG. 2 can be made smaller than 200 μm, the wiring area can be further reduced as compared with the design method shown in the first embodiment.

In FIG. 4, when the process SB7 is not replaced with the processing flow shown in FIG. 5, the wiring distance between the output terminal of the preceding scan register and the scan data input terminal of the subsequent scan register becomes minimum. Since the terminals are connected to each other, the scan register 24 shown in FIG.
, And the scan chain connection is the same except that the positive logic output terminal Q is connected to the scan data input terminal SI of the scan register 25. Therefore, the wiring 41Z and the wiring 4 corresponding to the case where the conventional design method shown in FIG.
Since the wiring length is shorter than the 2Z and the wiring 43Z, the wiring area can be reduced.

FIG. 6 shows a method of selecting an output terminal with a small load in consideration of the fan-out number of each output terminal of the preceding scan register shown in FIG. 9 is a flowchart illustrating a method of calculating a load capacity and selecting an output terminal having a small load capacity. In FIG. 6, the same steps as those in FIG. S shown in FIG.
B7g is a step of calculating the load capacity for each output terminal in the candidate list to be connected, and SB7h is connecting the output terminal of the preceding scan register with the smallest load capacity to the scan data input terminal of the subsequent scan register. Is a step of determining In addition, the load capacitance for the output terminal in this embodiment is the sum of the load capacitance of the input terminal of the element connected to the output terminal and the load capacitance of the connection wiring.

Hereinafter, a description will be given of a wiring method when the processing method shown in FIG. 6 is used instead of the step SB7 in FIG.

When a pair of scan register 24 and scan register 25 is selected in step SB4 shown in FIG. 4, the difference in the linear distance becomes 3 μm in step SB7a shown in FIG. Next, in step SB7b, since the difference between the linear distances is equal to or smaller than the fixed value α of 3 μm,
Decide to go to d.

Next, in step SB7d, after registering the positive logic output terminal Q and the inverted logic output terminal NQ in the candidate list to be connected, in step SB7g, the positive logic output terminal Q and the inverted logic output terminal in the candidate list are registered. Calculate the load capacity for NQ. One positive logic output terminal Q is connected to the two elements of the inverter 34 and the inverter 35, and the total value of the load capacitance of the connection wiring and the load capacitance of the input terminals of the inverters 34 and 35 is 1.5 pF. Of the load capacitance of the inverted logic output terminal NQ is 0.5 pF
Becomes

Next, in step SB7h, the inverted logic output terminal NQ having the smallest load capacity and the scan register 2
5 to be connected to the scan data input terminal SI. As a result, the final circuit diagram has the same connection as the scan chain connection shown in FIG.

Therefore, the wiring 41B and the wiring 4 shown in FIG.
2B and wiring 43B are wiring 41Z, corresponding to the case where the conventional method of designing a semiconductor integrated circuit shown in FIG. 26 is applied.
Since the wiring length can be shorter than the wirings 42Z and 43Z, the wiring area can be reduced. FIG.
Is connected to the scan data input terminal SI of the scan register 25 by using an inverted logic output terminal NQ having a load capacity smaller than the positive logic output terminal Q. Therefore, compared to the case where the conventional design method is applied. Thus, an increase in the load on the positive logic output terminal Q of the scan register 24 can be avoided, so that a significant increase in the delay time of the signal from the positive logic output terminal Q to the inverter 34 and the inverter 35 can be prevented.

The wiring distance of the wiring 41B shown in FIG. 23 is 130 μm, which can be made smaller than the wiring distance of 200 μm of the wiring 41A shown in FIG. 22, so that the wiring area is further larger than the design method shown in the first embodiment. Can be reduced.

In this embodiment, the value of the constant value α is set to 3 μm. However, the same effect can be obtained by setting the value of α to an arbitrary value of 0 μm or more.

(Third Embodiment) Hereinafter, a method for designing a semiconductor integrated circuit according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a flowchart showing a method for designing a semiconductor integrated circuit according to the third embodiment of the present invention. In FIG. 7, steps SC1 to SC4, SC8 and S
C9 represents steps SA1 to SA4, SA described in FIG.
8 and SA9, and the corresponding steps have the same contents. SC5 is a step of calculating the number of fanouts of each output terminal of the preceding scan register, SC6 is a step of selecting one of the output terminals of the preceding scan register that has the smallest number of fanouts, SC7. Is a step of determining the output terminal of the preceding scan register to be connected to the scan data input terminal of the subsequent scan register. In step SC7, the output terminal of the previous-stage scan register selected in the previous step SC6 is connected.

The flowchart shown in FIG. 8 is based on the case where there is an output terminal whose difference from the minimum value of the fan-out number selected in step SC6 shown in FIG. It is another object of the present invention to further reduce the load area as well as the load capacity by further determining the linear distance on the substrate from the scan data input terminal of the register. Therefore, the object is achieved by replacing the step SC7 shown in FIG. 7 with the flowchart shown in FIG.

In FIG. 8, SC7a is a step of calculating the difference between the number of fanouts of the output terminal of the preceding scan register having the smallest number of fanouts and the other output terminals, and SC7b is a step SC7a. A step of determining whether or not there are a plurality of output terminals of the preceding scan register including the output terminal having the smallest fan-out number, in which the calculated difference in the number of fan-outs is equal to or smaller than the fixed value α, A step of deciding to connect the output terminal of the preceding scan register with the minimum number to the scan data input terminal of the subsequent scan register,
SC7d is a step of registering the output terminal of the preceding scan register satisfying the condition of step SC7b in the candidate list to be connected, and SC7e is a linear distance between each output terminal in the candidate list and the scan data input terminal of the subsequent scan register. SC7f is a step of determining to connect the output terminal with the shortest linear distance to the scan data input terminal of the subsequent scan register.
Here, a constant value α that determines the width of the minimum fan-out number
Is set to 0.

FIG. 24 is a circuit diagram obtained by performing the arrangement and wiring processing shown in FIGS. 7 and 8 on the semiconductor integrated circuit shown in FIG. In FIG. 24, reference numeral 20A denotes an arrangement and wiring area for arranging and wiring the semiconductor integrated circuit at the time of generation of the scan chain, and the position and size of each element and wiring reflect actual hardware. Reference numerals 21 to 25 denote scan registers constituting a shift register at the time of a scan test.
6 to 32 are AND gates that output "1" only when both input signals are "1"; 33 to 35 are inverters that output inverted signals of the input signals; and 36 is a scan test signal. An input scan-in terminal 37 is a scan-out terminal for outputting a scan test signal. 41C is a wiring connecting the inverted logic output terminal NQ of the scan register 21 and the scan data input terminal SI of the scan register 22, and 42C is a wire connecting the inverted logic output terminal NQ of the scan register 22 and the scan data input terminal SI of the scan register 23. Wiring to connect, 43C
Is a wiring connecting the inverted logic output terminal NQ of the scan register 23 to the scan data input terminal SI of the scan register 24; and 44C is connecting the inverted logic output terminal NQ of the scan register 24 to the scan data input terminal SI of the scan register 25. 45C are the positive logic output terminal Q of the scan register 25 and the scan out terminal 37.
And a wiring for respectively connecting.

A process in which the scan registers are wired by sequentially performing the processes shown in FIGS. 7 and 8 on the semiconductor integrated circuit before the generation of the scan chain shown in FIG. 21 will be described. First, in step SC1, the connection order of the scan registers is designated so as to be connected in the order of scan register 21, scan register 22, scan register 23, scan register 24, scan register 25, and scan out terminal 37.

Next, in step SC2, scan registers 21 to 25, AND gates 26 to 32, and inverters 33 to 35 are arranged, and in step SC3, wiring processing of each element other than scan registers 21 to 25 is performed. Do.

Next, in step SC4, a pair of the scan register 21 and the scan register 22 is first selected.

Next, in step SC5, the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 21 are set.
Is calculated, the fan-out number of the positive logic output terminal Q is 2, and the inverted logic output terminal N
The fan-out number of Q is 1.

Next, in step SC6, the inverted logic terminal NQ with the minimum fan-out number is selected from the calculation result in step SC5, and in the next step SC7, each processing shown in FIG. 8 is sequentially executed.

First, in step SC7a shown in FIG.
The difference between the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 21 and the minimum value of the number of fanouts is calculated to obtain 1 as the calculation result.

Next, in step SC7b, since the difference from the minimum value of the fan-out number is larger than the fixed value α of 0,
The next processing step is determined as step SC7c.

In step SC7c, the inverted logic output terminal NQ that minimizes the number of fanouts is set to the scan register 2
2 to be connected to the scan data input terminal SI.

Next, the process returns to step SC8 shown in FIG. 7, and since there are four remaining scan register pairs, the process returns to step SC4.

Next, in step SC4, a pair of the scan register 22 and the scan register 23 is selected.
[Table 3] shown below is a list of the number of fan-outs of the positive logic output terminal Q and the inverted logic output terminal NQ of the preceding scan register for each adjacent scan register. Here, the unit of the number of fan-outs is individual.

[0150]

[Table 3]

Hereinafter, each process from step SC5 to step SC8 is described by the scan register 22 and the scan register 23.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 22 as shown in [Table 3].
Are 1 and 0, respectively, so that the difference between the fan-out numbers is 1 and is larger than the fixed value α of 0, so that the output terminal to be connected is the inverted logic output terminal NQ that minimizes the fan-out number. To decide.

Next, each process from step SC5 to step SC8 is performed by the scan register 23 and the scan register 24.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 23 as shown in [Table 3].
Is 1 in step SC7b, the difference in the number of fanouts is 0 in step SC7b shown in FIG. 8, and is equal to the constant value α.
To decide.

In step SC7d, after registering the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 24 in the candidate list to be connected, in step SC7e, the positive logic output terminal Q and the inverted logic output The linear distance on the board between the terminal NQ and the scan data input terminal of the scan register 24 at the subsequent stage is calculated. It is assumed that the positive logic output terminal Q side is 40 μm and the inverted logic output terminal NQ side is 35 μm. As a result, the next step SC7
f, the inverted logic output terminal N having the shortest linear distance
It is determined that Q is connected to the scan data input terminal of the scan register 24.

Next, each process from step SC5 to step SC8 is performed by the scan register 24 and the scan register 25.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 24 as shown in [Table 3].
Are 2 and 1, respectively, so that the difference between the number of fanouts is 1 and is larger than the fixed value α of 0, so that the output terminal to be connected is the inverted logic output terminal NQ that minimizes the number of fanouts. To decide.

Next, the processing from step SC5 to step SC8 is performed by the scan register 25 and the scan-out terminal 3
7, the positive logic output terminal Q and the inverted logic output terminal N of the scan register 25 as shown in [Table 3].
Since the fan-out numbers of Q are 0 and 1, respectively,
Since the difference between the fan-out numbers is 1, which is larger than the fixed value α of 0, the output terminal to be connected is determined to be the positive logic output terminal Q with the minimum fan-out number.

Next, when the flow proceeds to step SC8, since all the pairs of scan registers have been processed, the flow proceeds to step SC9 by judgment. In step SC9, each wiring process is performed between the output terminal Q or NQ of the preceding scan register determined to be connected in step SC7 and the scan data input terminal SI or the scan out terminal 37 of the subsequent scan register. Thus, a scan chain connected by the wirings 41C to 45C shown in FIG. 24 is generated.

The wiring 43C shown in FIG. 24 connected by the above arrangement and wiring processing corresponds to the case where the conventional semiconductor integrated circuit design method shown in FIG. 26 is applied.
Since the wiring length is shorter than Z, the wiring area can be reduced.

The scan register 21 is connected to the scan register 22 using the inverted logic output terminal NQ having a smaller number of fanouts than the positive logic output terminal Q, so that the scan register 21 is compared with the case where the conventional method is applied. Since an increase in the load on the positive logic output terminal Q of the register 21 can be avoided, the AND gate 26 and the AND gate 26
The scan register 24 is connected to the scan register 25 using an inverted logic output terminal NQ having a smaller fanout number than the positive logic output terminal Q, while preventing a significant increase in the delay time of the signal reaching the gate 27. Therefore, an increase in the load on the positive logic output terminal Q of the scan register 24 can be avoided, so that a significant increase in the delay time of the signal from the positive logic output terminal Q to the inverter 34 and the inverter 35 can be prevented.

In FIG. 7, when the process SC7 is not replaced with the processing flow shown in FIG. 8, the output terminal of the preceding scan register having the smallest fan-out number and the scanning of the subsequent scan register are selected. Since the output terminals of the scan register 23 shown in FIG. 24 have the same fan-out number because they are connected to the data input terminal, the positive logic output terminal Q which is the output terminal searched earlier is used.
Are connected in the same scan chain except that the positive logic output terminal Q and the scan data input terminal SI of the scan register 24 are connected. Accordingly, the delay time of the signal from the positive logic output terminal Q of the scan register 21 to the AND gate 26 and the AND gate 27 is prevented from significantly increasing, and the signal from the positive logic output terminal Q of the scan register 24 to the inverter 34 and the inverter 35 is prevented. Can be prevented from significantly increasing the delay time.

FIG. 9 shows an output terminal having the minimum linear distance in consideration of the linear distance on the substrate between each output terminal of the preceding scan register and the scan data input terminal of the subsequent scan register shown in FIG. 6 is a flowchart illustrating a method of calculating a wiring distance on a substrate and selecting an output terminal having a minimum wiring distance instead of a method of selecting the output terminal. FIG.
In FIG. 8, the same steps as those in FIG. SC7g shown in FIG. 9 is a step of calculating the wiring distance between each output terminal in the candidate list to be connected and the scan data input terminal of the succeeding scan register, and SC7h is the output of the preceding scan register which minimizes the wiring distance. This is a step of deciding to connect a terminal to a scan data input terminal of a subsequent scan register.

Hereinafter, a description will be given of a wiring method when the processing method shown in FIG. 9 is used instead of the step SC7 of FIG.

When a pair of the scan register 23 and the scan register 24 is selected in the step SC4 shown in FIG. 7, a difference 0 in the fan-out number is obtained in the step SC7a shown in FIG. Next, in step SC7b, since the difference in the number of fan-outs is equal to the fixed value α of 0,
Decide to go to 7d.

Next, in step SC7d, after registering the positive logic output terminal Q and the inverted logic output terminal NQ in the candidate list to be connected, in step SC7g, the positive logic output terminal Q and the inverted logic output terminal in the candidate list are registered. The wiring distance between the NQ and the scan data input terminal of the subsequent scan register 24 is calculated. The wiring distance on the positive logic output terminal Q side is 6
0 μm, and the wiring distance on the inverted logic output terminal NQ side is 5 μm.
It is assumed that it is 0 μm.

Next, in step SC7h, the inverted logic output terminal NQ having the shortest wiring distance and the scan register 2
4 to be connected to the scan data input terminal SI. As a result, the final circuit diagram has the same connection as the scan chain connection shown in FIG.

Therefore, the wiring 43C shown in FIG.
6, the wiring length can be made shorter than the wiring 43Z corresponding to the case where the conventional semiconductor integrated circuit design method shown in FIG. 6 is applied, so that the wiring area can be reduced.

Since the load on the positive logic output terminal Q of the scan register 21 does not increase, the AND gates 26 and A
Since the delay time of the signal reaching the ND gate 27 is prevented from significantly increasing and the load on the positive logic output terminal Q of the scan register 24 does not increase, the inverter 34 and the inverter 3 are connected from the positive logic output terminal Q of the scan register 24.
5 can be prevented from increasing significantly.

In the present embodiment, the value of the constant value α is set to 0, but the same effect can be obtained by setting the value of α to an integer of 1 or more.

(Fourth Embodiment) Hereinafter, a method for designing a semiconductor integrated circuit according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a flowchart showing a method for designing a semiconductor integrated circuit according to the fourth embodiment of the present invention. 10, steps SD1 to SD4, SD8 and SD9 correspond to steps SA1 to SA4 described in FIG.
SA8 and SA9 respectively correspond, and the corresponding steps have the same contents. SD5 is a step of calculating the load capacitance for each output terminal of the preceding scan register, SD6 is a step of selecting one of the output terminals of the preceding scan register that has the smallest load capacitance, and SD7 is a latter step. Is a step of determining the output terminal of the preceding scan register to be connected to the scan data input terminal of the scan register. In step SD7, the output terminal of the previous-stage scan register selected in the previous step SD6 is set as a connection target.

The flowchart shown in FIG. 11 is based on the case where there is an output terminal whose difference from the minimum value of the load capacitance selected in step SD6 shown in FIG.
An object of the present invention is to further reduce the wiring area as well as the load capacitance by further determining the linear distance on the substrate between each output terminal and the scan data input terminal of the subsequent scan register. Therefore, this object is achieved by replacing the step SD7 shown in FIG. 10 with the flowchart shown in FIG.

In FIG. 11, SD7a is a step of calculating the difference in load capacitance between the output terminal having the minimum load capacitance among the output terminals of the preceding scan register and the other output terminal, and SD7b is calculated in step SD7a. A step of determining whether there are a plurality of output terminals of the preceding scan register including the output terminal having the minimum load capacitance, in which the difference in load capacitance is equal to or smaller than the fixed value α, and SD7c having the minimum load capacitance A step of deciding to connect the output terminal of the preceding scan register to the scan data input terminal of the subsequent scan register; SD7d registers the output terminal of the preceding scan register satisfying the condition of step SD7b in a candidate list to be connected; SD7e is connected to each output terminal in the candidate list and the scan data input terminal of the subsequent scan register. Step of calculating straight line distances, respectively,
SD7f is a step of deciding to connect the output terminal with the shortest linear distance to the scan data input terminal of the subsequent scan register. Here, the constant value α that determines the width of the minimum load capacitance is 0.2 pF.

FIG. 24 is a circuit diagram obtained by performing the arrangement and wiring processing shown in FIGS. 10 and 11 on the semiconductor integrated circuit shown in FIG. FIG. 24 has been described in the third embodiment, and a description of each component will be omitted.

A process in which the scan registers are wired by sequentially performing the steps shown in FIGS. 10 and 11 on the semiconductor integrated circuit before the generation of the scan chain shown in FIG. 21 will be described. First, in step SD1,
Change the connection order of each scan register to scan register 21 →
It is designated to connect in the order of the scan register 22 → the scan register 23 → the scan register 24 → the scan register 25 → the scan out terminal 37.

Next, in step SD2, the scan registers 21 to 25, AND gates 26 to 32, and inverters 33 to 35 are arranged, and in step SD3, wiring processing for each element other than the scan registers 21 to 25 is performed. Do.

Next, in step SD4, a pair of the scan register 21 and the scan register 22 is first selected. Next, in step SD5, scan register 2
The load capacitance for the positive logic output terminal Q and the inverted logic output terminal NQ is calculated. Positive logic output terminal Q is A
Since they are connected to the ND gates 26 and 27, the load capacitance is 2.0 pF and the inverted logic output terminal NQ is AND
Since it is connected to the gate 28, the load capacity is 0.7 p
Let it be F.

Next, in step SD6, the inverting logic terminal NQ having the minimum load capacity is selected from the calculation result in step SD5, and in the next step SD7, the processes shown in FIG. 11 are sequentially executed.

First, in step SD7a shown in FIG. 11, the difference between the positive logical output terminal Q and the inverted logical output terminal NQ of the scan register 21 and the minimum value of the load capacitance is calculated, and the calculation result is 1.3 pF. Get.

Next, in step SD7b, since the difference from the minimum value of the load capacitance is larger than the fixed value α of 0.2 pF, the next processing step is determined as step SC7c.

In step SD7c, it is determined that the inverted logic output terminal NQ having the smallest load capacitance is connected to the scan data input terminal SI of the scan register 22.

Next, returning to step SD8 shown in FIG. 10, the remaining four scan register pairs remain.
Return to step SD4.

Next, in step SD4, a pair of the scan register 22 and the scan register 23 is selected.

Table 4 below shows a list of load capacitances for the positive logic output terminal Q and the inverted logic output terminal NQ of the preceding scan register for each adjacent scan register. Here, the unit of the load capacity is pF.

[0182]

[Table 4]

Hereinafter, each processing from step SD5 to step SD8 is described by the scan register 22 and the scan register 23.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 22 as shown in [Table 4].
Are 0.5 pF and 0 pF, respectively, and the difference between the load capacitances is 0.5 pF, which is larger than the fixed value α of 0.2 pF. The logic output terminal NQ is determined.

Next, each processing from step SD5 to step SD8 is performed by the scan register 23 and the scan register 24.
And a positive logic output terminal Q and an inverted logic output terminal NQ of the scan register 23 as shown in [Table 4].
1 is 0.5 pF.
In step SD7b shown in FIG. 1, since the difference in load capacitance is 0 and smaller than the fixed value α of 0.2 pF, the next processing step is determined as step SD7d.

After registering the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 23 in the candidate list to be connected in step SD7d, in step SD7e, the positive logic output terminal Q and the inverted logic output terminal in the candidate list are registered. The linear distance on the board between the terminal NQ and the scan data input terminal of the scan register 24 at the subsequent stage is calculated. It is assumed that the positive logic output terminal Q side is 40 μm and the inverted logic output terminal NQ side is 35 μm. As a result, the next step SD7f
, The inverted logic output terminal NQ having the shortest linear distance
Is connected to the scan data input terminal of the scan register 24.

Next, each processing from step SD5 to step SD8 is performed by the scan register 24 and the scan register 25.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 24 as shown in [Table 4].
Are 1.2 pF and 0.5 pF, respectively.
Since the load capacitance is F, the load capacitance difference is 0.7 pF, which is larger than the fixed value α of 0.2 pF. Therefore, the output terminal to be connected is determined to be the inverted logic output terminal NQ with the minimum load capacitance.

Next, each processing from step SD5 to step SD8 is performed by the scan register 25 and the scan-out terminal 3
7, the positive logic output terminal Q and the inverted logic output terminal N of the scan register 25 as shown in [Table 4].
The load capacitance for Q is 0 pF and 0.4 pF, respectively.
Therefore, the difference of the load capacitance becomes 0.4 pF and the constant value α
Therefore, the output terminal to be connected is determined to be the positive logic output terminal Q having the minimum load capacitance.

Next, in step SD8, since all pairs of scan registers have been processed, the flow proceeds to step SD9 by judgment. In step SD9, each wiring process is performed between the output terminal Q or NQ of the preceding scan register determined to be connected in step SD7 and the scan data input terminal SI or the scan out terminal 37 of the subsequent scan register. Thus, a scan chain connected by the wirings 41C to 45C shown in FIG. 24 is generated.

The wiring 43C shown in FIG. 24 connected by the above arrangement and wiring processing is a wiring 43C corresponding to the case where the conventional semiconductor integrated circuit design method shown in FIG. 26 is applied.
Since the wiring length is shorter than Z, the wiring area can be reduced.

The scan register 21 has an inverted logic output terminal NQ having a smaller load capacity than the positive logic output terminal Q.
Is connected to the scan register 22, so that the load on the positive logic output terminal Q of the scan register 21 can be prevented from increasing as compared with the case where the conventional method is applied. 26 and AND
A significant increase in the delay time of the signal reaching the gate 27 can be prevented, and the scan register 24 has an inverted logic output terminal NQ having a smaller load capacity than the positive logic output terminal Q.
, The load on the positive logic output terminal Q of the scan register 24 can be prevented from increasing, so that the delay time of the signal from the positive logic output terminal Q to the inverter 34 and the inverter 35 can be reduced. Significant increase can be prevented.

In FIG. 10, step SD7 is performed as shown in FIG.
When the processing flow is not replaced with the processing flow shown in FIG. 1, since the output terminal of the output register of the preceding scan register that minimizes the load capacitance is connected to the scan data input terminal of the subsequent scan register, the scan shown in FIG. When the load capacity of each output terminal of the register 23 is the same value, even if a logic for connecting the positive logic output terminal Q which is the previously searched output terminal to the connection target is adopted, this positive logic output terminal Q and the scan The scan chain connection is the same as in FIG. 24 except that the scan data input terminal SI of the register 24 is connected. Accordingly, the AND gate 26 and the AN
The delay time of the signal reaching the D gate 27 can be prevented from significantly increasing, and the delay time of the signal reaching the inverter 34 and the inverter 34 from the positive logic output terminal Q of the scan register 24 can be prevented from increasing significantly.

FIG. 12 shows an output terminal having a minimum linear distance in consideration of the linear distance on the board between each output terminal of the preceding scan register and the scan data input terminal of the subsequent scan register shown in FIG. 6 is a flowchart illustrating a method of calculating a wiring distance on a substrate and selecting an output terminal having a minimum wiring distance instead of a method of selecting the output terminal. 12, the same steps as those in FIG. 11 are denoted by the same reference numerals, and the description thereof will be omitted. SD7g shown in FIG.
Is a step of calculating a wiring distance between each output terminal in the candidate list to be connected and the scan data input terminal of the subsequent scan register. SD7h is a step of scanning the output terminal of the preceding scan register having the shortest wiring distance by the subsequent scan register. This is a step of determining connection to the scan data input terminal of the register.

Hereinafter, FIG. 1 is replaced with step SD7 in FIG.
The wiring method when the processing method shown in FIG. 2 is used will be described.

When the pair of the scan register 23 and the scan register 24 is selected in the step SD4 shown in FIG. 10, a difference 0 of the load capacity is obtained in the step SD7a shown in FIG. Next, in step SD7b,
Since the difference between the load capacities is smaller than the fixed value α of 0.2 pF, it is determined to proceed to step SD7d.

Next, in step SD7d, the positive logic output terminal Q and the inverted logic output terminal NQ are registered in the connection candidate list, and in step SD7g, the positive logic output terminal Q and the inverted logic output terminal Q in the connection candidate list are registered. Logic output terminal N
The wiring distance between Q and the scan data input terminal of the subsequent scan register 24 is calculated. Since the wiring distance on the positive logic output terminal Q side is 60 μm and the wiring distance on the inverted logic output terminal NQ side is 50 μm, in step SD7h,
It is determined that the inverted logic output terminal NQ having the shortest wiring distance is connected to the scan data input terminal SI of the scan register 24. As a result, the final circuit has the same connection as the scan chain connection shown in FIG.

Therefore, the wiring 43C shown in FIG.
6, the wiring length can be made shorter than the wiring 43Z corresponding to the case where the conventional semiconductor integrated circuit design method shown in FIG. 6 is applied, so that the wiring area can be reduced.

Since the load on the positive logic output terminal Q of the scan register 21 does not increase, the AND gates 26 and A
Since the delay time of the signal reaching the ND gate 27 is prevented from significantly increasing and the load on the positive logic output terminal Q of the scan register 24 does not increase, the inverter 34 and the inverter 3 are connected from the positive logic output terminal Q of the scan register 24.
5 can be prevented from increasing significantly.

In the present embodiment, the value of the constant value α is set to 0.2 pF, but the same effect can be obtained by setting the value of α to a value of 0 pF or more.

(Fifth Embodiment) Hereinafter, a method for designing a semiconductor integrated circuit according to a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a flowchart showing a method for designing a semiconductor integrated circuit according to the fifth embodiment of the present invention. In FIG. 13, SE1 is a step of designating the connection order of the scan registers, SE2 is a step of selecting a pair of scan registers of the preceding stage and the succeeding stage, and SE3 is a driving capability of the output terminal of the preceding stage of the scanning register which is the maximum. A step of selecting one output terminal; SE4, a step of determining an output terminal of the preceding scan register to be connected to the scan data input terminal of the subsequent scan register; SE5, whether or not processing of all pairs of the scan registers is completed SE6 is a step of connecting the terminals determined in step SE4 to generate a scan chain.

The driving capability of the element used in the present embodiment is a parameter expressed in units of ns / pF, and is a parameter having the property that the greater the driving capability, the shorter the signal propagation time. This driving capability uses data for each element listed in the library.

FIG. 24 is a circuit diagram obtained by performing the arrangement and wiring processing shown in FIG. 13 on the semiconductor integrated circuit shown in FIG. FIG. 24 has been described in the third embodiment, and a description of each component will be omitted.

A process in which the scan registers are wired by sequentially performing the steps shown in FIG. 13 on the semiconductor integrated circuit before the generation of the scan chains shown in FIG. 21 will be described. First, in step SD1, the connection order of each scan register is changed to scan register 21 → scan register 22 → scan register 23 → scan register 24 → scan register 25 → scan out terminal 37.
Specify to connect in order.

Next, in step SE2, a pair of the scan register 21 and the scan register 22 is first selected.

Next, in step SE3, the positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 21 are read.
Select the terminal having the larger driving capability. For example, in the scan registers 21 to 25 in the present embodiment, it is assumed that the driving capability of the inverted logic output terminal NQ is greater than that of the positive logic output terminal Q.

Next, in step SE4, the inverted logic output terminal NQ having the maximum driving capability and the scan register 22 are connected.
Is determined to be connected to the scan data input terminal SI.

Next, in step SE5, since there are four remaining pairs of scan registers, the process returns to step SE2.

Next, in step SE2, a pair of the scan register 22 and the scan register 23 is selected.

Hereinafter, the processing from step SE3 to step SE5 will be referred to as scan register 22 and scan register 23.
, The drive capability of the inverted logic output terminal NQ of the scan register 22 is greater than the drive capability of the positive logic output terminal Q, and therefore the connection target output terminal is determined to be the inverted logic output terminal NQ.

Next, each processing from step SE3 to step SE5 is performed by the scan register 23 and the scan register 24.
, And the pair of scan register 24 and scan register 25, respectively.
In addition, since each drive capability of the inverted logic output terminal NQ of the scan register 24 is greater than each drive capability of the positive logic output terminal Q, each output terminal to be connected is determined as the inverted logic output terminal NQ.

Next, each processing from step SE3 to step SE5 is performed by the scan register 25 and the scan-out terminal 3
7, the drive capability of the inverted logic output terminal NQ of the scan register 25 is greater than the drive capability of the positive logic output terminal Q, so the output terminal to be connected is determined as the inverted logic output terminal NQ.

Next, in step SE5, all pairs of scan registers have been processed, so the flow proceeds to step SE6.

In step SE6, the wiring process between the output terminal Q or NQ of the preceding scan register determined to be connected in step SE4 and the scan data input terminal SI or scan out terminal 37 of the subsequent scan register is performed. 24, the wirings 41C to 41C shown in FIG.
A scan chain connected by 45C is generated.

In the scan register 23 shown in FIG. 24 connected by the above wiring processing, even if the load capacitances of the positive logic output terminal Q and the inverted logic output terminal NQ have the same value,
Since the inverted logic output terminal NQ having a large driving capability is connected to the scan data input terminal SI of the scan register 24, an increase in the load of the positive logic output terminal Q of the scan register 24 can be avoided. From A
It is possible to prevent the delay time of the signal reaching the ND gate 30 and the delay time of the signal reaching the inverter 33 from the inverted logic output terminal NQ from increasing.

The flowchart shown in FIG. 14 shows whether or not there is an unconnected output terminal before selecting the output terminal having the maximum driving capability among the output terminals of the preceding stage scan register in step SE3 shown in FIG. SE for determining whether
3A and a step SE3B of selecting one of the unconnected output terminals having the highest driving capability when there is a connected output terminal. Accordingly, if there is an unconnected output terminal at each output terminal of the preceding scan register, it is possible to reliably suppress the increase in the delay time of the signal of the scan register without determining the driving capability of the preceding scan register. it can.

Only the differences from the wiring process shown in FIG. 13 when the respective steps shown in FIG. 14 are performed on the semiconductor integrated circuit before the scan chain wiring shown in FIG. 21 will be described.

In the pair of the scan register 22 and the scan register 23, the inverted logic output terminal NQ is connected to the scan data input terminal SI of the subsequent scan register 23 regardless of the driving capability of the unconnected inverted logic output terminal NQ of the scan register 22. , And in the pair of the scan register 25 and the scan-out terminal 37, the unconnected positive logic output terminal Q
, The positive logic output terminal Q is connected to the scan-out terminal 37.

(Sixth Embodiment) Hereinafter, a method for designing a semiconductor integrated circuit according to a sixth embodiment of the present invention will be described with reference to the drawings. First, from one output terminal of the scan register to another register, external output, ROM or RAM
, The difference between the delay time of the connection path with the longest signal delay time and the cycle time of one clock among the connection paths on the combinational circuit reaching the above is called the design margin of the output terminal of the scan register. Further, in the present embodiment, the reduction in the design margin of the output terminal of the preceding scan register due to the connection between the output terminal of the preceding scan register and the scan data input terminal of the succeeding scan register is uniformly reduced to 1 ns for convenience. Suppose that
Here, the delay time of the signal on the connection path is a value obtained by integrating the propagation times of the elements registered in the library, and the value of the design margin of the unconnected output terminal is infinite.

FIG. 15 is a flowchart showing a method for designing a semiconductor integrated circuit according to the sixth embodiment of the present invention.
In FIG. 15, steps SF1 to SF4, SF8 and SF
Reference numeral 9 denotes steps SA1 to SA4 and SA8 described in FIG.
And SA9, and the corresponding steps have the same contents. SF5 is a step of calculating the design margin of each output terminal of the preceding scan register, SF6 is a step of selecting one of the output terminals of the preceding scan register that maximizes the design margin, and SF7 is a subsequent step. Is a step of determining the output terminal of the preceding scan register to be connected to the scan data input terminal of the scan register. In step SF7, the output terminal of the preceding scan register selected in the previous step SF6 is set as a connection target.

FIG. 24 is a circuit diagram obtained by performing the arrangement and wiring processing shown in FIG. 15 on the semiconductor integrated circuit shown in FIG. FIG. 24 has been described in the third embodiment, and a description of each component will be omitted.

A process in which the scan registers are wired by sequentially performing the steps shown in FIG. 15 on the semiconductor integrated circuit before the generation of the scan chains shown in FIG. 21 will be described. First, in step SF1, the connection order of each scan register is changed to scan register 21 → scan register 22 → scan register 23 → scan register 24 → scan register 25 → scan out terminal 37.
Specify to connect in order.

Next, in step SF2, scan registers 21 to 25, AND gates 26 to 32, and inverters 33 to 35 are arranged, and in step SF3, wiring processing of each element other than scan registers 21 to 25 is performed. Do.

Next, in step SF4, after the pair of the scan register 21 and the scan register 22 is first selected, in the next step SF5, the scan register 2 is selected.
The design margins of the positive logic output terminal Q and the inverted logic output terminal NQ are calculated. It is assumed that the design margin of the positive logic output terminal Q is 1 ns, and the design margin of the inverted logic output terminal NQ is 3 ns.

Then, in step SF6, after selecting the inverted logic output terminal NQ having the maximum design margin value from the calculation result in step SF5, in the next step SF7, the selected inverted logic output terminal NQ is connected to the subsequent stage. Is determined to be connected to the scan data input terminal SI of the scan register 22.

Next, in step SF8, the remaining four scan register pairs remain.
Return to

Next, in step SF4, a pair of the scan register 22 and the scan register 23 is selected.

Table 5 below shows a list of design margins of the positive logic output terminal Q and the inverted logic output terminal NQ of the preceding scan register for each adjacent scan register. Here, the unit of the design margin is ns.

[0227]

[Table 5]

Hereinafter, each process from step SF5 to step SF8 will be referred to as scan register 22 and scan register 23.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 22 as shown in [Table 5].
Are 4 ns and infinity, respectively, so that the output terminal to be connected is determined to be the inverted logic output terminal NQ with the maximum design margin.

Next, each process from step SF5 to step SF8 is performed by the scan register 23 and the scan register 24.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 23 as shown in [Table 5].
Since the design margin values are 2 ns and 4 ns, respectively, the output terminal to be connected is determined to be the inverted logic output terminal NQ that maximizes the design margin.

Next, each processing from step SF5 to step SF8 is performed by the scan register 24 and the scan register 25.
, The positive logic output terminal Q and the inverted logic output terminal NQ of the scan register 24 as shown in [Table 5].
Are 0.5 ns and 2 ns, respectively, so that the output terminal to be connected is determined to be the inverted logic output terminal NQ that maximizes the design margin.

Next, each processing from step SF5 to step SF8 is performed by the scan register 25 and the scan-out terminal 3
7, a positive logic output terminal Q and an inverted logic output terminal N of the scan register 25 are provided as shown in [Table 5].
Since the design margin values of Q are infinity and 5 ns, respectively, the output terminal to be connected is determined to be the positive logic output terminal Q with the maximum design margin.

Next, since all the pairs of scan registers have been processed, the flow advances to the next step SF9 based on the determination in step SF8.

In step SF9, each wiring process is performed between the output terminal Q or NQ of the preceding scan register determined to be connected in step SF7 and the scan data input terminal SI or scan out terminal 37 of the subsequent scan register. 24, respectively, to obtain the wiring 4 shown in FIG.
Generate scan chains connected by 1C to 45C.

In the present embodiment, since it is assumed that the amount of reduction in the design margin of the output terminal due to the scan chain connection is 1 ns, the scan registers 21 and 23 after the scan chain generation shown in FIG.
And the design margin values of the inverted logic output terminal NQ of the scan register 24 are 2 ns, 3 ns, and 1 n, respectively.
s.

In the case of the scan chain according to the conventional semiconductor integrated circuit design method shown in FIG. 26, the value of each design margin of the positive logic output terminal Q of the scan register 21, scan register 23 and scan register 24 is
Since they are 0 ns, 1 ns, and -0.5 ns, respectively,
The scan register 21 has no margin, and the scan register 24 has a timing violation.

Therefore, by using the method of designing a semiconductor integrated circuit described in the present embodiment, it is possible to prevent the problem of timing constraint due to scan chain connection from occurring.

Further, since the reduction amount of the design margin due to the scan chain connection is 1 ns, any output terminal whose margin amount in Table 5 is larger than 1 ns is larger than 0 ns even after the scan chain connection. Since the same effect can be obtained as the margin amount, it is not always necessary to select only the output terminal having the maximum margin amount when selecting the output terminal.

(Seventh Embodiment) Hereinafter, a method for designing a semiconductor integrated circuit according to a seventh embodiment of the present invention will be described with reference to the drawings. The difference between the present embodiment and the sixth embodiment is that in the sixth embodiment, the output of the preceding scan register is connected to the output terminal of the preceding scan register and the scan data input terminal of the succeeding scan register. Although the amount of decrease in the design margin of the terminal is assumed to be 1 ns uniformly, in the present embodiment, the design margin of the case where the output terminal of the preceding scan register is connected to the scan data input terminal of the succeeding scan register is assumed. The reduction was determined by calculation.

FIG. 16 is a flowchart showing a method for designing a semiconductor integrated circuit according to the seventh embodiment of the present invention.
In FIG. 16, steps SG1 to SG4, SG8 and SG
Reference numeral 9 denotes steps SA1 to SA4 and SA8 described in FIG.
And SA9, and the corresponding steps have the same contents. SG5A is a step of selecting one output terminal of the scan register, and SG5B is a step of selecting SG5.
Connecting the output terminal selected in A to the scan data input terminal of the subsequent scan register, SG5
C is a step of calculating the design margin of the output terminal connected in step SG5B, SG5D is a step of determining whether or not calculation of all output terminals of the selected scan register is completed, and SG6 is a step of determining whether the calculation of the preceding scan register is completed. SG1 is a step of selecting one of the output terminals having the maximum design margin, and SG7 is a step of determining an output terminal of the preceding scan register to be connected to the scan data input terminal of the subsequent scan register. In step SG7, the output terminal of the preceding scan register selected in the previous step SG6 is set as a connection target.

FIG. 24 is a circuit diagram obtained by performing the arrangement and wiring processing shown in FIG. 16 on the semiconductor integrated circuit shown in FIG. FIG. 24 has been described in the third embodiment, and a description of each component will be omitted.

A process in which the scan registers are wired by sequentially performing the steps shown in FIG. 16 on the semiconductor integrated circuit before the generation of the scan chain shown in FIG. 21 will be described. First, in step SG1, the connection order of the scan registers is changed to scan register 21, scan register 22, scan register 23, scan register 24, scan register 25, and scan out terminal 37.
Specify to connect in order.

Next, in step SG2, the scan registers 21 to 25, AND gates 26 to 32, and inverters 33 to 35 are arranged, and in step SG3, wiring processing for each element other than the scan registers 21 to 25 is performed. Do.

Next, in step SG4, after the pair of the scan register 21 and the scan register 22 is first selected, the positive logic output terminal Q of the scan register 21 is selected in the next step SG5A.

Next, in step SG5B, assuming that the selected positive logic output terminal Q and the scan data input terminal SI of the scan register 22 have been connected, the next step S5B
In G5C, the design margin of the positive logic output terminal Q of the scan register 21 is calculated. As a result, it is assumed that the design margin of the positive logic output terminal Q is 1 ns.

Next, in the determination process of step SG5D,
Since the unprocessed inverted logic output terminal NQ remains, the process returns to step SG5A.

In step SG5A, after selecting the inverted logic output terminal NQ, in step SG5B, the inverted logic output terminal NQ is connected to the scan data input terminal SI of the scan register 22.

Next, in step SG5C, the inverted logic output terminal NQ of the scan register 21 assumed to be connected
Is calculated, and the design margin is 3 ns.
And

Next, in the determination process of step SG5D,
Since there are no unprocessed output terminals, the process proceeds to step SG6.

Next, in step SG6, step SG5C
After selecting the inverted logic output terminal NQ at which the value of the design margin is maximum from the calculation result in step SG7, in the next step SG7,
It is determined that the selected inverted logic output terminal NQ is to be connected to the scan data input terminal SI of the subsequent scan register 22.

Next, in step SG8, since the remaining four scan register pairs remain, the process proceeds to step SG4.
Return to

Next, in step SG4, a pair of the scan register 22 and the scan register 23 is selected.
[Table 6] shown below is calculated on the assumption that the positive logic output terminal Q or the inverted logic output terminal NQ of the preceding scan register is connected to the scan data input terminal of the subsequent scan register for each adjacent scan register. It is a list of the respective design margins. The unit of the design margin is n
s.

[0252]

[Table 6]

Hereinafter, each process from step SG5A to step SG8 will be referred to as scan register 22 and scan register 2
3, the positive logic output terminal Q and the inverted logic output terminal N of the scan register 22 as shown in [Table 6].
Since the design margin value of Q becomes 3 ns and infinity, respectively, the output terminal to be connected is determined to be the inverted logic output terminal NQ with the maximum design margin.

Next, each process from step SG5A to step SG8 is performed by the scan register 23 and the scan register 2
4, the positive logic output terminal Q and the inverted logic output terminal N of the scan register 23 as shown in [Table 6].
Since the design margin values of Q are 1 ns and 3 ns, respectively, the output terminal to be connected is determined as the inverted logic output terminal NQ with the maximum design margin.

Next, each processing from step SG5A to step SG8 is performed by the scan register 24 and the scan register 2
5, the positive logic output terminal Q and the inverted logic output terminal N of the scan register 24 as shown in [Table 6].
The design margin values of Q are -0.5 ns and 1 n, respectively.
Therefore, the output terminal to be connected is determined to be the inverted logic output terminal NQ that maximizes the design margin.

Next, when the processes from step SG5A to step SG8 are performed on the pair of the scan register 25 and the scan-out terminal 37, as shown in [Table 6], the positive logic output terminal Q of the scan register 25 and the inverted Since the design margin values of the logic output terminal NQ are infinite and 3 ns, respectively, the output terminal to be connected is determined as the positive logic output terminal Q having the largest design margin.

Next, since all the pairs of scan registers have been processed, the flow advances to the next step SG9 based on the judgment in the step SG8.

In step SG9, each wiring process between the output terminal Q or NQ of the preceding scan register determined to be connected in step SG7 and the scan data input terminal SI or scan out terminal 37 of the succeeding scan register. 24, respectively, to obtain the wiring 4 shown in FIG.
Generate scan chains connected by 1C to 45C.

In this embodiment, the values of the design margins of the scan register 21, scan register 23, and inverted logic output terminal NQ of the scan register 24 after the generation of the scan chain shown in FIG.
s and 1 ns.

In the case of the scan chain according to the conventional semiconductor integrated circuit design method shown in FIG. 26, the value of each design margin of the positive logic output terminal Q of the scan register 21, scan register 23 and scan register 24 is
Since they are 0 ns, 1 ns, and -0.5 ns, respectively,
The scan register 21 has no margin, and the scan register 24 has a timing violation.

Therefore, when the method of designing a semiconductor integrated circuit according to the present embodiment is used, it is assumed that each output terminal of the preceding scan register is connected to the input terminal of the succeeding scan register, and the preceding scan register is connected. Since the design margin is calculated, the problem of the timing constraint due to the scan chain connection is less likely to occur.

In addition, if the output terminal has a margin amount larger than 0 ns in Table 6 showing the design margin amount after the scan chain connection, the same effect can be obtained. It is not always necessary to select only the output terminal having the largest margin.

(Eighth Embodiment) Hereinafter, a method of designing a semiconductor integrated circuit according to an eighth embodiment of the present invention will be described with reference to the drawings. FIG. 17 is a flowchart showing a method for designing a semiconductor integrated circuit according to the eighth embodiment of the present invention. In FIG. 17, SH1 is a step of designating the connection order of the scan registers, SH2 is a step of selecting a pair of scan registers of the previous stage and the subsequent stage, and SH3 is an output terminal from the scan data input terminal among the output terminals of the previous stage scan register The output terminal with the largest delay value to the terminal
SH4 is a step of determining the output terminal of the preceding scan register to be connected to the scan data input terminal of the subsequent scan register, and SH5 is determining whether or not the processing of all the pairs of scan registers is completed. Step SH6 is a step of connecting the terminals determined in step SH4 to generate a scan chain. In step SH2, the pair of the scan register and the scan-out terminal at the last stage is also treated as the pair of scan registers in the scan chain.

FIGS. 18 and 19 are timing charts showing signal changes at the terminals of the scan registers 22 to 24 in the circuit shown in FIG. 22. SI indicates a signal change at the scan data input terminal SI of the scan register 22; CK, 23. CK and 24. CK represents a signal change at the clock input terminals of the scan registers 22, 23, and 24, respectively. NQ, 23. NQ and 24. NQs are scan registers 22, 23, respectively.
24 indicates a signal change at the inverted logic output terminal NQ,
2. Q, 23. Q and 24. Q represents a signal change at the positive logic output terminal Q of the scan registers 22, 23, 24, respectively. In FIG. 21, scan registers 21 and
It is assumed that macrocells A and 2 are used for macrocells A and macrocells B are used for scan registers 23 and 24. Both macrocell A and macrocell B are logically shown in FIG.
0 is a scan register. Macrocell A is SI
The delay value of the signal input from the terminal to the Q terminal or the NQ terminal is 3 ns and 1 ns, respectively.
Indicates that the delay value of the signal input from the SI terminal to the Q terminal or the NQ terminal is 1 ns and 3 ns, respectively. In addition,
In the present embodiment, for the sake of convenience, the description will be made assuming that each wiring has no delay.

FIG. 22 is a circuit diagram after the processing shown in FIG. 17 has been performed on the semiconductor integrated circuit before the wiring shown in FIG. 21. Reference numerals 41A to 45A shown in FIG. 22 indicate wiring connecting the scan chains. .

For the semiconductor integrated circuit of FIG. 21, first,
In step SH1, the connection order of the scan registers is changed to scan register 21 → scan register 22 → scan register 23 → scan register 24 → scan register 2
Specify to connect in the order of 5. Next, in step SH2, the scan register 21 and the scan register 22
Select a pair with Next, in step SH3, the output terminal Q having the maximum delay value of 3 ns of the signal input from the SI terminal is selected from the output terminals Q and NQ of the scan register 21. Next, in Step SH4, Step SH3
It is determined that the output terminal Q of the scan register 21 selected in the step 2 is connected to the SI terminal of the scan register 22. Next, in step SH5, the pairs of scan registers are still (22, 23), (23, 24), (24, 2).
Since a total of four (5) and (25, scan-out terminal 37) remain, the process proceeds to step SH2.

In step SH2, scan register 2
Select 2,23 pairs. Next, in step SH3, of the output terminals Q and NQ of the scan register 22,
The maximum output terminal Q is selected when the delay value of the signal input from the SI terminal is 3 ns. Next, in step SH4, it is determined that the output terminal Q of the scan register 22 selected in step SH3 is connected to the SI terminal of the scan register 23. Next, in step SH5, the scan register pairs are (23, 24), (24, 25) and (2).
5, since the scan-out terminal 37) remains, the process proceeds to step SH2.

Similarly, in the pair of scan registers 23 and 24, it is determined that the output terminal NQ of the scan register 23 and the SI terminal of the scan register 24 are connected. It is determined that the output terminal NQ of the register 24 is connected to the SI terminal of the scan register 25. In the pair of the scan register 25 and the scan-out terminal 37, the output terminal Q of the scan register 25 and the scan-out terminal 37 are connected. It is decided to connect. Thereafter, in step SH5, all the pairs of scan registers have been processed, so the process proceeds to step SH6.

In step SH6, a wiring process is performed between the output terminal determined to be connected in step SH4 and the SI terminal or the scan-out terminal 37 of the subsequent scan register to perform scan chain connection.

By the above operation, scan register 22
Scan register 23 for signals input from SI terminal
The delay time to the SI terminal is 3 ns in the present embodiment while the circuit obtained by the conventional method shown in FIG. 26 is 1 ns, and the timing problem due to the skew of the clock signal can be suppressed as compared with the conventional method. . Similarly, the delay time of a signal input from the SI terminal of the scan register 23 to the SI terminal of the scan register 24 and the delay time of a signal input from the SI terminal of the scan register 24 to the SI terminal of the scan register 25 are The circuit obtained by the conventional method shown in FIG. 26 is 1 ns, whereas in the present embodiment, it is 3 ns.
Timing problems due to variations in clock signals can be suppressed. Note that even if the scan data input to each scan register is delayed, the scan data at the time when the clock signal is input is fetched, so that a problem such as missing of the scan data does not occur.

Hereinafter, a specific description will be given based on a timing chart. FIG. 18 shows scan registers 22 to 24.
4 is a timing chart in an ideal case where there is no variation in the time when the clock signal reaches the clock input terminal of FIG. Scan data input terminal 22. It is assumed that 1 → 0 → 1 is input to SI from the Q terminal of the scan register 21 at the preceding stage in synchronization with the clock. The Q terminal of the scan register 22, the NQ terminal of the scan register 23, and the N terminal of the scan register 24
As the signal at the Q terminal, the data fetched with a delay of 3 ns after the input of the clock signal is output to the SI terminal of the subsequent scan register. Therefore, the clock signal 3
The signals at the Q terminal of the scan register 22, the NQ terminal of the scan register 23, and the NQ terminal of the scan register 24 after the cycle are set to 1 because the input data is shifted to the scan registers 22 to 24 for each clock. 0,0.

FIG. 19 is a timing chart showing a case where the time when the clock signal reaches the scan register 23 is delayed by 2 ns from the time when the clock signal reaches the scan registers 22 and 24. In this case, the Q terminal of the scan register 22 changes with a delay of 3 ns from the clock signal of the scan register 22, so that the scan register 2
Data is input to the SI terminal 3 with a delay of 1 ns from the clock signal of the scan register 23, and the next data that has just changed is not taken in.
As a result, the signals at the Q terminal of the scan register 22, the NQ terminal of the scan register 23, and the NQ terminal of the scan register 24 after three cycles of the clock signal are 1, respectively.
It becomes 0,0 and operates normally.

As described above, in this embodiment, the timing problem with respect to the variation of the clock signal can be less likely to occur than in the conventional method.

Although the present embodiment has been described using a scan register having two output terminals, a positive logic output terminal Q and an inverted logic output terminal NQ, the positive logic output terminal Q
Similar effects can be obtained for a scan register having three or more output terminals including an output terminal such as a scan data output terminal in addition to the inverted logic output terminal NQ.

Further, as long as the output terminal has a delay value of 2 ns or more in clock variation, the same effect can be obtained, so that the output terminal does not necessarily have to have the maximum delay value.

The delay value of the signal from the SI terminal of the scan register to each output terminal uses the data described in the library, but the data input terminal 1 shown in FIG.
It may be a delay value of a signal from 1 to each output terminal.

[0277]

【The invention's effect】

[0278]

[0279] According to a method of designing a semiconductor integrated circuit according to the invention of claim 1, an output terminal and a second of the first storage element
Shortest linear distance from the scan data input terminal of the storage element
Connected between the first and second storage elements.
Since the wiring is shortened, the wiring area can be reduced. That
In addition, since the output terminal having the smallest fan-out number connected to each output terminal of the first storage element is selected and wired, an increase in the load capacitance of the circuit in the normal operation mode is avoided. An increase in signal delay time can be suppressed.

According to the method of designing a semiconductor integrated circuit according to the second aspect of the present invention, the output terminal of the first storage element is connected to the second terminal.
Shortest linear distance from the scan data input terminal of the storage element
Connected between the first and second storage elements.
Since the wiring is shortened, the wiring area can be reduced. That
In addition, since the output terminal connected to each output terminal of the first storage element and having the smallest load capacitance is selected and wired, an increase in the load capacitance of the circuit in the normal operation mode is avoided. Can be suppressed from increasing.

[0281]

[0282] According to a method of designing a semiconductor integrated circuit according to the invention of claim 3, the output terminal and the second of the first storage element
Shortest wiring distance to scan data input terminal of storage element
Connected between the first and second storage elements.
Since the wiring is reliably shortened, the wiring area can be further reduced.
You. In addition, since the output terminal having the smallest fanout number among the output terminals connected to each output terminal of the first storage element is selected and wired, an increase in the load capacitance of the circuit in the normal operation mode is avoided. In addition, it is possible to suppress an increase in signal delay time.

According to the method of designing a semiconductor integrated circuit according to the fourth aspect of the present invention, the effect of the method of designing a semiconductor integrated circuit according to the third aspect of the present invention can be obtained, and each output terminal of the first storage element can be obtained. Since the output terminal with the smallest load capacity is selected and wired, the increase in the load capacity of the circuit in the normal operation mode is avoided, so that it is possible to suppress the increase in the signal delay time. it can.

According to the method of designing a semiconductor integrated circuit according to the fifth aspect of the present invention, among the output terminals connected to each output terminal of the first storage element, the output terminal having the smallest fan-out number is selected and wired. Since an increase in the load capacitance of the circuit in the normal operation mode is avoided, an increase in the signal delay time can be suppressed.

[0285] According to a method of designing a semiconductor integrated circuit according to the invention of claim 6, on the effect of the method of designing a semiconductor integrated circuit according to the invention of claim 5 is obtained, and an output terminal of the first storage element Since the scan data input terminal of the second storage element is connected with the shortest linear distance, the wiring between the first and second storage elements is shortened, so that the wiring area can be reduced.

According to the method of designing a semiconductor integrated circuit according to the seventh aspect of the present invention, the effect of the method of designing a semiconductor integrated circuit according to the fifth aspect of the present invention can be obtained, and the output terminal of the first storage element can be used. Since the scan data input terminal of the second storage element is connected with the shortest wiring distance, the wiring between the first and second storage elements is reliably reduced, so that the wiring area can be further reduced.

[0287]

According to the method of designing a semiconductor integrated circuit according to the eighth aspect of the present invention, the output terminal connected to each output terminal of the first storage element with the smallest load capacitance is selected and wired. Since an increase in the load capacitance of the circuit in the operation mode is avoided, it is possible to suppress an increase in signal delay time.

According to the method of designing a semiconductor integrated circuit of the ninth aspect of the present invention, the effect of the method of designing a semiconductor integrated circuit of the eighth aspect of the present invention can be obtained, and the output terminal of the first storage element can be used. Since the scan data input terminal of the second storage element is connected with the shortest linear distance, the wiring between the first and second storage elements is shortened, so that the wiring area can be reduced.

According to the semiconductor integrated circuit design method of the tenth aspect , the effect of the semiconductor integrated circuit design method of the eighth aspect can be obtained, and the output terminal of the first storage element and Since the scan data input terminal of the second storage element is connected with the shortest wiring distance, the wiring between the first and second storage elements is reliably shortened.
The wiring area can be further reduced.

According to the semiconductor integrated circuit designing method of the eleventh aspect of the present invention, the output terminal having the largest driving capability among the output terminals connected to each output terminal of the first storage element is selected and wired. Since the delay time is shortened even with the terminal having the load capacitance of, the increase in the delay time of the signal can be suppressed.

According to the semiconductor integrated circuit designing method of the twelfth aspect of the present invention, the output terminal having the largest driving capability among the output terminals connected to each output terminal of the first storage element is selected and wired. Since the unconnected output terminal is preferentially connected, an increase in signal delay time can be reliably suppressed.

According to the method of designing a semiconductor integrated circuit according to the thirteenth or fourteenth aspect , the output terminal having the largest design margin among the output terminals connected to each output terminal of the first storage element is selected and wired. In addition, since it is possible to suppress an increase in the delay time of a signal, it is unlikely that a problem relating to an operation timing occurs.

According to the method of designing a semiconductor integrated circuit according to the invention of claim 15 or 16 , the method of claim 13 or 14 is provided.
In addition to obtaining the effect of the method of designing a semiconductor integrated circuit according to the invention, the design margin of the connection to each output terminal of the first storage element is reduced by the second output terminal of the first storage element. After calculating assuming that they are connected to the respective storage elements, the maximum design margin is selected and wired, so that it is possible to reliably suppress an increase in signal delay time. Is less likely to occur.

According to the method of designing a semiconductor integrated circuit according to the seventeenth aspect , the output terminal of the first storage element at which the delay value of the signal input from the scan data input terminal of the first storage element becomes maximum. Is connected to the scan data input terminal of the second storage element, so that data is input to the scan data input terminal of the second storage element with a delay.
As a result, data destruction due to clock skew on the scan chain can be suppressed.

According to the method of designing a semiconductor integrated circuit according to the eighteenth aspect of the present invention, the effect of the method of designing a semiconductor integrated circuit according to the nineteenth aspect of the present invention can be obtained, and the scan data input of the first storage element can be performed. Since the output terminal of the first storage element and the scan data input terminal of the second storage element, where the delay value of the signal input from the terminal is equal to or more than a predetermined amount, are connected, the range of selection of the output terminal is expanded. be able to.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a method for designing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a process of determining the number of fan-outs in the method for designing a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a flowchart illustrating a process of determining a load capacitance in the method of designing a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 4 is a flowchart illustrating a method for designing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a flowchart illustrating a process of determining the number of fan-outs in a method for designing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a flowchart illustrating a process of determining a load capacitance in a method of designing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 7 is a flowchart illustrating a method of designing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 8 is a flowchart illustrating a process of determining a linear distance between terminals in a method of designing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 9 is a flowchart illustrating a process of determining a wiring distance between terminals in a method of designing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 10 is a flowchart illustrating a method of designing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 11 is a flowchart illustrating a process of determining a linear distance between terminals in a method for designing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 12 is a flowchart illustrating a process of determining a wiring distance between terminals in a method of designing a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 13 is a flowchart illustrating a method of designing a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 14 is a flowchart illustrating a process of determining an unconnected output terminal in a method for designing a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 15 is a flowchart illustrating a method of designing a semiconductor integrated circuit according to a sixth embodiment of the present invention.

FIG. 16 is a flowchart showing a method for designing a semiconductor integrated circuit according to a seventh embodiment of the present invention.

FIG. 17 is a flowchart illustrating a method of designing a semiconductor integrated circuit according to an eighth embodiment of the present invention.

FIG. 18 is an ideal timing chart of a clock signal in a semiconductor integrated circuit according to an eighth embodiment of the present invention.

FIG. 19 is a timing chart when a variation occurs in a clock signal in a semiconductor integrated circuit according to an eighth embodiment of the present invention.

FIG. 20 is a circuit diagram showing a scan register for performing a scan test.

FIG. 21 is a diagram showing a semiconductor integrated circuit before a scan chain is generated.

FIG. 22 is a circuit diagram obtained by using the semiconductor integrated circuit designing method according to the first or eighth embodiment of the present invention.

FIG. 23 is a circuit diagram obtained by using the method for designing a semiconductor integrated circuit according to the second embodiment of the present invention.

FIG. 24 is a circuit diagram obtained by using the method of designing a semiconductor integrated circuit according to the third to seventh embodiments of the present invention.

FIG. 25 is a flowchart showing a conventional method of designing a semiconductor integrated circuit.

FIG. 26 is a circuit diagram obtained by using a conventional semiconductor integrated circuit design method.

FIG. 27 is an ideal timing chart of a clock signal in a conventional semiconductor integrated circuit.

FIG. 28 is a timing chart when a clock signal in a conventional semiconductor integrated circuit varies.

[Description of Signs] 10 scan register 11 data input terminal 12 scan data input terminal 13 clock terminal 14 input switching terminal 15 positive logic output terminal 16 inverted logic output terminal 20A layout wiring area 20B formation area 21 scan register 22 scan register 23 scan register 24 scan register 25 scan register 26 AND gate 27 AND gate 28 AND gate 29 AND gate 30 AND gate 31 AND gate 32 AND gate 33 inverter 34 inverter 35 inverter 36 scan-in terminal 37 scan-out terminal SI scan data input terminal Q positive logic output Terminal NQ Inverted logic output terminal

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 21/822 H01L 21/82 W 27/04 27/04 T (56) References JP-A-7-152812 (JP, A) JP-A-9-69117 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/28 G06F 17/50 H01L 21/82 H01L 21/822

Claims (18)

(57) [Claims] An output terminal of the first storage element having a plurality of output terminals; and an output terminal of a second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit for connecting a scan data input terminal, wherein a linear distance on a substrate between each output terminal of the first storage element and the scan data input terminal of the second storage element is calculated. A distance calculation step of calculating a minimum value of the linear distances, and a distance comparison step of comparing the minimum value with a linear distance other than the minimum value; and a linear distance other than the minimum value and the minimum value. When there is an output terminal of the first storage element in which the difference is equal to or less than a predetermined value,
Calculate the number of fan-outs between the output terminal of the first storage element where the linear distance is minimum and the output terminal of the first storage element where the difference between the minimum value of the linear distance is equal to or less than a predetermined value. Calculating the output terminal of the first storage element calculated in the calculation step, the output terminal having the smallest fan-out number is the scan data input terminal of the second storage element.
Is determined as a terminal to be connected to the minimum value and the minimum value and a value other than the minimum value.
The first storage element, wherein a difference from the linear distance is equal to or less than a predetermined value
If there is no output terminal, before the straight line distance becomes minimum
The output terminal of the first storage element is connected to the switch of the second storage element.
Determine the terminal to be connected to the scan data input terminal, and
A connection step of connecting a fixed terminal and a scan data input terminal of the second storage element. 2. The method according to claim 1, wherein one of the plurality of output terminals in the first storage element having a plurality of output terminals and a second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit for connecting a scan data input terminal, wherein a linear distance on a substrate between each output terminal of the first storage element and the scan data input terminal of the second storage element is calculated. A distance calculation step of calculating a minimum value of the linear distances, and a distance comparison step of comparing the minimum value with a linear distance other than the minimum value; and a linear distance other than the minimum value and the minimum value. When there is an output terminal of the first storage element in which the difference is equal to or less than a predetermined value,
A capacity for calculating a load capacity for the output terminal of the first storage element in which the difference between the output terminal of the first storage element in which the linear distance is minimum and the minimum value of the linear distance is equal to or less than a predetermined value; A calculating step, of the output terminals of the first storage element calculated in the capacity calculating step, the output terminal with the minimum load capacitance being a scan data input terminal of the second storage element.
The terminal to be connected is determined, and the minimum value and a value other than the minimum value are determined.
The first storage element whose difference from the line distance is equal to or less than a predetermined value.
When there is no output terminal, the linear distance is minimized.
The output terminal of the first storage element is connected to the scan of the second storage element.
Terminal to be connected to the scan data input terminal.
Method for designing a semiconductor integrated circuit, characterized in that a connecting step of connecting the terminal and the scan data input terminal of said second storage element. 3. A first storage element having a plurality of output terminals and one output terminal of the plurality of output terminals in the first storage element, and a second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit for connecting a scan data input terminal to a scan data input terminal, wherein each output terminal of the first storage element is connected to a scan data input terminal of the second storage element. Calculating a distance; calculating a minimum value of the wiring distances; and comparing the minimum value with a wiring distance other than the minimum value; and a wiring distance other than the minimum value and the minimum value. Is the output terminal of the first storage element whose difference is equal to or less than a predetermined value, the output terminal of the first storage element having the minimum wiring distance and the minimum value of the wiring distance Difference A calculation step of calculating the number of fan-outs with the output terminal of the first storage element that is equal to or less than a fixed value, and the number of fan-outs of the output terminals of the first storage element calculated in the calculation step is the smallest The output terminal is a scan data input terminal of the second storage element.
Is determined as a terminal to be connected to the minimum value and the minimum value and a value other than the minimum value.
The first storage element, wherein a difference from a wiring distance is equal to or less than a predetermined value
If there is no output terminal before the wiring distance becomes minimum
The output terminal of the first storage element is connected to the switch of the second storage element.
It determines a terminal to be connected to the candy over data input terminal, the determined
A connection step of connecting a fixed terminal and a scan data input terminal of the second storage element. 4. An output terminal of one of the plurality of output terminals of the first storage element having a plurality of output terminals and a second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit for connecting a scan data input terminal to a scan data input terminal, wherein each output terminal of the first storage element is connected to a scan data input terminal of the second storage element. Calculating a distance; calculating a minimum value of the wiring distances; and comparing the minimum value with a wiring distance other than the minimum value; and a wiring distance other than the minimum value and the minimum value. When there is an output terminal of the first storage element, the difference of which is equal to or less than a predetermined value,
Calculate the load capacitances for the output terminal of the first storage element where the wiring distance is minimum and the output terminal of the first storage element where the difference between the minimum value of the wiring distance is equal to or less than a predetermined value. A capacitance calculation step, and among the output terminals of the first storage element calculated in the capacitance calculation step, the output terminal with the smallest load capacitance is used as a scan data input terminal of the second storage element.
The terminal to be connected is determined, and the minimum value and the wiring other than the minimum value are determined.
The first storage element whose difference from the line distance is equal to or less than a predetermined value.
When there is no output terminal, the wiring distance is minimized.
The output terminal of the first storage element is connected to the scan of the second storage element.
Terminal to be connected to the scan data input terminal.
Method for designing a semiconductor integrated circuit, characterized in that a connecting step of connecting the terminal and the scan data input terminal of said second storage element. 5. The first storage element having a plurality of output terminals and one of the plurality of output terminals in the first storage element, and the second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit for connecting a scan data input terminal, the method comprising: calculating a fan-out number of each output terminal of the first storage element; And a connection step of connecting an output terminal of the first storage element with the minimum fan-out number to a scan data input terminal of the second storage element. Circuit design method. 6. The storage device according to claim 1, wherein one of the plurality of output terminals in the first storage element having a plurality of output terminals, and the second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit for connecting to a scan data input terminal, the method comprising: calculating a fanout number of each output terminal of the first storage element; and calculating a minimum value of the fanout number. Calculating and comparing the minimum value and the number of fan-outs other than the minimum value; and the step of comparing the difference between the minimum value of the fan-out number and the number of fan-outs other than the minimum value with a predetermined value or less . One of the storage elements
When there is an output terminal, the output terminal of the first storage element having the minimum fan-out number and the output terminal of the first storage element having a difference between the minimum value of the fan-out number and a predetermined value or less. A distance calculation step for calculating a linear distance on the substrate between the first storage element and the scan data input terminal of the second storage element; and the linear distance among the output terminals of the first storage element calculated in the distance calculation step. Is the scan data input terminal of the second storage element.
Determine the terminal to be connected, the minimum value of the number of fan-out and
The difference between the fan-out number other than the minimum value and the
If there is no output terminal of the first storage element,
An output terminal of the first storage element having a small fan-out number
To the scan data input terminal of the second storage element.
A method of designing a semiconductor integrated circuit , comprising: determining a terminal to be connected; and connecting the determined terminal to a scan data input terminal of the second storage element. 7. An output terminal of one of the plurality of output terminals in the first storage element having a plurality of output terminals and a second storage element having a scan test function and having a scan data input terminal. A method of designing a semiconductor integrated circuit for connecting to a scan data input terminal, the method comprising: calculating a fanout number of each output terminal of the first storage element; and calculating a minimum value of the fanout number. Calculating and comparing the minimum value and the number of fan-outs other than the minimum value; and the step of comparing the difference between the minimum value of the fan-out number and the number of fan-outs other than the minimum value with a predetermined value or less . One of the storage elements
When there is an output terminal, the output terminal of the first storage element having the minimum fan-out number and the output terminal of the first storage element having a difference between the minimum value of the fan-out number and a predetermined value or less. A distance calculation step of calculating a wiring distance when the scan data input terminal of the second storage element is connected to the first storage element; and a wiring among the output terminals of the first storage element calculated in the distance calculation step. The output terminal having the minimum distance is used as the scan data input terminal of the second storage element.
Determine the terminal to be connected, the minimum value of the number of fan-out and
The difference between the fan-out number other than the minimum value and the
If there is no output terminal of the first storage element,
An output terminal of the first storage element having a small fan-out number
To the scan data input terminal of the second storage element.
A method of designing a semiconductor integrated circuit , comprising: determining a terminal to be connected; and connecting the determined terminal to a scan data input terminal of the second storage element. 8. An output terminal of one of the plurality of output terminals in the first storage element having a plurality of output terminals, and a second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit for connecting a scan data input terminal, wherein: a capacity calculation step of calculating a load capacity for each output terminal of the first storage element; An output terminal of the first storage element having the minimum load capacitance;
Connecting the scan data input terminal of the storage element to the scan data input terminal. 9. A method according to claim 1, wherein one of the plurality of output terminals in the first storage element having a plurality of output terminals, and the second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit that connects to a scan data input terminal, the method comprising: calculating a load capacitance for each output terminal of the first storage element; and obtaining a minimum value of the load capacitance. A capacity comparison step of comparing the minimum value with a load capacity other than the minimum value; and the first storage in which a difference between the minimum value of the load capacity and a load capacity other than the minimum value is equal to or less than a predetermined value. when the output terminal of the device Oh <br/> Ru, the first difference between the minimum value of the output terminal and the load capacitance of the first storage element to be the minimum load capacity is less than a predetermined value Output terminal of storage element A distance calculation step of calculating a linear distance between the scan data input terminal of the second storage element and the scan data input terminal on the substrate, and the linear distance of the output terminal of the first storage element calculated in the distance calculation step is The minimum output terminal is used as a scan data input terminal of the second storage element.
Determine the terminal to be connected, and determine the minimum value of the load capacitance and the minimum value.
Wherein the difference from the load capacity other than the value is equal to or less than a predetermined value.
If there is no output terminal of the storage element, the minimum load capacity
The output terminal of the first storage element,
Determine the terminal to be connected to the scan data input terminal of the element
And a connecting step of connecting the determined terminal to a scan data input terminal of the second storage element. 10. A first storage element having a plurality of output terminals and one output terminal of the plurality of output terminals of the first storage element, and a second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit that connects to a scan data input terminal, the method comprising: calculating a load capacitance for each output terminal of the first storage element; and obtaining a minimum value of the load capacitance. Te, the capacity comparing step of comparing the load capacity of the other outermost small value and outermost small value, the difference between the minimum value and the load capacitance other than the outermost minimum value of the load capacitance previous SL first equal to or less than a predetermined value when the output terminal of the storage element is Ah <br/> Ru, the minimum of the first difference between the minimum value of the output terminal and the load capacitance of the first storage element as a load capacitance is equal to or less than the predetermined value Output end of the storage element A distance calculation step of calculating a wiring distance when the scan data input terminal of the second storage element is connected to the scan data input terminal; and the wiring among the output terminals of the first storage element calculated in the distance calculation step The output terminal having the minimum distance is used as the scan data input terminal of the second storage element.
Determine the terminal to be connected, and determine the minimum value of the load capacitance and the minimum value.
Wherein the difference from the load capacity other than the value is equal to or less than a predetermined value.
If there is no output terminal of the storage element, the minimum load capacity
The output terminal of the first storage element,
Determine the terminal to be connected to the scan data input terminal of the element
And a connecting step of connecting the determined terminal to a scan data input terminal of the second storage element. 11. The first storage element having a plurality of output terminals and one of the plurality of output terminals of the first storage element, and the second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit for connecting a scan data input terminal, the method comprising: selecting an output terminal having a maximum drive capability among output terminals of the first storage element; A method for designing a semiconductor integrated circuit, comprising a connection step of connecting a scan data input terminal of a second storage element. 12. The connecting step determines whether an unconnected output terminal is present at an output terminal of the first storage element, and determines whether the unconnected output terminal exists when the unconnected output terminal is present. 12. The method of designing a semiconductor integrated circuit according to claim 11 , further comprising a step of selecting the output terminal having the maximum driving capability among the output terminals. 13. A first storage element having a plurality of output terminals and one output terminal of the plurality of output terminals in the first storage element, and a second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit for connecting a scan data input terminal, wherein, among output terminals of the first storage element, one cycle time of a clock signal and another output terminal of the first storage element are used. A design margin, which is a difference from a propagation time for a signal to propagate through a connection path to a storage element or an external output, is equal to or more than a predetermined amount .
If there is an output terminal, select the output terminal and
If there is no output terminal with more than
Selects the output terminal of total margin is maximized, characterized in that it comprises a connection step of connecting the scan data input terminal of the selected pre <br/> SL output terminal and before Symbol second memory element A method for designing a semiconductor integrated circuit. 14. A first memory element having a plurality of output terminals.
One output terminal of the plurality of output terminals in the slave
And scan test function with scan data input terminal
The scan data input in a second storage element having
A method for designing a semiconductor integrated circuit for connecting a terminal to a terminal, comprising:
One cycle time and the output terminal of the first storage element
Signal propagates through the connection path to another storage element or external output
Before the design margin, which is the difference from the propagation time
Output terminal and scan data input of the second storage element
It is characterized by having a connection process to connect the terminal
Semiconductor integrated circuit design method. 15. An output terminal of one of the plurality of output terminals in a first storage element having a plurality of output terminals, and a second storage element having a scan data input terminal and having a scan test function. A method of designing a semiconductor integrated circuit for connecting a scan data input terminal to a scan data input terminal, wherein each of the output terminals of the first storage element is connected to a scan data input terminal of the second storage element. Margin calculation for calculating a design margin, which is a difference between a time of one cycle of a clock signal and a propagation time for a signal to propagate through a connection path from an output terminal of the first storage element to another storage element or an external output. The design margin is equal to or more than a predetermined amount among the output terminals of the first storage element calculated in the margin calculation step.
If there is an output terminal, select the output terminal and
If there is no output terminal whose margin is more than the specified amount,
Selects the output terminal of design margin is maximized, characterized in that a connecting step of connecting the scan data input terminal of the selected <br/> said output terminal and a pre-Symbol second memory element A method for designing a semiconductor integrated circuit. 16. A first memory element having a plurality of output terminals.
One output terminal of the plurality of output terminals in the slave
And scan test function with scan data input terminal
The scan data input in a second storage element having
A method of designing a semiconductor integrated circuit for connecting a terminal to a terminal, wherein the output terminal of the first storage element includes
And the scan data input terminal of the second storage element.
The clock signal for one cycle,
From the output terminal of the first storage element, another storage element or external output
Is the difference from the propagation time of the signal
Margin calculation process to calculate each design margin
And the first storage calculated in the margin calculation step
Among the output terminals of the element, the design margin is maximized
Scan data input of the output terminal and the second storage element
And a connection step for connecting to the force terminal.
Semiconductor integrated circuit design method. 17. A first memory device having a scan data input terminal and a plurality of output terminals, one output terminal of the plurality of output terminals and a scan data input terminal having a scan test function. 2. A method for designing a semiconductor integrated circuit for connecting a scan data input terminal of a second storage element to the scan data input terminal, wherein the output terminal of the first storage element is input from a scan data input terminal of the first storage element. A connection step of selecting an output terminal having a maximum delay value of the selected signal and connecting the selected output terminal to a scan data input terminal of the second storage element. How to design integrated circuits. 18. A first memory device having a scan data input terminal and a plurality of output terminals, one of the plurality of output terminals and a scan data input terminal having a scan test function. 2. A method for designing a semiconductor integrated circuit for connecting a scan data input terminal of a second storage element to the scan data input terminal, wherein the output terminal of the first storage element is input from a scan data input terminal of the first storage element. If there is an output terminal whose delay value of the signal exceeds a predetermined amount, the output terminal
Is selected, and there is no output terminal for which the delay value is equal to or more than a predetermined amount.
If not, scan data input terminal of the first storage element
A connection step of selecting an output terminal having a maximum delay value of a signal input from the second storage element and connecting the selected output terminal to a scan data input terminal of the second storage element. Semiconductor integrated circuit design method.