JP3199944B2 - Still video equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still video apparatus for recording or reproducing an image signal.

[0002]

2. Description of the Related Art In recent years, various recording / reproducing apparatuses for recording and / or reproducing images, sounds, or other information have been developed and have become widespread. Among them, a still video camera is a device that records a photographed image on a magnetic disk together with various information related to the image, and can reproduce the photographed image as a still image as necessary.

In this still video camera, a subject image is photoelectrically converted by a solid-state image sensor to obtain a luminance signal and a color difference signal, and these signals are FM-modulated and combined to form a multiplexed image signal, and the image signal is rotated. A method of recording data on tracks of a magnetic disk is adopted. Further, ID data signals relating to field recording / frame recording, a track number, a shooting date, and the like are transmitted using DPSK (Differential Phasing).
(Se Shift Keying) modulated and recorded on the magnetic disk by superimposing on the image signal by the frequency multiplexing method.

When reproducing an image signal recorded on a magnetic disk, a luminance signal and a color difference signal subjected to FM demodulation are converted into sampling pulses generated based on vertical and horizontal synchronization signals extracted from the luminance signal, respectively. , Is temporarily stored in a memory as digital data, the data is read out according to a predetermined reference clock, converted into an analog signal, and output to a video output terminal via an output circuit.

[0005] In a still video device represented by such a still video camera, when image signals of various television systems are recorded on a magnetic disk, recording is performed in accordance with the format of the image signal input to the still video device. It is necessary to change the processing method, and when reproducing an image signal from a magnetic disk, it is necessary to reproduce the image signal by a reproduction processing method corresponding to the recording processing method.

For example, when the input image signal is a standard TV signal (standard image signal) such as an NTSC signal, the luminance signal and the line-sequential color difference The signal and the signal are recorded by a recording processing method of superimposing and recording on the same track, and at the time of reproduction, a reproduction process corresponding to the recording process is performed.

When the input image signal is an HDTV signal (high-definition image signal) such as a high-definition signal, the above-mentioned recording processing method does not have a sufficient recording band, and thus cannot record an image. Therefore, for example, an image signal corresponding to one screen is divided into a plurality of tracks and recorded while being expanded in the time axis, and at the time of reproduction, a reproduction process corresponding to the recording process is performed. According to such a recording processing method, the frequency band of a recordable image signal is substantially expanded, so that a high-definition image can be recorded.

In the case of a business system, for example,
Camera (shooting unit) according to the image signal system to be recorded
And a monitor are selected, and each is connected to a still video device. When an image signal of a predetermined system is recorded on a magnetic disk, the image signal is recorded for several screens (images), and In some cases, an image signal recorded on the spot is reproduced to check an image or the like. Further, an image signal previously recorded may be reproduced by the same recording processing method as the recorded image signal.

However, there are cases where image signals recorded in a recording processing system different from the image signal to be reproduced are mixed on the magnetic disk, and therefore, the recording is erroneously performed in another recording processing system. When the image signal is reproduced,
Since improper reproduction processing is performed, an image signal different from that at the time of input is output, and there is a problem that a normal image is not displayed on the dedicated monitor connected.

Although there is no conventional still video apparatus capable of selecting a desired recording and reproduction processing method from the two types of recording and reproduction processing methods, a still video apparatus capable of selecting a recording and reproduction processing method by manual operation is provided. When a video device is developed and recording and reproduction are performed by the device, in addition to the above-described problems, the reproduction processing method must be switched according to the recording processing method, which is a burden on the operator, and There is a problem that a reproduction processing method is erroneously selected.

[0011]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a still video apparatus capable of preventing an inappropriate image from being reproduced which does not conform to a recording processing method.

[0012]

This and other objects are achieved by the present invention which is defined below as (1) to (6).

(1) A still video apparatus comprising: a recording system for recording an image signal corresponding to one screen on a recording medium; and a reproduction system for reproducing the image signal recorded on the recording medium. The system includes a recording mode switching unit that switches a recording processing method according to a method of the image signal input to the recording system, and the reproduction system performs a reproduction processing method according to a last recording processing method of the recording system. And a playback mode switching means for switching only the image signal recorded by the last recording processing method.

(2) The recording mode switching means switches the recording processing method to a recording processing method for recording a standard image signal or a recording processing method for recording a high definition image signal. The still video device according to (1), wherein the switching unit switches the reproduction processing method to a reproduction processing method for reproducing a standard image signal or a reproduction processing method for reproducing a high-definition image signal.

(3) The image signal is composed of a luminance signal and a color difference signal, and in the recording processing method for recording the high definition image signal, the luminance signal and the color difference signal are respectively recorded on a recording medium. The still video device according to the above (2), wherein the still video device is recorded in a plurality of tracks.

(4) The still video device according to any one of (1) to (3), wherein the recording mode switching means is configured to be operated by a manual operation.

(5) The reproduction mode switching means determines the last recording processing method of the recording system and switches to the reproduction processing method according to the recording processing method. The still video device according to any one of the above).

(6) The still video as described in any of (1) to (5) above, wherein the main components constituting the recording system are also used as some of the components constituting the reproduction system. apparatus.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a still video apparatus according to the present invention. The still video device of the present invention has a recording system and a reproduction system.
In the embodiments described below, the main constituent elements of the recording system are also used as some of the constituent elements of the reproduction system, particularly the main constituent elements. However, the present invention is not limited to this. The reproduction system is independent of each other, and constitutes, for example, separate recording devices and reproduction devices, and these may be line-connected or wirelessly communicable. .

FIG. 1 is a block diagram showing a configuration example of a recording system of a still video apparatus according to the present invention. As shown in FIG. 1, the still video device 1 has a system control circuit 10 for controlling various functions of the still video device described later. This system control circuit 10 is usually constituted by a microcomputer.

The still video device 1 is provided with a magnetic disk drive mechanism 2. The magnetic disk drive mechanism 2 has a spindle motor 5 that can rotate at a high speed. The rotation of the spindle motor 5 is performed by supplying a power to the spindle motor 5 and driving the motor.
The operation of the circuit 4 is controlled by a system control circuit 10.

The magnetic disk drive mechanism 2 is loaded with a magnetic disk 3 housed in a case, for example, as a recording medium for recording an image to be photographed, audio, various data relating to the image, and the like. The magnetic disk 3 is formed by forming a magnetic layer on the surface of a circular sheet material.
) Are formed concentrically. Also,
The center of the magnetic disk 3 is structured so as to fit on the rotating shaft of the spindle motor 5. During recording and reproduction, the magnetic disk 3 is driven at a constant speed (3600 rpm in the NTSC system, PAL) by the spindle motor 5.
In the case of the system, it is rotated at 3000 rpm.

A predetermined number of FG pulses corresponding to the number of rotations of the spindle motor 5 are output from the spindle motor 5, and one rotation of the magnetic disk 3 from the vicinity of the center of the magnetic disk 3 set on the rotation axis of the spindle motor 5. 1 for each
One PG pulse is output. System control circuit 10
Is based on these pulse signals.
The magnetic disk 3 is rotated at a constant speed during recording and reproduction.

The magnetic disk drive mechanism 2 includes:
A magnetic head 6 is provided. This magnetic head 6
The magnetic disk 3 is moved continuously or intermittently (intermittently) in the radial direction of the magnetic disk 3 by a stepping motor (not shown). That is, at the time of recording and reproduction, the stepping motor is driven to move the magnetic head 6 on a predetermined track of the magnetic disk 3, and at the time of reproduction, the magnetic head 6 is placed at an appropriate position on the track, Is performed to finely adjust the position of the magnetic head 6 so as to obtain the output of (1).

The moving amount, moving speed and moving timing of the magnetic head 6 are controlled by a tracking drive circuit 7. The operation of the tracking drive circuit 7 is controlled by the system control circuit 10.

The operation unit 8 is connected to the system control circuit 10. The operation unit 8 includes a normal recording mode for recording a standard image,
In addition to the recording method selection switch 81 for selecting one of the high-definition recording modes for recording a high-definition image, for example, a selection switch for selecting one of field recording and frame recording, and the magnetic head 6 is connected to the magnetic disk 3 One of a head feed switch for moving on a predetermined track, a Rec switch for recording an image signal on the magnetic disk 3, an erase switch for erasing an image signal recorded on the magnetic disk 3, and recording / reproduction is selected. Switches and the like (both not shown) are installed as necessary.

A display unit (not shown) is connected to the system control circuit 10. The display unit displays, for example, whether field recording / frame recording, normal (standard image) / high-definition image related to a recording processing method, and normal (standard image) / high-definition image related to a reproduction processing method described later. Information, such as recording / reproduction, track number, presence / absence of track recording, shooting date, magnetic disk 3
Necessary information out of the presence or absence of the power supply, information on the power supply, information on the light emission of the strobe, and the current time is displayed by, for example, a liquid crystal or a light emitting element.

When the still video device is a still video camera, it has an image pickup unit (not shown). The imaging unit includes a lens system (not shown), an aperture, a mirror, an optical filter, a shutter, and a solid-state imaging device (CCD). When the shutter is opened, an image of a subject passes through the lens system and the like.
Image on top. The CCD may be either a black-and-white image or a color image, but in the present embodiment, a color image will be described.

The CCD photoelectrically converts the formed image and outputs color signals (R, G, B). These color signals are amplified by an amplifier (not shown) and further processed by a process / matrix circuit (not shown) to output a luminance signal (Y).
And two color difference signals (RY, BY).
The luminance signal is supplied to a horizontal and vertical synchronization signal (S) corresponding to a standard image signal by a synchronization signal generation circuit (not shown).
Alternatively, a horizontal and vertical synchronizing signal ( _SH ) corresponding to a high-definition image signal is added and output as a luminance signal (Y + S) or a luminance signal (Y + _SH ). In the case of a high-vision signal, the horizontal and vertical synchronizing signals ( _SH ) are added to the two color difference signals (RY, BY), respectively. When the still video device does not have an imaging unit, these signals are input from an external input terminal.

In this case, the still video device 1 of the present embodiment
According to the method of the image signal input to the recording system, the recording processing method selection switch 81 of the operation unit 8 described above
The recording processing method includes a recording processing method for recording a standard image signal (standard TV signal) (hereinafter, referred to as a normal recording mode) and a recording processing method for recording a high-definition image signal (HDTV signal) (hereinafter, referred to as a normal recording mode). High-definition recording mode). Hereinafter, the recording mode switching means for switching the recording processing method will be described for each case.

[High-definition recording mode] The recording processing mode selection switch 8 of the operation unit 8 is operated by manual (artificial) operation.
When the high-definition recording mode is selected in step 1, the changeover switches 51, 52, 53, 5 constituting a part of the recording mode switching means.
The terminals h of 4, 55, 56, 57 and 58 are connected. The terminal n of the changeover switch 52 is grounded, and the terminals h of the changeover switches 53, 54 and 55 are grounded. Each of the changeover switches 51 to 5
8 are controlled by the system control circuit 10, respectively.

As shown in FIG. 1, as an HDTV signal,
For example, when a Hi-Vision signal is input, the luminance signal (Y + S _H ) passes through the low-pass filter 11A and cuts a high band that may become noise (return noise due to sampling). From the luminance signal (Y + S _H ), the horizontal and vertical synchronizing signals (S _H ) are separated and extracted by the synchronizing signal separating circuit 13 and input to the clock generating circuit 14. The clock generation circuit 14 generates a memory write clock signal serving as a reference for writing to each memory, and the memory write clock signal is input to each of the memory control circuit 12 and the A / D converter 15A.

The luminance signal (Y) from which the horizontal and vertical synchronizing signals (S _H ) are separated is converted into a digital signal by the A / D converter 15A, and is temporarily stored in the Y memory 16A. After passing through the low-pass filter 11B, the color difference signal (RY) (hereinafter, referred to as a color difference signal (Pr))
The signal is converted into a digital signal by the D converter 15B, and is temporarily stored in the Pr memory 16B. Similarly, the color difference signal (BY) (hereinafter, referred to as a color difference signal (Pb)) passes through the low-pass filter 11C, and then passes through the A / D converter 16.
C is converted to a digital signal by the Pb memory 16C
Is stored once.

In this case, as described above, the changeover switch 56
Since the terminal h is in the connected state for each of ~ 58,
Even if the standard image signal is input, the image signal is not stored in each of the memories 16A to 16C, so that it is possible to prevent the standard image signal from being recorded on the magnetic disk 3 in the high definition recording mode.

The memory control circuit 12 performs the following control based on the memory write clock signal from the clock generation circuit 14 while setting the timing of writing to each of the memories 16A to 16C. That is, based on the memory write clock signal from the clock generation circuit 14, A
As the / D converter 15A operates, the memory control circuit 12 operates the built-in write address counter to write the digital data of the luminance signal (Y) to a predetermined address of the Y memory 16A.

The memory write clock signal from the clock generation circuit 14 is frequency-divided by 1/2 by the frequency divider 17A to operate the A / D converters 15B and 15C, and the memory control circuit 12 Activate the built-in address counter for writing to the Pr memory 16
Digital data of a color difference signal (Pr) and a color difference signal (Pb) are written to predetermined addresses of the B and Pb memories 16C, respectively. Note that the synchronization signal (S _H ) included in the input signal such as the luminance signal is not sampled, and therefore is not written to the memory.

From the synchronizing signal generation circuit 18, for example, NT
The horizontal and vertical synchronization signals (S) according to the SC system are output and input to the clock generation circuit 19. The clock generation circuit 19 generates a memory read clock signal serving as a reference for reading from each memory, and the memory read clock signal is supplied to the memory control circuit 12 and the D / A
Input to converters 20A, 20B and 20C, respectively. The memory control circuit 12 performs the following control based on the memory read clock signal from the clock generation circuit 19 while taking the timing of reading from each of the memories 16A to 16C.

That is, based on the memory read clock signal from the clock generation circuit 19, the memory control circuit 12 activates a built-in read address counter, and outputs a luminance signal (Y) from a predetermined address of the Y memory 16A. Read digital data and D / A
The converter 20A operates to read the luminance signal (Y)
Is converted into an analog signal.

Also, based on the memory read clock signal from the clock generation circuit 19, the memory control circuit 12
Operates a built-in write address counter to read out digital data of a color difference signal (Pr) and a color difference signal (Pb) from predetermined addresses of the Pr memory 16B and the Pb memory 16C, respectively.
The / A converters 20B and 20C operate to convert the read digital signals of the respective color difference signals into analog signals.

In the memory control circuit 12, the mode switching between the writing control and the reading control of the memory is controlled by a mode switching command signal from the system control circuit 10. The horizontal and vertical synchronizing signals (S _H ) from the synchronizing signal separating circuit 13 and the horizontal and vertical synchronizing signals (S) from the synchronizing signal generating circuit 18 are also input to the system control circuit 10, respectively. Is used as a timing signal for various operations.

In the case of recording such a high-definition image, the memory read clock signal from the clock generation circuit 19 has a smaller frequency, for example, １ ／ than the memory write clock signal from the clock generation circuit 14. Frequency. Therefore, the frequency of the read clock signal of the luminance signal is １ ／ of the frequency of the write clock signal, and the frequency of the read clock signal of the two color difference signals is の of the frequency of the write clock signal. As a result, the signal is recorded after being extended on the time axis as compared with the signal input to the recording system.

The luminance signal (Y), color difference signal (Pr), and color difference signal (Pb), which are analog signals, are respectively
After the high frequencies are cut by the low-pass filters 21A, 21B, and 21C, the synchronization signal adding circuits 22A, 22A
The vertical and horizontal synchronizing signals (S) from the synchronizing signal generation circuit 18 are added by B and 22C.

Synchronous signal adding circuits 22A, 22B and 2
Terminals a, b and c of the changeover switch 23 are connected to 2C, respectively. The switching of the terminals a, b, and c connected by the changeover switch 23 is controlled by the system control circuit 10, and the luminance signal (Y + S), the color difference signal (Pr + S), and the color difference signal (Pb + S) are sequentially sent to the recording processing circuit 24A. input. In the recording processing circuit 24A,
Each input signal is FM-modulated.

The system control circuit 10 determines whether field recording / frame recording, field number in the case of frame recording, normal recording / high-definition recording, the type of image signal to be recorded, that is, the luminance signal (Y + S) / Color difference signal (Pr + S) / color difference signal (Pb + S), component of one screen (for example, upper left / lower left / upper right / lower right of screen in case of 4 divisions), track number, shooting year An ID data signal relating to image information such as date is output,
The ID recording processing circuit 25 performs DPSK modulation on a carrier (carrier) generated based on the horizontal synchronization signal (S) from the synchronization signal generation circuit 18 based on the ID data signal to obtain a DPSK signal.

The DPSK signal for this ID data is
The adder 26 combines the image signal with the image signal FM-modulated by the recording processing circuit 24. The image signal synthesized by the adder 26 is amplified by a recording amplifier 27 controlled by the system control circuit 10 and is recorded on a predetermined track of the rotating magnetic disk 3 by the magnetic head 6.

In recording a high-definition image, an image signal corresponding to one screen is divided into a plurality of tracks and recorded in a time-axis-expanded manner. Therefore, data is stored in the memories 16A to 16C as follows. It is divided and performed.

FIG. 3 is a schematic diagram showing an example of a storage area pattern of an image signal in the memories 16A to 16C. In the example shown in this figure, an image signal is recorded in a frame recording mode, and a luminance signal (Y) and a color difference signal (Pr) are recorded.
9 is an example of high-definition image recording in which each of a color difference signal (Pb) is recorded on a plurality of tracks. That is, one screen is composed of a first field and a second field, the luminance signal (Y) is divided into four for one screen, and the color difference signal (Pr) and the color difference signal (Pb) are each divided into two for one screen. Corresponding memory 16A-16
Stored in C. Note that FIG. 3 shows the arrangement of image signal storage areas on the memory and also corresponds to the configuration of a screen (still image) displayed on the display.

As for the luminance signal (Y), the screen has center lines E and F extending in the horizontal and vertical directions, respectively.
In the first field, a luminance signal Y ₁ corresponding to the upper left, a luminance signal Y ₂ corresponding to the upper right, a luminance signal Y ₃ corresponding to the lower left, and a luminance signal Y ₄ corresponding to the lower right are respectively , Y memory 16A are stored in a first area, a second area, a third area, and a fourth area.

The color difference signal (Pr) is divided into two parts by a center line G extending in the horizontal direction. In the first field, the color difference signal Pr ₁ corresponding to the upper half and the color difference signal Pr corresponding to the lower half are provided. ₂ are stored in the fifth area and the sixth area of the Pr memory 16B, respectively.

The color difference signal (Pb) is divided into two parts by a center line G extending in the horizontal direction. In the first field, the color difference signal Pb ₁ corresponding to the upper half and the color difference signal Pb corresponding to the lower half are provided. ₂ are stored in the seventh area and the eighth area of the Pb memory 16C, respectively.

Similarly, for the second field, the luminance signals Y ₅ and Y ₅ corresponding to the upper left, upper right, lower left and lower right of the screen,
Y ₆ , Y ₇ and Y ₈ are each stored in the Y memory 16A.
Ninth region of the tenth region, stored in the eleventh region and a twelfth region, the color difference signals Pr ₃ and Pr ₄ corresponding to the upper and lower screens, respectively, Pr memory 16B
And the color difference signals Pb ₃ and Pb ₄ corresponding to the upper and lower parts of the screen are stored in the thirteenth and fourteenth areas, respectively.
The fifteenth area and the first area of the Pb memory 16C, respectively.
It is stored in six areas.

FIG. 4 is a diagram showing an example of a track pattern formed on the magnetic disk 3. As shown in the figure, each of the above image signals is recorded on 16 tracks continuously arranged in the radial direction of the magnetic disk 3. in this case,
The image signals belonging to the first field are recorded on eight consecutively arranged tracks, and the image signals belonging to the second field are recorded on the other eight consecutively arranged tracks. In the illustrated configuration, from the outer peripheral side of the magnetic disk 3 toward the inner peripheral side,
Luminance signals Y ₁ , Y ₂ , Y ₃ , Y _{4 of} the first field, color difference signals Pr ₁ , Pr ₂ , color difference signals Pb ₁ , Pb ₂ , _second signal
The luminance signals Y ₅ , Y ₆ , Y ₇ , Y ₈ , the color difference signals Pr ₃ , Pr ₄ , and the color difference signals Pb ₃ , Pb _{4 of the field} are sequentially recorded one by one.

FIG. 5 is a time chart showing the relationship between the luminance signal (Y) input to the recording system of the still video device and the luminance signal (Y) recorded on the track when recording a high-definition image. . One screen is composed of the first field and the second field.
Shows the luminance signal of the first field. The luminance signal of the first field is composed of a number of horizontal scanning lines H, and the luminance signal corresponding to one horizontal scanning line H is between two adjacent horizontal synchronizing signals S _Hh (hereinafter referred to as “horizontal scanning line H”). Synchronization period).

When recording a luminance signal, the changeover switch 2
The terminal a of the magnetic disk 3 is connected, and the magnetic head 6 sequentially moves from the first track to the fourth track on the outer peripheral side of the magnetic disk 3. That is, when the recording of the luminance signal Y ₁ is
The magnetic head 6 is first on track, during the recording of the luminance signal Y ₂ are the magnetic head 6 on the second track, the time of recording of the luminance signal Y _3, the magnetic head 6 on the third track When recording the luminance signal Y ₄ , the magnetic head 6
It moves on the track and performs recording (see FIG. 4). Here, the Nth track does not mean the Nth track from the outermost periphery of the magnetic disk 3,
It means a relative track number with respect to an arbitrary track.

As shown in FIG. 5, the frequency band of the luminance signals Y _{1 to} Y ₄ when written into the Y memory 16A is represented by f
_{If H} is set, the frequency band is extended by a factor of four when read from the Y memory 16A, so that the frequency band of the luminance signals Y _{1 to} Y ₄ recorded on the first to fourth tracks is f _H / 4. Due to the characteristics of the magnetic disk 3, there is a limit in the recordable band, but with such a configuration, a luminance signal in a higher band can be substantially recorded, and a high-definition image can be recorded. You.

FIG. 6 shows a color difference signal (Pr) input to a recording system of a still video device in recording a high-definition image.
4 is a time chart showing a relationship between the color difference signal (Pr) recorded on a track. One screen is composed of the first field and the second field.
FIG. 6 shows the color difference signal (Pr) of the first field. The color difference signal of the first field is composed of a number of horizontal scanning lines H, and there is a color difference signal corresponding to one horizontal scanning line H within one horizontal synchronization period.

When recording the color difference signal (Pr), the terminal b of the changeover switch 23 is connected, and the magnetic head 6 sequentially moves to the fifth track and the sixth track. ₁ is recorded on the fifth track, and the color difference signal Pr ₂ is recorded on the sixth track (see FIG. 4).

As shown in FIG. 6, the frequency band of the color difference signals Pr ₁ and Pr ₂ when written to the Pr memory 16B is f _H / 2, and is expanded by a factor of two when read from the Pr memory 16B. Therefore, the fifth and sixth
The frequency band of the color difference signals Pr ₁ and Pr ₂ recorded on the track is f _H / 4. Although the recordable band is limited due to the characteristics of the magnetic disk 3, in such a configuration, a color difference signal of a band higher than that can be substantially recorded, and recording of a high-definition image is realized. You.

At the time of recording the color difference signal (Pb), the terminal c of the changeover switch 23 is connected, and the magnetic head 6 moves to the seventh track and the eighth track. Similarly to Pr), the color difference signal Pb ₁
Are recorded on the seventh track in the band of f _H / 4, and the color difference signal Pb ₂ is recorded on the eighth track in the band of f _H / 4.

The luminance signals Y _{5 to} Y in the second field
₈ , the recording of the color difference signals Pr ₃ , Pr ₄ , Pb ₃ and Pb ₄ is the same as in the first field, and is recorded on the (N + 8) th track (N = 1 to 8), respectively (FIG. 4). reference). Incidentally, the synchronization signal recorded on the magnetic disk 3, the synchronous signal for a high definition image (S _H) without, for example, as being replaced by the synchronization signal (S) conforming to the NTSC system. In this case, FIGS.
Only the horizontal synchronization signal _Sh is shown.

[Normal recording mode] The recording mode selection switch 8 of the operation unit 8 is operated by manual (artificial) operation.
When the normal recording mode is selected at 1, the changeover switches 51, 52, 53, which constitute a part of the recording mode switching means,
The terminals n of 54, 55, 56, 57 and 58 are connected.

As shown in FIG. 1, as a standard TV signal,
For example, when a composite video (NTSC) signal is input, the decoder 46 separates the signal into a luminance signal (Y + S), a color difference signal (Pr), and a color difference signal (Pb).

The separated luminance signal (Y + S) passes through the low-pass filter 11A and cuts a high frequency band which may become noise (aliasing noise due to sampling).
From the luminance signal (Y + S), the synchronizing signal separating circuit 13
, The horizontal and vertical synchronization signals (S) are separated and extracted, and input to the clock generation circuit 14. The clock generation circuit 14 generates a memory write clock signal serving as a reference for writing to each memory, and the memory write clock signal is input to each of the memory control circuit 12 and the A / D converter 15A.

The luminance signal (Y) from which the horizontal and vertical synchronizing signals (S) are separated is converted into a digital signal by the A / D converter 15A, and is temporarily stored in the Y memory 16A. After passing through the low-pass filter 11B, the color difference signal (Pr) is converted into a digital signal by the A / D converter 15B, and is temporarily stored in the Pr memory 16B. Similarly, the color difference signal (Pb) is supplied to the low-pass filter 1.
After passing through 1C, the signal is converted into a digital signal by the A / D converter 16C, and is temporarily stored in the Pb memory 16C.

In this case, as described above, the changeover switch 56
Since the terminal n is in a connected state in each of the devices 58 to 58,
Even if a high-definition image signal is input, the image signal is not stored in each of the memories 16A to 16C, thereby preventing the high-definition image signal from being recorded on the magnetic disk 3 in the normal recording mode. it can.

The memory control circuit 12 performs the following control based on the memory write clock signal from the clock generation circuit 14 while setting the timing of writing to each of the memories 16A to 16C. That is, based on the memory write clock signal from the clock generation circuit 14, A
As the / D converter 15A operates, the memory control circuit 12 operates the built-in write address counter to write the digital data of the luminance signal (Y) to a predetermined address of the Y memory 16A.

The memory write clock signal from the clock generation circuit 14 is frequency-divided by 1/2 by the frequency divider 17A to operate the A / D converters 15B and 15C, and the memory control circuit 12 Activate the built-in address counter for writing to the Pr memory 16
Digital data of a color difference signal (Pr) and a color difference signal (Pb) are written to predetermined addresses of the B and Pb memories 16C, respectively. Note that the synchronization signal (S) included in an input signal such as a luminance signal is not sampled,
Therefore, it is not written to memory.

From the synchronizing signal generation circuit 18, for example, NT
The horizontal and vertical synchronization signals (S) according to the SC system are output and input to the clock generation circuit 19. The clock generation circuit 19 generates a memory read clock signal serving as a reference for reading from each memory, and the memory read clock signal is supplied to the memory control circuit 12 and the D / A
Input to converters 20A, 20B and 20C, respectively.

The memory control circuit 12 performs the following control based on the memory read clock signal from the clock generation circuit 19 while setting the timing of reading from each of the memories 16A to 16C. That is, based on the memory read clock signal from the clock generation circuit 19,
The memory control circuit 12 operates a built-in read address counter to read digital data of the luminance signal (Y) from a predetermined address of the Y memory 16A, and operates the D / A converter 20A to read the digital data. The digital signal of the luminance signal (Y) is converted into an analog signal.

Further, based on the memory read clock signal from the clock generation circuit 19, the memory control circuit 12
Operates a built-in write address counter to read digital data of a color difference signal (Pr) and a color difference signal (Pb) from predetermined addresses of the Pr memory 16B and the Pb memory 16C, respectively. The memory read clock signal is frequency-divided by に よ り by the frequency divider 17B, and operates the D / A converters 20B and 20C to convert the read digital signal of each color difference signal into an analog signal.

In the memory control circuit 12, the mode switching between the writing control and the reading control of the memory is controlled by a mode switching command signal from the system control circuit 10. The horizontal and vertical synchronizing signals (S) from the synchronizing signal separating circuit 13 and the horizontal and vertical synchronizing signals (S) from the synchronizing signal generating circuit 18 are also input to the system control circuit 10, respectively. It is used for controlling the rotation phase of the spindle motor 5 based on the timing, and is used as a timing signal for various other operations.

In the case of recording such a standard image, the memory read clock signal from the clock generation circuit 19 and the memory write clock signal from the clock generation circuit 14 have the same frequency. Therefore, the frequency of the read clock signal of the luminance signal and the frequency of the write clock signal are the same, the frequency of the read clock signal of both color difference signals and the frequency of the write clock signal are the same, The frequency of the write and read clock signals is twice the frequency of the write and read clock signals of both color difference signals.

The luminance signal (Y), color difference signal (Pr), and color difference signal (Pb), which are analog signals, are respectively
The high band is cut by the low-pass filters 21A, 21B and 21C, and thereafter, the vertical and horizontal synchronization signals (S) from the synchronization signal generation circuit 18 are added to the luminance signal (Y) by the synchronization signal addition circuit 22A. You. The changeover switch 23 has a terminal a connected, and the luminance signal (Y + S) is input to the recording processing circuit 24A via the changeover switch 23 and is subjected to FM modulation.

The terminal n of the changeover switch 53 is connected to the synchronizing signal adding circuit 22B.
The terminal n of the changeover switch 54 is connected to C, and the color difference signal (Pr) and the color difference signal (Pb) are supplied to the C signal recording processing circuit 24 via the changeover switches 53 and 54, respectively.
B is input. The input color difference signal (Pr) and color difference signal (Pb) are line-sequentialized and FM-modulated by the C signal recording processing circuit 24B, and input to the adder 26 via the changeover switch 55.

Also, various ID data signals are output from the system control circuit 10 as in the case of the high-definition recording mode, and the ID recording processing circuit 25 outputs the horizontal synchronization signal (from the synchronization signal generation circuit 18). The carrier (carrier) generated based on S) is subjected to DPSK modulation based on the ID data signal to obtain a DPSK signal.

A DPSK signal relating to the ID data,
The FM-modulated luminance signal (Y + S) and the line-sequentialized and FM-modulated color difference signals (Pr, Pb) are added to an adder 2.
Synthesized by 6. The image signal synthesized by the adder 26 is amplified by a recording amplifier 27 controlled by the system control circuit 10 and is recorded on a predetermined track of the rotating magnetic disk 3 by the magnetic head 6.

In this case, in the case of field recording, 1
An image signal corresponding to a screen is recorded on one track, and in the case of frame recording, an image signal for one field is recorded on one track (an image signal corresponding to one screen is recorded on two tracks).

Next, when the high-definition recording mode or the normal recording mode is selected by the recording mode selection switch of the operation unit 8 shown in FIG. 1, the recording mode is switched by the recording mode switching means and the image is recorded on the magnetic disk 3. The control operation for recording a signal will be described. FIG.
FIG. 8 is a flowchart illustrating a control operation when performing recording in the high-definition recording mode, and FIG. 8 is a flowchart illustrating a control operation when performing recording in the normal recording mode.

As shown in FIG. 7, when recording is performed in the high-definition recording mode, terminals h of changeover switches 51 to 58 are connected.
Are connected (step 201). Next, the clocks generated by the clock generation circuits 14 and 19 are respectively switched for high definition (step 20).
2). In this case, the frequency of the clock generated by the clock generation circuit 14 is four times the frequency of the clock generated by the clock generation circuit 19.

Next, each of the low-pass filters 11A-1A
The cut-off frequency of 1C is switched for high definition (step 203). Specifically, each low-pass filter 11
The cutoff frequency of A to 11C is set to each A / D converter 15A.
サ ン プ リ ン グ of the sampling frequency of １５15C.

Next, each of the low-pass filters 21A to 21A
The cut-off frequency of 1C is switched for high definition (step 204). Specifically, the low-pass filter 21B
And 21C are set to １ ／ of the sampling frequency of D / A converters 20B and 20C, respectively.

By executing the steps 201 to 204, the cutoff frequency of each of the low-pass filters 11A to 11C, the sampling frequency of each of the A / D converters 15A to 15C, the writing frequency to each of the memories 16A to 16C, and the respective memories 16A to 16C Reading frequency from 16C,
Sampling frequency of each of the D / A converters 20A to 20C,
The cutoff frequency of each of the low-pass filters 21A to 21C is set as shown in Table 1 below.

[0083]

[Table 1]

After setting the respective frequencies as shown in Table 1, the luminance signal (Y), the color difference signal (Pr), and the color difference signal (Pb) are stored in the memories 16A to 16C, respectively (step 205). Next, after the terminal a of the selection switch 23 is connected (step 206), the luminance signal (Y) stored in the Y memory 16A is read out and recorded on a predetermined track of the magnetic disk 3 (step 2).
07).

Next, after the terminal b of the selection switch 23 is connected (step 208), the Pr memory 16B
Is read and recorded on a predetermined track of the magnetic disk 3 (step 209).
Next, after the terminal c of the selection switch 23 is connected (step 210), the color difference signal (Pb) stored in the Pb memory 16C is read out and recorded on a predetermined track of the magnetic disk 3 (step 211).

In this way, of the image signals for one screen, the image signals belonging to the first field are recorded on the eight tracks, and the above-mentioned steps 206 to 211 are repeatedly executed, whereby the second field is recorded. The belonging image signals are recorded on the other eight tracks, and as a result, the image signals for one screen are recorded in the track pattern shown in FIG.

When recording is performed in the normal recording mode, as shown in FIG.
Are connected to each other (step 30).
1). Next, the clocks generated by the clock generation circuits 14 and 19 are each switched to the standard clock (step 302). In this case, the frequency of the clock generated by the clock generation circuit 14 is made equal to the frequency of the clock generated by the clock generation circuit 19.

Next, each of the low-pass filters 11A-1A
The cutoff frequency of 1C is switched to the standard one (step 303). Specifically, each low-pass filter 11A
~ 11C cut-off frequency to each A / D converter 15A ~
Set to 1/2 of the sampling frequency of 15C.

Next, each of the low-pass filters 21A-2
The cutoff frequency of 1C is switched to the standard one (step 304). Specifically, the cutoff frequencies of the low-pass filters 21B and 21C are set to １ ／ of the sampling frequency of the D / A converters 20B and 20C, respectively.

By executing the steps 301 to 304, the cutoff frequency of each of the low-pass filters 11A to 11C, the sampling frequency of each of the A / D converters 15A to 15C, the writing frequency to each of the memories 16A to 16C, and the respective memories 16A to 16C Reading frequency from 16C,
Sampling frequency of each of the D / A converters 20A to 20C,
The cut-off frequency of each of the low-pass filters 21A to 21C is set as shown in Table 2 below.

[0091]

[Table 2]

After setting the respective frequencies as shown in Table 2, the luminance signal (Y), the color difference signal (Pr), and the color difference signal (Pb) are stored in the memories 16A to 16C, respectively (step 305).

Next, after the terminal a of the selection switch 23 is connected (step 306), each of the memories 16A to 16A is connected.
Luminance signal (Y) and color difference signal (Pr) stored in 16C
And the color difference signal (Pb) are read out at the same time, and a predetermined recording process (luminance signal recording process) is performed on the luminance signal (Y) by the recording processing circuit 24A, and the color difference signal (Pr)
For the color difference signal (Pb), a predetermined recording process (color difference signal recording process) is performed by the C signal recording processing circuit 24B, and is recorded on a predetermined track of the magnetic disk 3 (step 307). In this way, of the image signals for one screen, the image signal belonging to the first field is recorded on one track, and the image signal belonging to the second field is recorded on another track.

FIG. 2 is a block diagram showing a configuration example of a reproduction system of the still video device of the present invention. In the still video apparatus 1 shown in FIG. 1, a magnetic disk drive mechanism 2, an operation unit 8, and a display unit (a magnetic disk 3, a motor drive circuit 4, a spindle motor 5, a magnetic head 6, and a tracking drive circuit 7). The system control circuit 10 (not shown) is the same as or shared with the recording system shown in FIG.

The still video apparatus 1 of this embodiment has a reproduction mode switching means for switching the reproduction processing method according to the last recording processing method of the recording system described above. The reproduction mode switching means determines, for example, the last recording processing method of the recording system based on the information (signal) relating to the recording processing method of the recording system described above. Is a standard image signal (standard TV)
To a reproduction processing method (hereinafter referred to as a normal reproduction mode) for reproducing a high-definition image signal (HDTV signal). High-definition playback mode)
It is configured to switch to.

In the present embodiment, for example, a signal input to the system control circuit 10 indicating the state (normal recording mode or high-definition recording mode) of the recording mode selection switch 81 of the operation unit 8 or a signal based on this signal is displayed. The last recording processing method of the recording system is determined based on a signal output from the system control circuit 10 or information on the recording processing method such as a signal indicating a recording processing method when performing automatic switching of a recording mode described later. . Specifically, this is performed as follows.

For example, the state of a recording processing mode selection switch 81 which is a two-state switch is determined to switch the reproduction processing mode.

For example, information on the recording processing method is stored in a memory built in the system control circuit 10, and this memory is rewritten each time a new recording is performed. As a result, information on the last recording processing method is stored in this memory. Therefore, at the time of reproduction, this information is appropriately read from the memory and used for discrimination for switching the reproduction processing method. Can be. According to this method, the recording processing method selection switch 81 of this embodiment is used as the recording processing method selection switch.
The determination can be made even when a switch other than the above is used, or when automatic switching of a recording mode described later is performed.

FIG. 13 is a flowchart showing the control operation of the system control circuit 10. Hereinafter, this flowchart will be described. First, it is determined whether or not the printing mode is set (step 701). If it is determined that the printing mode is set, it is determined whether or not the printing method is the high-definition printing mode (step 702).

If it is determined in step 702 that the recording mode is the high-definition recording mode, a flag Fr indicating that the recording processing mode is the high-definition recording mode is set (Fr = 1), and a signal (information ) Is stored at a predetermined address of a memory built in the system control circuit 10 (step 703).

If it is determined in step 702 that the recording mode is the normal recording mode, the flag Fr indicating that the recording method is the high-definition recording mode is not set (Fr =
0), a signal corresponding to Fr = 0 (a signal indicating that the recording processing method is the normal recording mode) is stored in a predetermined address of a memory built in the system control circuit 10 (step 704). Hereinafter, step 701 will be described.
Steps 704 to 704 are repeatedly executed, and information on the set recording processing method is always stored at a predetermined address of the memory.

If it is determined in step 701 that the mode is the reproduction mode, information already stored at a predetermined address of the memory is read, and it is determined whether or not Fr = 1 (step 705). That is, it is determined whether or not the last recording processing method is the high-definition recording mode.

If it is determined in step 705 that Fr = 1, a high-definition reproduction mode described later is set (step 706). Also, in step 705, Fr =
If it is determined to be 0, a normal reproduction mode described later is set (step 707). This ends the program.

In the present invention, the reason why the last recording processing method is determined and the reproduction processing method is selected based on this is that the recorded image is usually reproduced as it is after recording. This is because the frequency of reproduction by the reproduction processing method according to the method is high. For example, this corresponds to a case where the image signal is reproduced and monitored immediately after recording.

The still video apparatus 1 of the present embodiment is
Only the image signal recorded by the last recording processing method determined by the reproduction mode switching means is reproduced.

That is, in the present embodiment, for example, the recording processing method of the image signal is determined for each track based on the information on the recording processing method indicating the normal recording / high-definition recording in the above-mentioned ID data. If the last recording processing method determined by the reproduction mode switching means matches the recording processing method determined based on the ID data,
Reproduction is permitted, and if they do not match, reproduction is prohibited, thereby preventing improper reproduction processing from being performed and reproducing image signals. Hereinafter, the high-definition reproduction mode and the normal recording mode will be described separately together with the reproduction mode switching means.

[High Definition Reproduction Mode] The system control circuit 10 constituting a part of the reproduction mode switching means shown in FIG.
When the last recording processing method of the recording system is determined to be the high-definition recording mode, that is, when Fr = 1 as shown in FIG. 13, the reproduction processing method is set to the high-definition reproduction mode (steps 705 and 706). In this case, as shown in FIG. 2, the changeover switches 61, 62 and 63, which constitute a part of the reproduction mode changeover means, are respectively controlled by the system control circuit 10, and the terminal h is connected. In addition,
The terminal n of the changeover switch 63 is grounded.

Next, with respect to the rotating magnetic disk 3,
The magnetic head 6 is moved in a predetermined order on a predetermined track on which an image signal corresponding to one still image is recorded, that is, 16 tracks shown in FIG. 4, and the image signal and the DPSK signal are sequentially transmitted from each track. Read.

In this case, in this embodiment, among the image signals recorded on the 16 tracks corresponding to one still image, first, the luminance signals Y ₁ to Y ₁ recorded on the outer track of the magnetic disk 3 are output. Read Y ₄ and Y memory 3
9A, and then the color difference signals Pr ₁ and Pr recorded on these inner adjacent tracks.
Performs writing to the _second reading and Pr memory 39B, then the first field is performed to write to these inner peripheral color difference recorded in the track adjacent to the side signal Pb ₁ and Pb ₂ read and Pb memory 39C after regeneration of the belonging image signals is carried out analogously to this luminance signal Y ₅ to Y ₈ belonging to the second field, the reproduction of the color difference signals Pr _3, Pr _4, Pb ₃ and Pb _4.

The image signal and the like read by the magnetic head 6 are first amplified by the reproducing amplifier 30, and among them,
The luminance signal (Y + S), the color difference signal (Pr + S), and the color difference signal (Pb + S) pass through a high-pass filter (not shown) and are input to the image signal reproduction processing circuit 31A, where they are FM-demodulated.

The read DPSK signal passes through a band-pass filter (not shown) and is input to the ID reproduction processing circuit 32, where it is DPSK-demodulated to reproduce ID data. This ID data is input to the system control circuit 10. Then, the system control circuit 10
Based on the D data, a recording processing method of the image signal read by the magnetic head 6 is determined, and execution of the reproduction of the image signal and control of prohibition thereof are performed as described later.

The output side of the reproduction amplifier 30 is connected to an envelope detection circuit 33. The envelope detection circuit 33 detects the envelope (envelope) of the reproduction signal read by the magnetic head 6, and detects the envelope. Is output to the system control circuit 10. The system control circuit 10 controls the tracking drive circuit 7 to perform the automatic tracking of the magnetic head 6 so that the output of the envelope detection signal is maximized. Such as the automatic tracking of the magnetic head 6,
By performing the rotation phase control of the spindle motor 5 described later, a good still image can be obtained.

The luminance signal (Y + S), chrominance signal (Pr + S) and chrominance signal (Pb + S) FM-demodulated by the reproduction processing circuit 31A pass through the low-pass filter 34A to cut the high frequency band. Then, the horizontal and vertical synchronizing signals (S) are separated and extracted by the synchronizing signal separating circuit 36 and input to the system control circuit 10 and the clock generating circuit 37, respectively. Horizontal and vertical synchronization signals (S) input to the system control circuit 10
Is used, for example, for reading ID data. Further, the clock generation circuit 37 generates a memory write clock signal as a reference for writing to the memory, and the generated memory write clock signal is supplied to the A / D converter 38.
A and the memory control circuit 35 respectively.

The luminance signal (Y) that has been FM-demodulated and from which the horizontal and vertical synchronizing signals (S) have been separated is converted into a digital signal by an A / D converter 38A, and is converted into a Y memory 39.
A is temporarily stored at a predetermined address. FM demodulated,
The color difference signal (Pr) from which the horizontal and vertical synchronizing signals (S) are separated is converted into a digital signal by the A / D converter 38A, and the Pr memory 39B is switched via the switch 61.
Is stored once. Similarly, the color difference signal (Pb) is
The signal is converted into a digital signal by the A / D converter 38A, and is temporarily stored in the Pb memory 39C via the switch 62.

The system control circuit 10 determines whether the image signal read by the magnetic head 6 is a luminance signal Y _{1 to} Y ₈ , a color difference signal Pr _{1 to} Pr ₄ , or a color difference signal Pb _{1 to} Pb _4. Is determined from the reproduced ID data, and the operation of the memory control circuit 35 is controlled based on this. The memory control circuit 35 controls each of the memories 39A based on the memory write clock signal from the clock generation circuit 37.
The following control is performed while setting the timing of writing to .about.39C.

That is, based on the memory write clock signal from the clock generation circuit 37, the A / D converter 38
A operates, and the memory control circuit 35 operates the built-in write address counter to write the digital data of the luminance signal (Y) to a predetermined address of the Y memory 16A.

The memory control circuit 35 activates a built-in write address counter based on the memory write clock signal from the clock generation circuit 37, so that a predetermined address of the Pr memory 39B and a predetermined address of the Pb memory 39C respectively. The digital data of the color difference signal (Pr) and the color difference signal (Pb) is written. In addition,
A synchronization signal (S) included in a reproduced signal such as a luminance signal is
It is not sampled and therefore not written to memory.

The horizontal and vertical synchronizing signals (S _H ) corresponding to the high-definition image signal are output from the synchronizing signal generating circuit 40 and input to the clock generating circuit 41. The clock generation circuit 41 generates a memory read clock signal as a reference for reading from each memory, and this memory read clock signal is supplied to the memory control circuit 35 and the D / D
Each is input to the A converter 42A. Further, this memory read clock signal is frequency-divided by a frequency divider 43B into １ ／, and then input to D / A converters 42B and 42C, respectively.

The memory control circuit 35 performs the following control based on the memory read clock signal from the clock generation circuit 41 while setting the timing of reading from each of the memories 39A to 39C. That is, based on the memory read clock signal from the clock generation circuit 41,
The memory control circuit 35 operates a built-in read address counter to read digital data of the luminance signal (Y) from a predetermined address of the Y memory 39A, and operates the D / A converter 42A to read the digital data. The digital signal of the luminance signal (Y) is converted into an analog signal.

Further, based on the memory read clock signal from the clock generation circuit 41, the memory control circuit 35
Operates a built-in write address counter to read digital data of a color difference signal (Pr) and a color difference signal (Pb) from predetermined addresses of the Pr memory 39B and the Pb memory 39C, respectively, and
The / A converters 42B and 42C operate to convert the read digital signals of the respective color difference signals into analog signals.

In the memory control circuit 35, the mode switching between the write control and the read control of the memory is controlled by a mode switching command signal from the system control circuit 10. Also, the horizontal and vertical synchronizing signals from the synchronizing signal separation circuit 36 (S), the horizontal and vertical synchronizing signals from the synchronizing signal generating circuit 40 and (S _H), respectively, are also inputted to the system control circuit 10, which Is used as a timing signal for various operations.

In the case of reproducing such a high-definition image, the memory read clock signal from the clock generation circuit 41 has a higher frequency, for example, four times as large as the memory write clock signal from the clock generation circuit 37. Have a frequency. Therefore, the frequency of the read clock signal of the luminance signal is four times the frequency of the write clock signal, and the frequency of the read clock signal of the two color difference signals is twice the frequency of the write clock signal. The signal read out by the head 6 is compressed in the time axis and reproduced in the original state (state at the time of input to the recording system).

The luminance signal (Y), color difference signal (Pr), and color difference signal (Pb), which have been analog signals, are respectively
After the high frequencies are cut by the low-pass filters 44A, 44B and 44C, the synchronization signal adding circuits 45A and 45C
The vertical and horizontal synchronizing signals ( _SH ) from the synchronizing signal generation circuit 40 are added by B and 45C.

The luminance signal (Y + S
_H ), the color difference signal (Pr + S _H ) and the color difference signal (Pb +
S _H ) is output as a video signal via an output circuit (not shown), and a still image is reproduced on a connected display.

[Normal Reproduction Mode] The system control circuit 10 constituting a part of the reproduction mode switching means shown in FIG.
However, when the last recording processing method of the recording system is determined to be the normal recording mode, that is, when Fr = 0 is determined as shown in FIG. 13, the reproduction processing method is set to the normal reproduction mode (steps 705 and 707). In this case, as shown in FIG. 2, the changeover switches 61, 62 and 63, which constitute a part of the reproduction mode changeover means, are controlled by the system control circuit 10, and the terminal n is connected.

Next, with respect to the rotating magnetic disk 3,
The magnetic head 6 is positioned on a predetermined track on which an image signal corresponding to one still image is recorded, and an image signal and a DPSK signal are sequentially read from each track.

The image signal and the like read by the magnetic head 6 are first amplified by the reproducing amplifier 30, and among them,
The luminance signal (Y + S) passes through a high-pass filter (not shown) and is input to an image signal reproduction processing circuit 31A.
The color difference signals (Pr, Pb) that have been FM-demodulated pass through a low-pass filter (not shown), and are passed through a C signal reproduction processing circuit 31.
B and FM demodulated.

The read DPSK signal passes through a band pass filter (not shown) and is input to the ID reproduction processing circuit 32, where it is subjected to DPSK demodulation to reproduce ID data. This ID data is input to the system control circuit 10. Then, the system control circuit 10
Based on the D data, a recording processing method of the image signal read by the magnetic head 6 is determined, and execution of the reproduction of the image signal and control of prohibition thereof are performed as described later.

Also, as in the case of the high definition playback mode,
The system control circuit 10 controls the tracking drive circuit 7 to perform the automatic tracking of the magnetic head 6 so that the output of the envelope detection signal of the reproduction signal becomes maximum. Such as the automatic tracking of the magnetic head 6,
By performing the rotation phase control of the spindle motor 5 described later, a good still image can be obtained.

The luminance signal (Y + S) FM-demodulated by the reproduction processing circuit 31A passes through the low-pass filter 34A, and the high frequency is cut off. (S) is separated and extracted and input to each of the system control circuit 10 and the clock generation circuit 37. The horizontal and vertical synchronization signals (S) input to the system control circuit 10 are:
For example, it is used for reading ID data. Further, the clock generation circuit 37 generates a memory write clock signal serving as a reference for writing to the memory, and the generated memory write clock signal is input to each of the A / D converter 38A and the memory control circuit 35. You.

The luminance signal (Y) that has been FM-demodulated and from which the horizontal and vertical synchronizing signals (S) have been separated is converted into a digital signal by an A / D converter 38A, and is converted into a Y memory 39.
A is temporarily stored at a predetermined address. The color difference signal (Pr) subjected to the FM demodulation passes through a low-pass filter 34B and is cut in a high frequency band, is converted into a digital signal by an A / D converter 38B, and is temporarily stored in a Pr memory 39B via a switch 61. Can be Similarly, the color difference signal (Pb) is passed through a low-pass filter 34C and cut in a high frequency band, and then converted into a digital signal by an A / D converter 38C.
9C.

The system control circuit 10 determines from the reproduced ID data whether the image signal read by the magnetic head 6 is an image signal belonging to the first field or an image signal belonging to the second field. Then, based on this, the operation of the memory control circuit 35 is controlled. The memory control circuit 35 controls each of the memories 39A based on the memory write clock signal from the clock generation circuit 37.
The following control is performed while setting the timing of writing to .about.39C.

That is, based on the memory write clock signal from the clock generation circuit 37, the A / D converter 38
A operates, and the memory control circuit 35 operates the built-in write address counter to write the digital data of the luminance signal (Y) to a predetermined address of the Y memory 16A.

The memory write clock signal from the clock generation circuit 37 is frequency-divided by 1/2 by the frequency divider 43A to operate the A / D converters 38B and 38C, and the memory control circuit 35 Activate the built-in write address counter to set Pr memory 39
Digital data of the color difference signal (Pr) and the color difference signal (Pb) are written into predetermined addresses of the B and Pb memories 39C, respectively. Note that the synchronization signal (S) included in a reproduced signal such as a luminance signal is not sampled,
Therefore, it is not written to memory.

From the synchronizing signal generating circuit 40, a horizontal and vertical synchronizing signal corresponding to a standard image signal, for example, a horizontal and vertical synchronizing signal (S) conforming to the NTSC system is output and input to the clock generating circuit 41. The clock generation circuit 41 generates a memory read clock signal as a reference for reading from each memory, and the memory read clock signal is input to the memory control circuit 35 and the D / A converter 42A. Further, this memory read clock signal is frequency-divided by a frequency divider 43B into １ ／, and then input to D / A converters 42B and 42C, respectively.

The memory control circuit 35 performs the following control based on the memory read clock signal from the clock generation circuit 41 while setting the timing of reading from each of the memories 39A to 39C. That is, based on the memory read clock signal from the clock generation circuit 41,
The memory control circuit 35 operates a built-in read address counter to read digital data of the luminance signal (Y) from a predetermined address of the Y memory 39A, and operates the D / A converter 42A to read the digital data. The digital signal of the luminance signal (Y) is converted into an analog signal.

Also, based on the memory read clock signal from the clock generation circuit 41, the memory control circuit 35
Operates a built-in write address counter to read digital data of a color difference signal (Pr) and a color difference signal (Pb) from predetermined addresses of the Pr memory 39B and the Pb memory 39C, respectively, and
The / A converters 42B and 42C operate to convert the read digital signals of the respective color difference signals into analog signals.

In the memory control circuit 35, the mode switching between the writing control and the reading control of the memory is controlled by a mode switching command signal from the system control circuit 10. The horizontal and vertical synchronizing signals (S) from the synchronizing signal separating circuit 36 and the horizontal and vertical synchronizing signals (S) from the synchronizing signal generating circuit 40 are also input to the system control circuit 10, respectively. The rotation phase control of the spindle motor 5 is performed on the basis of the above, and it is used as a timing signal for various other operations.

In reproducing such a standard image, the memory read clock signal from the clock generation circuit 41 and the memory write clock signal from the clock generation circuit 37 have the same frequency. Therefore, the frequency of the read clock signal of the luminance signal and the frequency of the write clock signal are the same, the frequency of the read clock signal of both color difference signals and the frequency of the write clock signal are the same, The frequency of the write and read clock signals is twice the frequency of the write and read clock signals of both color difference signals.

The luminance signal (Y), the color difference signal (Pr), and the color difference signal (Pb), which are analog signals, are respectively
The high band is cut by the low-pass filters 44A, 44B and 44C, and thereafter, the vertical and horizontal synchronization signals (S) from the synchronization signal generation circuit 40 are added to the luminance signal (Y) by the synchronization signal addition circuit 45A. .

The luminance signal (Y +
S), the color difference signal (Pr) and the color difference signal (Pb) are respectively passed through an encoder 47 to the composite video (N
TSC) signal, and a still image is reproduced on the connected display.

Next, a description will be given of a control operation in the case where an image signal is reproduced from the magnetic disk 3 by switching the reproduction processing method by the reproduction mode switching means. FIG. 9 is a flowchart showing a control operation when performing reproduction in the high-definition reproduction mode, and FIG. 10 is a flowchart showing a control operation when performing reproduction in the normal reproduction mode.

As shown in FIG. 13, when the last recording processing method of the recording system is determined to be the high-definition recording mode (Fr = 1) by the reproduction mode switching means, the reproduction processing method is set to the high-definition reproduction mode. (Steps 705 and 706). When the reproduction is performed in the high-definition reproduction mode, as shown in FIG. 9, the terminals h of the switches 61 to 63 are connected (step 401). Next, the synchronization signal generation circuit 40 is switched to the one for high definition (step 40).
2).

Next, clock generation circuits 37 and 41
The clocks generated in step (1) are switched to those for high definition (step 403). In this case, the clock generation circuit 41
The frequency of the clock generated by the clock generation circuit 37
4 times the frequency of the clock generated by

Next, each of the low-pass filters 44A to 44A
The 4C cutoff frequency is switched to a high definition (step 404). Specifically, each low-pass filter 44
A to 44C cut-off frequency is set to each D / A converter 42A.
サ ン プ リ ン グ of the sampling frequency of 42C.

By executing steps 401 to 404, the cutoff frequency of each of the low-pass filters 34A to 34C, the sampling frequency of each of the A / D converters 38A to 38C, the writing frequency to each of the memories 39A to 39C, and the respective memories 39A to 39C. Reading frequency from 39C,
Sampling frequency of each D / A converter 42A to 42C,
The cutoff frequency of each of the low-pass filters 44A to 44C is set as shown in Table 3 below.

[0147]

[Table 3]

After setting each frequency as shown in Table 3, each track on which the luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb) are recorded is reproduced, and the respective tracks are stored in the memories 39A to 39A. It is stored at a predetermined address of 39C (step 405).

Next, the luminance signal (Y), the color difference signal (Pr), and the color difference signal (Pb) stored in each of the memories 39A to 39C are simultaneously read and output to the monitor (step 406). Thus, in the high definition recording mode, the high definition image signal recorded in the track pattern shown in FIG. 4 is reproduced.

As shown in FIG. 13, when the last recording processing method of the recording system is determined to be the normal recording mode (Fr = 0) by the reproduction mode switching means, the reproduction processing method is set to the normal reproduction mode. (Steps 705 and 7
07). When the reproduction is performed in the normal reproduction mode, as shown in FIG. 10, the terminals n of the changeover switches 61 to 63 are respectively connected (step 501). Next, the synchronization signal generation circuit 40 is switched to the standard signal (step 502).

Next, clock generation circuits 37 and 41
Are switched to the standard clocks (step 503). In this case, the clock generation circuit 41
The frequency of the clock generated by the clock generation circuit 37
And the frequency of the clock generated in step (1).

Next, each of the low-pass filters 44A to 44A
The 4C cutoff frequency is switched to the standard frequency (step 504). Specifically, each low-pass filter 44A
~ 44C cut-off frequency of each D / A converter 42A ~
The sampling frequency is set to の of the sampling frequency of 42C.

By executing the steps 501 to 504, the cutoff frequency of each of the low-pass filters 34A to 34C, the sampling frequency of each of the A / D converters 38A to 38C, the writing frequency to each of the memories 39A to 39C, and each of the memories 39A to 39C Reading frequency from 39C,
Sampling frequency of each of the D / A converters 42A to 42C,
The cut-off frequency of each of the low-pass filters 44A to 44C is set as shown in Table 4 below.

[0154]

[Table 4]

After setting the respective frequencies as shown in Table 4 above, the track on which the image signal of the standard image is recorded is reproduced. For the luminance signal (Y), predetermined reproduction processing (luminance signal) is performed by the reproduction processing circuit 31A. The C signal reproduction processing circuit 31B performs predetermined reproduction processing (color difference signal reproduction processing) on the color difference signal (Pr) and the color difference signal (Pb), respectively. Pr) and the color difference signal (Pb) are stored at predetermined addresses of the memories 39A to 39C, respectively (step 505).

Next, the luminance signal (Y), the color difference signal (Pr) and the color difference signal (Pb) stored in each of the memories 39A to 39C are simultaneously read, and output to the monitor as a composite video signal through the encoder 47 (step 506). . Thus, the standard image signal recorded in the normal recording mode is reproduced.

Next, control for reproducing only an image signal recorded by the last recording processing method of the recording system at the time of reproduction will be described. FIG. 11 is a flowchart showing an example of a control operation when reproducing an image signal from each of the 50 tracks of the magnetic disk 3. Hereinafter, this flowchart will be described.

First, the magnetic head is transferred in the state where the predetermined reproduction processing method is set as described above, and is positioned on the first track (outermost track) of the magnetic disk (step 601). Next, the current track is reproduced and I
The D data is decoded, and the recording processing method of the image signal recorded on the current track is determined based on the ID data (step 602).

Next, the recording processing method of the image signal recorded on the current track is changed to the recording processing selection switch 81.
It is determined whether or not it matches the last recording processing method selected in (the last recording processing method of the recording system) (step 60).
3).

If it is determined in step 603 that the recording processing methods do not match, reproduction of the image signal recorded on the current track is prohibited (step 604). If it is determined in step 603 that the recording processing methods match, the image signal recorded on the current track is reproduced (step 605). That is, as described above, the reproduction is performed by the predetermined reproduction processing method, and the reproduced image signal is output to the monitor.

Next, it is determined whether or not the current track is the 50th track (the 50th track from the outermost track) based on the ID data (step 606). If it is determined in step 606 that the current track is not the 50th track, the magnetic head is moved to the inner circumference by one track and positioned on that track (step 60).
7) Returning to step 602, and again steps 602-6
Execute 06.

Then, step 607 and steps 602 to 606 are repeatedly executed in the same manner.
If it is determined at 06 that the current track is the 50th track, this program ends. In the present embodiment, in the flowchart shown in FIG. 11, the ID data is decoded for each track and the reproduction is performed. However, in addition to this, for example, the pre-search is performed for all the tracks and then the reproduction is performed. There may be.

The recording system of the still video apparatus 1 of the present embodiment shown in FIG. 1 has a configuration in which the recording mode switching means is operated by manual operation, but the present invention is not limited to this. In addition to this, for example, a mechanism for determining the type of image signal input to the recording system is provided. By this mechanism, the recording mode switching means automatically operates without manual operation, and the method of image signal May be switched to a recording processing method according to the above.

FIG. 12 shows a configuration example of a recording system of a still video device having such a discrimination mechanism. The still video device 1 shown in the drawing has a mechanism for determining the type of an image signal input to a recording system, and the recording system of the still video device 1 shown in FIG. They have substantially the same configuration. Although not shown, the playback system has substantially the same configuration as the playback system of the still video device 1 shown in FIG.

In this case, as a method of determining whether the image signal input to the recording system is a high-definition image signal or a standard image signal, the following methods (1) to (4) are exemplified. The following methods (1) to (4) are performed depending on the type of image signal, for one horizontal synchronization period and one vertical synchronization period (between the rise of one vertical synchronization signal of two adjacent vertical synchronization signals and the rise of the other vertical synchronization signal). )
The difference is used to determine the method of the image signal.

An arbitrary time is set by a timer, and the number of pulses of the horizontal synchronizing signal within the set time is measured (counted). Then, a predetermined number of pulses is set, and it is determined whether or not the measured number of pulses is larger than the set value. In this case, it is preferable that an intermediate pulse number is set as the set value in the high-definition image signal and the standard image signal.

For example, when discriminating between a HDTV signal and an NTSC signal, the time may be set to 1 ms and the set value α of the number of pulses may be set to about 17 to 36. In this case, if the measured number of pulses is larger than α, it is determined to be a Hi-Vision signal, and if it is smaller than α, it is determined to be an NTSC signal.

The time between two adjacent horizontal synchronization signals or the time between horizontal synchronization signals at both ends of three or more adjacent horizontal synchronization signals is measured. Then, a predetermined time is set, and it is determined whether or not the time measured from the set value is longer. In this case, it is preferable to set an intermediate time as the set value in the high-definition image signal and the standard image signal.

For example, when the time between two adjacent horizontal synchronizing signals is measured to discriminate between a Hi-Vision signal and an NTSC signal, the time setting value β may be set to about 30 to 63 μsec. In this case, if the measured time is shorter than β, it is determined to be a Hi-Vision signal, and if it is longer than β, it is determined to be an NTSC signal.

The number of pulses of the horizontal synchronization signal within one vertical synchronization period is measured (counted). Then, a predetermined number of pulses is set, and it is determined whether or not the measured number of pulses is larger than the set value. In this case, it is preferable that an intermediate pulse number is set as the set value in the high-definition image signal and the standard image signal.

For example, when discriminating between a Hi-Vision signal and an NTSC signal, the set value γ of the pulse number is set to 264 to 264.
It may be about 561. In this case, when the measured pulse number is larger than γ, it is determined that the signal is a high-definition signal,
If it is smaller than γ, it is determined that the signal is an NTSC signal.

Further, in this embodiment, the setting of each frequency is performed as shown in Tables 1 to 4. However, the setting of each frequency is not limited to this. The setting of each frequency can be changed in accordance with the method of the image signal input to the CPU, the frequency band of the image signal, the pattern of the screen division (the number of divisions in the screen horizontal direction, the number of divisions in the screen vertical direction, etc.).

Further, in this embodiment, the recording processing system and the reproduction processing system are configured to be switched between the high-definition mode and the normal mode, respectively.
The present invention may have a configuration in which the recording processing method and the reproduction processing method are each switched to three or more methods.

As described above, the reproduction is frequently performed by the reproduction processing method corresponding to the last recording processing method. However, exceptionally, an image other than the last recorded image may be reproduced. Since the still video cannot be played back when recorded in a recording processing method different from the recording processing method of the present invention, the still video device of the present invention is provided with means for releasing the above-described functions of the present invention as necessary. It may be.

Further, in this embodiment, a decoder 46 is mounted as shown in FIG. 1, and a color difference signal is obtained from the NTSC signal by the decoder 46.
The recording system may be configured such that the decoder 46 is omitted and the color difference signal decoded in advance or the color difference signal not encoded is directly input to the recording system. Further, the changeover switches 56 to 58 shown in FIG. 1 may be omitted. Further, in the present embodiment, the encoder 47 is mounted as shown in FIG. 2, but this encoder 47 may be omitted.

In the high-definition recording mode of this embodiment,
For an image signal corresponding to one screen, the ratio of the number of tracks on which the luminance signal (Y) is recorded, the number of tracks on which the color difference signal (Pr) is recorded, and the number of tracks on which the color difference signal (Pb) is recorded Is 4: 2: 2, but is not limited thereto, and may be, for example, 4: 1,: 1, 2: 2: 2, or the like.

In this embodiment, one magnetic head is provided for recording and reproducing image signals. However, a plurality of magnetic heads may be provided in each of the recording system and the reproducing system. In such a case, as each magnetic head, for example, a dedicated magnetic head provided for each of the luminance signal (Y), the color difference signal (Pr), and the color difference signal (Pb), or an image signal for one field Corresponding magnetic heads (in the case of the present embodiment, eight magnetic heads arranged side by side) are mentioned. In this embodiment, the case of frame recording has been described. However, the present invention can be applied to an apparatus capable of field recording.

In the high-definition recording mode of this embodiment,
Although the color difference signal (Pr) and the color difference signal (Pb) are recorded on different tracks, they may be recorded on the same one or more tracks. In this case, the color difference signal (P
r) and the color difference signal (Pb) are recorded in a line-sequential manner, and the color difference signal (Pr) and the color difference signal (Pb) are each divided into a plurality of pieces within one horizontal synchronization period (for example, divided into the first half and the second half). Recording method.

Further, in the present embodiment, recording or reproduction is sequentially performed on the image signal corresponding to one screen from the track on the outer peripheral side of the magnetic disk 3, but the present invention is not limited to this order. In the high-definition recording mode of the present embodiment, from the outer peripheral side of the magnetic disk 3 toward the inner peripheral side,
Luminance signals Y ₁ , Y ₂ , Y ₃ , Y _{4 of} the first field, color difference signals Pr ₁ , Pr ₂ , color difference signals Pb ₁ , Pb ₂ , _second signal
The luminance signals Y ₅ , Y ₆ , Y ₇ , Y ₈ , the color difference signals Pr ₃ , Pr ₄ , and the color difference signals Pb ₃ , Pb _{4 of the field} are sequentially recorded one by one on the magnetic disk 3. The track pattern is not limited to this.

In the present invention, the image signal recording medium is
It is not limited to a magnetic recording medium such as a magnetic disk, but may be an optical recording medium, a magneto-optical recording medium, or the like. As described above, the still video device of the present invention has been described based on the illustrated configuration example, but the present invention is not limited to this. In particular, any circuit having the same function is included in the present invention as to the circuit configuration of the recording system and the reproducing system.

[0181]

As described above, according to the still video apparatus of the present invention, the same apparatus uses different image signals,
For example, a high-definition image signal such as a Hi-Vision signal and N
A standard image signal such as a TSC signal can be recorded and reproduced.

In addition, since the mode is automatically switched to the reproduction processing method according to the last recording processing method of the recording system, the labor of the operator is remarkably reduced, and the reproduction processing method is not mistaken. Since only the image signal recorded by the last recording processing method of the recording system is reproduced, when reproducing a magnetic disk in which image signals with different recording processing methods are mixed, reproduction by an inappropriate reproduction processing method is performed. Can be prevented. Further, the still video device of the present invention
The circuit configuration is simple.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a recording system of a still video device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a reproduction system of the still video device of the present invention.

FIG. 3 is a schematic diagram showing an example of a storage area pattern of an image signal in each memory in a high definition recording mode.

FIG. 4 is a diagram showing an example of a track pattern formed on a magnetic disk in a high-definition recording mode.

FIG. 5 is a time chart showing a relationship between a luminance signal (Y) input to a recording system of a still video device and a luminance signal (Y) recorded on a track in a high definition recording mode.

FIG. 6 is a time chart showing a relationship between a color difference signal (Pr) input to a recording system of a still video device and a color difference signal (Pr) recorded on a track in a high definition recording mode.

FIG. 7 is a flowchart illustrating a control operation when recording is performed in a high-definition recording mode.

FIG. 8 is a flowchart illustrating a control operation when recording is performed in a normal recording mode.

FIG. 9 is a flowchart showing a control operation when performing reproduction in a high-definition reproduction mode.

FIG. 10 is a flowchart showing a control operation when performing reproduction in a normal reproduction mode.

FIG. 11 is a flowchart illustrating a control operation when reproducing an image signal.

FIG. 12 is a block diagram showing another configuration example of the recording system of the still video device of the present invention.

FIG. 13 is a flowchart illustrating a control operation when determining the last recording processing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Still video apparatus 2 Magnetic disk drive mechanism 3 Magnetic disk 4 Motor drive circuit 5 Spindle motor 6 Magnetic head 7 Tracking drive circuit 8 Operation part 81 Recording processing mode selection switch 10 System control circuit 11A, 11B, 11C Low pass filter 12 Memory control circuit Reference Signs List 13 synchronization signal separation circuit 14 clock generation circuit 15A, 15B, 15C A / D converter 16A Y memory 16B Pr memory 16C Pb memory 17A, 17B frequency divider 18 synchronization signal generation circuit 19 clock generation circuit 20A, 20B, 20C D / A converter 21A, 21B, 21C Low-pass filter 22A, 22B, 22C Synchronous signal adding means 23 Changeover switch 24A Recording processing circuit 24B C signal recording processing circuit 25 ID recording circuit 26 Adder 27 Recording amplifier 28 Erasure signal generation circuit 29 Changeover switch 30 Reproduction amplifier 31A Reproduction processing circuit 31B C signal reproduction processing circuit 32 ID reproduction processing circuit 33 Envelope detection circuit 34A, 34B, 34C Low-pass filter 35 Memory control circuit 36 Synchronization signal separation circuit 37 Clock Generation circuits 38A, 38B, 38C A / D converter 39A Y memory 39B Pr memory 39C Pb memory 40 Synchronous signal generation circuit 41 Clock generation circuits 42A, 42B, 42C D / A converters 43A, 43B Dividers 44A, 44B 44C Low-pass filter 45A, 45B, 45C Synchronization signal adding means 46 Decoder 47 Encoder 51-58 Changeover switch 61-63 Changeover switch 201- 211 Step 301-307 Step 401-4 6 step 501 to 506 601 to 607 step step 701 to 707 step

──────────────────────────────────────────────────の Continuation of the front page (51) Int.Cl. ⁷ identification code FI // H04N 101: 00 (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/956 H04N 9 / 79-9/898 H04N 101: 00

Claims (6)

(57) [Claims] 1. A still video apparatus comprising: a recording system that records an image signal corresponding to one screen on a recording medium; and a reproduction system that reproduces the image signal recorded on the recording medium. Has a recording mode switching unit that switches a recording processing method according to a method of the image signal input to a recording system, and the reproduction system changes a reproduction processing method according to a last recording processing method of the recording system. A still video device comprising a reproduction mode switching means for switching, and configured to reproduce only an image signal recorded by the last recording processing method. 2. The recording mode switching means switches the recording processing method to a recording processing method for recording a standard image signal or a recording processing method for recording a high-definition image signal. 2. The still video apparatus according to claim 1, wherein the means switches the reproduction processing method to a reproduction processing method for reproducing a standard image signal or a reproduction processing method for reproducing a high-definition image signal. 3. A recording processing method for recording the high-definition image signal, wherein the image signal includes a luminance signal and a color difference signal. 3. The still video apparatus according to claim 2, wherein recording is performed by dividing the data into tracks. 4. The still video apparatus according to claim 1, wherein said recording mode switching means is configured to be operated by a manual operation. 5. The reproduction mode switching means according to claim 1, wherein said reproduction mode switching means determines a last recording processing method of said recording system and switches to a reproduction processing method according to said recording processing method. 7. The still video device according to item 1. 6. The still video device according to claim 1, wherein the main components constituting the recording system are also used as some of the components constituting the reproduction system.