JP3198343B2 - Manufacturing method of three-dimensional integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit formed on a semiconductor substrate without damaging it by a high-temperature heat treatment.
The present invention relates to a method for manufacturing a highly integrated three-dimensional integrated circuit device by forming an integrated circuit having good electric characteristics with high alignment accuracy on the integrated circuit.

Heretofore, many means have been proposed for improving the degree of integration in a two-dimensional integrated circuit device. However, discussions have begun that two-dimensional high-integration technology will not be able to reach its end sooner or later, and technology for three-dimensional integration must be developed, and related technologies have been proposed. Although it has been a long time since such techniques can be used at the laboratory stage, there are few things that can be applied when actually mass-producing integrated circuit devices on a line. Therefore, although most integrated circuit devices that are currently in practical use are still two-dimensionally integrated, practically any technology for manufacturing a three-dimensional integrated circuit device has been developed. There must be.

[0003]

2. Description of the Related Art In recent years, a large capacity and low power consumption static random access memory (st
atic random access memory
In order to obtain a semiconductor integrated circuit formed on a silicon substrate via a layer insulating film, a three-dimensional integrated circuit device has been proposed to obtain, for example, a Y.SRAM (Y: SRAM) (if necessary, Y. Inoue et al. 5 Symp.
VLSI Tech. , Tech. Dig. , P. 3
9, 1989 "4 PMOS/2NMOS Verti
calli Stacked CMOS-SRAM w
is 0.6 μm Design Rule ”). In this proposed technology, a polycrystalline silicon film deposited on a bulk in which transistors are integrated via an interlayer insulating film is melted with an energy beam such as a laser beam, and then recrystallized. A three-dimensional integrated circuit device is obtained by forming a transistor on a crystal layer.

An electrical connection is made by joining an Au / In pool filled with an Au / In alloy to tungsten (W) bumps formed on one substrate and holes of a polyimide film formed on the other substrate. In addition, there has been proposed an idea of forming a three-dimensional integrated circuit device by bonding together semiconductor substrates on which an integrated circuit is formed (if necessary, Hayashi et al., "Semiconductor World,
September issue, p. 58, 1990 ").

[0005]

Among the prior arts described above, the technique of melting a polycrystalline silicon film with an energy beam and then recrystallizing the same is described in Japanese Patent Application Laid-Open No. H11-157,839.

It takes a lot of time to scan an energy beam to melt and recrystallize a polycrystalline silicon film. For example, a diameter of about 10 cm (4 cm) (4
It takes about 3 [hours] to process the entire surface of the [inch] wafer. As the number of layers of the recrystallized layer increases, the crystallinity in the recrystallized layer decreases. The heat generated during melting and recrystallization of the upper layer deteriorates the characteristics of the integrated circuit formed in the lower layer. There is such a problem.

[0007] Similarly, of the conventional techniques described above, the technique of bonding semiconductor substrates does not cause the problem of the melting and recrystallization technique described above. W bump and Au for connection
The position of the Au / In pool must be adjusted to 8 × 8 [μm, for example, since the position cannot be adjusted with high accuracy.
² ], it is necessary to provide a sufficient margin, so that the degree of integration is sacrificed.

In the present invention, when realizing a three-dimensional integrated circuit, it is possible to improve the degree of integration by realizing the alignment of the integrated circuit or the element with high precision, and to realize the three-dimensional integration of the substrate. It is intended to be able to perform the processing in a short time as in the case of the alignment technique, and not to sacrifice the crystallinity in the crystal layer forming the integrated circuit and the characteristics of the integrated circuit itself.

[0009]

SUMMARY OF THE INVENTION In the method of manufacturing a three-dimensional integrated circuit device according to the present invention, (1) an integrated circuit device is formed and used in an empty space between element groups in the integrated circuit device. Normal insulating film (for example, SiO ₂ film,
A first semiconductor substrate (for example, a p-silicon semiconductor substrate) on which alignment marks (for example, alignment marks 5) of a material (for example, polycrystalline silicon) different from a Si ₃ N ₄ film, a PSG film, a BPSG film, and the like are formed. 1) a step of planarizing the deposited an insulating film (e.g., a PSG film 8 and the SiO ₂ film 10) on, then, to form a concave plants (e.g. groove 11A) at a position corresponding to the cavity on the surface Embed the recess
To form an insulating film (eg, SiO ₂ film 12) on the entire surface
After that, the insulating film (for example, the n-silicon semiconductor substrate 11) and the first semiconductor substrate, each of which is flattened, are covered with an insulating film (for example, the SiO ₂ film 12 and the SiO ₂ film 10). A step of sticking closely together so as to face each other, and then a step of performing thinning from the back surface of the second semiconductor substrate and stopping at a stage where the insulating film embedded in the recess is exposed, and Detecting an alignment mark and performing alignment with an integrated circuit device formed on the first semiconductor substrate, and then forming an integrated circuit device on the thinned second semiconductor substrate. Or

(2) In the above (1), after the second semiconductor substrate is thinned, the insulating films stacked over the voids are selectively removed to position the alignment mark. Characterized by including a step of expressing
Or,

An insulating film is formed on a first semiconductor substrate in which an integrated circuit device is formed and alignment marks made of a material different from a normal insulating film used in the integrated circuit device are formed in the spaces between the element groups. A step of depositing and planarizing, and then a buried oxide layer (eg, S
A second semiconductor substrate having a buried oxide layer 20 formed by the IMOX method and having a flat insulating film (for example, an SiO ₂ film 21) on the surface thereof, and each of the first semiconductor substrates facing each other. And a step of performing thinning from the back surface of the second semiconductor substrate and stopping at the stage where the buried oxide layer is exposed, and then removing the buried oxide layer. Before
A step of exposing the semiconductor layer obtained by thinning the second semiconductor substrate, and then detecting the alignment mark to align the semiconductor layer with the integrated circuit device formed on the first semiconductor substrate. And then thinning the second semiconductor substrate
Or a step of manufacturing an integrated circuit device in the obtained semiconductor layer , or

In the above (2), after exposing a semiconductor layer obtained by thinning the second semiconductor substrate , each insulating film laminated so as to cover the space and Characterized by comprising a step of selectively removing the semiconductor layer obtained by thinning the semiconductor substrate to expose the alignment mark, or

(5) In the above (1) or (2) or (3) or (4), the element group is a block in which a required plurality of elements are formed, and the space is each block. Or a step of flattening after depositing an insulating film on the first semiconductor substrate, which is a line region to be independently separated, or

(6) In the above (1), (2), (3), or (4), a scribe line in which the element group constitutes one chip and the space separates each chip independently. A step of depositing an insulating film on the first semiconductor substrate which is a region and then planarizing the insulating film.

[0015]

According to the present invention, irrespective of the number of stacked semiconductor substrates, when the integrated circuit device is formed on the second or higher semiconductor substrate, the integrated circuit device is always formed on the first semiconductor substrate. Since the alignment can be performed by using the alignment mark formed at that time, the alignment accuracy is no different from that in the ordinary integrated circuit device manufacturing process, and therefore, the Au / In pool method or the like can be used. Such a large alignment margin is not required, and the semiconductor substrate of the second layer or more can be set to the minimum limit thickness for forming the element, so that the amount of etching at the time of patterning is small, and the step height is small. Due to the small size, fine elements, electrodes, wirings, and the like can be three-dimensionally integrated with high accuracy.

Further, the alignment mark formed on the first semiconductor substrate can be accurately detected irrespective of whether it is exposed or not, and is generally used in integrated circuit devices. It is possible to detect even when covered with an insulating film. Furthermore, even if the number of stacked semiconductor substrates increases, there is no danger that the crystallinity of the semiconductor will be reduced, and the productivity will be higher than that of annealing by an energy beam. Many similar benefits can be enjoyed.

[0017]

1 to 7 are cutaway side views of a main part of an integrated circuit device at a process essential point for explaining a first embodiment of the present invention, and refer to these drawings. This will be described in detail.

FIG. 1 1- (1) By applying a standard technique, an ordinary MIS (metal insulator) is formed on a first silicon semiconductor substrate.
An integrated circuit device is formed by fabricating a field effect transistor.

The illustrated first-layer integrated circuit device may depend on any technique unless it is a very specific technique. In short, it is only necessary to form a MIS field-effect transistor. Therefore, a detailed description will not be given of the manufacturing process up to the formation of the gate electrode and the source and drain regions. Therefore, here, a part of the configuration of the integrated circuit device will be described together with symbols.

In FIG. 1, reference numeral 1 denotes a p-silicon semiconductor substrate, and 2 denotes, for example, a silicon nitride (Si ₃ N ₄ ) film laminated on an extremely thin silicon dioxide (SiO ₂ ) film as an oxidation-resistant mask film. Thermal oxidation (local oxida
SiO ₂ having a thickness of, for example, 600 [nm] formed by applying a T.I.O.
The field insulating film 3 is made of, for example, 25 nm thick Si formed on the active region of the p-silicon semiconductor substrate 1 exposed by removing the oxidation-resistant mask film and the like.
A gate insulating film made of O ₂ , 4 is a gate electrode made of polycrystalline silicon formed on the gate insulating film 3, and 5 is an alignment mark made of polycrystalline silicon formed in the scribe line region simultaneously with the gate electrode 4. Reference numeral 6 denotes an n ⁺ -source region formed by a self-alignment method using the gate electrode 4 as a mask, and reference numeral 7 denotes an n ⁺ -drain region formed by a self-alignment method using the gate electrode 4 as a mask.

1- (2) Chemical vapor deposition
For example, a phosphor silicate glass (pho
A spo-silicate glass (PSG) film 8 is formed. 1- (3) Reactive ion etching (reactive ion etc) using a resist process and an etching gas of CF ₄ / CHF ₃ in a usual lithography technique
hing: RIE), the PSG film 8 and the gate insulating film 3 are selectively etched to obtain n ⁺
Forming an electrode contact hole on the source region 6;

1- (4) The thickness is, for example, 300 [n] by applying the CVD method.
m] is formed. Before forming the W polycide film, the PSG film 8 may be reflowed as necessary to smooth the surface. 1- (5) Patterning of a W polycide film to form an inter-element wiring 9 by applying a resist process in an ordinary lithography technique and an RIE method using CCl ₄ / O ₂ as an etching gas I do.

1- (6) By applying the CVD method, a thickness of, for example, 600
[Nm] SiO ₂ film 10 is formed. 1- (7) SiO ₂ film 1 by applying etch-back method
After the flattening to zero, the flatness on the surface of the SiO ₂ film 10 is further improved by applying a mirror polishing method. Through this step, the average thickness of the SiO ₂ film 10 is reduced to, for example, about 300 [nm].

Referring to FIG. 2, 2- (1) n- which is a second silicon semiconductor substrate is obtained by applying a resist process in lithography and an RIE method in which an etching gas is CCl ₄ / O _2. Selectively etching the surface of the silicon semiconductor substrate 11,
A groove 11A having the same shape as the scribe line region in the p-silicon semiconductor substrate 1 as the first silicon semiconductor substrate and having a depth of, for example, 0.5 [μm] is formed. 2- (2) By applying the CVD method, the thickness, for example, 1 [μ]
m] of the SiO ₂ film 12 is formed.

2- (3) The SiO ₂ film 1 is formed by applying the etch-back method.
After the flattening of Step 2, the flatness on the surface of the SiO ₂ film 12 is further improved by applying a mirror polishing method. Through this step, the SiO ₂ film 12 becomes the groove 1
The thickness corresponding to 1A is, for example, about 700 [nm]. It should be noted that the processing of the p-silicon semiconductor substrate 1 and the processing of the n-silicon semiconductor substrate 11 may be performed in any order, and may be performed simultaneously.

Referring to FIG. 3, 3- (1) SiO ₂ film 10 on p-silicon semiconductor substrate 1 and SiO ₂ film 12 on n-silicon semiconductor substrate 11
Are adhered to each other so that the scribe line areas overlap with each other, and are heated in a nitrogen (N ₂ ) atmosphere at a temperature of 900 ° C., for example.

Incidentally, the p-silicon semiconductor substrate 1 and n
When the alignment with the silicon semiconductor substrate 11 is performed, the target of the p-silicon semiconductor substrate 1 cannot be seen through the n-silicon semiconductor substrate 11 using a visible light microscope.

Then, the p-silicon semiconductor substrate 1 is viewed using an infrared microscope. The alignment accuracy by the infrared microscope is at most two to two due to the wavelength of infrared rays.
Although it is about 4 [μm], which is extremely difficult with a fine alignment mark, in the present embodiment, the role of the alignment mark in this case is the scribe line area, and its width is actually Since it is about 80 [μm], alignment can be easily performed, which is one of the great advantages of the present invention.

FIG. 4 4- (1) For example, the n-silicon semiconductor substrate 11 is thinned from the back side by applying a selective polishing method using colloidal silica as an etchant. Here, colloidal silica used as the etchant, but is to etch the silicon, since SiO ₂ is hardly etched, SiO ₂ thin film of n- silicon semiconductor substrate 11 is embedded in the groove 11A proceeds When the film 12 is exposed, the selective polishing is substantially stopped.

After this step, an island-shaped silicon film was formed on the integrated circuit device formed on the p-silicon semiconductor substrate 1 via an insulating film such as the SiO ₂ film 10 or the SiO ₂ film 12. Will be. However, for the sake of simplicity, the island-shaped silicon film thus obtained is also referred to as n-silicon semiconductor substrate 11.

Referring to FIG. 5, 5- (1) SiO ₂ film 12, SiO ₂ film 10, PSG in the scribe line region by applying the RIE method using CF ₄ / CHF ₃ as an etching gas. The film 8 and the gate insulating film 3 are removed by anisotropic etching to expose the alignment marks 5 made of polycrystalline silicon. When performing this etching, since the exposed SiO ₂ film is only in the scribe line region, a process such as forming a mask made of a resist film by applying a resist process is unnecessary. is there.

5- (2) The island-shaped n-silicon semiconductor substrate 11 is formed into a mesa shape by applying a resist process in the lithography technique and an RIE method using CCl ₄ / O ₂ as an etching gas. The insulation is separated by etching. 5- (3) A gate insulating film 13 made of SiO _{2 having} a thickness of, for example, 25 [nm] is formed by applying a thermal oxidation method at a temperature of, for example, 900 [° C.]. In this case, the same alignment film 5 as the gate insulating film 13 is formed on the alignment mark 5 made of polycrystalline silicon and the p-silicon semiconductor substrate 1 exposed in the scribe line region. In No. 5, since the shape has already appeared, even if it is covered with the SiO ₂ film, there is no influence on the detection by visible light.

6- (1) By applying a resist process in the lithography technique and an RIE method using CF ₄ / CHF ₃ as an etching gas, the SiO ₂ film 12, the SiO ₂ film 10,
The PSG film 8 and the gate insulating film 3 are anisotropically etched to form an electrode contact hole corresponding to the n ⁺ -drain region 7. 6- (2) The thickness is, for example, 300 [n] by applying the CVD method.
m] is formed.

6- (3) The W-polycide film formed in the above-mentioned step 6- (2) by applying a resist process in the lithography technique and an RIE method using CCl ₄ / O ₂ as an etching gas. To form an interlayer wiring 15 connecting the gate electrode 14 and the n ⁺ -drain region 7 formed on the p-silicon semiconductor substrate 1 to the p ⁺ -drain region formed later on the n-silicon semiconductor substrate 11. Form. 6- (4) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁵ [cm ⁻² ], the ion acceleration energy is set to 15 [keV], and B ⁺ is implanted to perform p ⁺ Forming a source region 16 and ap ⁺ -drain region 17;

FIG. 7 7- (1) The thickness is, for example, 600 [n] by applying the CVD method.
m] is formed. 7- (2) A temperature of 900 ° C. and a time of 30 in an N ₂ atmosphere
Annealing for [minutes] is performed to smooth the PSG film 18.

7- (3) The PSG film 18 is selectively etched by applying a resist process in the lithography technique and a RIE method using CF ₄ / CHF ₃ as an etching gas. An electrode contact hole corresponding to the p ⁺ -source region 16 formed in the semiconductor substrate 11 is formed. 7- (4) By applying the sputtering method, a thickness of, for example, 1
[Μm] Al film is formed, and then the resist process and etching gas in lithography are
By applying the RIE method of l ₂ / BCl ₃ ,
The wiring 19 is formed by patterning the Al film.

In the three-dimensional integrated circuit device manufactured according to the above-described steps, an n-channel transistor is formed in the p-silicon semiconductor substrate 1 as the first silicon semiconductor substrate, and the second The n-silicon semiconductor substrate 11, which is a silicon semiconductor substrate, has a configuration in which a p-channel transistor is formed. As is clear from the configuration of the electrodes and wirings, the n-silicon semiconductor substrate 11 is formed on the p-silicon semiconductor substrate 1. n ^{+ in} n-channel transistor
The source region 6, that is, the inter-element wiring 9 to the ground-side power supply level (= V _SS ) supply line, and the p ⁺ -source region 16 in the p-channel transistor formed in the n-silicon semiconductor substrate 11. Therefore, the wiring 19 is connected to the positive power supply level (= V _cc ) supply line, and the gate electrode 4 in the n-channel transistor and the gate electrode 14 in the p-channel transistor are each paired. And a cross connection between the gate electrode so connected and the interlayer wiring 15 is performed, and the transfer gates connected to the bit lines and the word lines are connected.
If the transistor and the interlayer wiring 15 are connected, the transistor can be operated as a CMOS type memory in the SRAM.

In the above-described embodiment, the p-silicon semiconductor substrate 1 as the first silicon semiconductor substrate and the n-silicon semiconductor substrate as the second silicon semiconductor substrate in which the integrated circuit device is built. When various processes are performed in a process after bonding with the substrate 11, the alignment marks 5 formed on the p-silicon semiconductor substrate 1, which is the first silicon semiconductor substrate, are all detected by visible light. n
The elements formed on the silicon semiconductor substrate 11 can be aligned with a high degree of accuracy, as in the case of forming the elements on the p-silicon semiconductor substrate 1; Can be easily formed.

In the case where three or more layers are laminated, this is realized by simply repeating the above-described step of forming the second layer. In this case as well, as described above, the positioning for performing various processes is performed. By using the alignment mark 5 formed on the p-silicon semiconductor substrate 1, high accuracy can be realized.

In the above-described embodiment, the SiO ₂ film 1 existing in the scribe line region is used.
1, the alignment marks 5 are exposed by anisotropically etching the SiO ₂ film 10, the PSG film 8, and the like. However, such steps may not be required in some cases.

The reason is that insulating films used in ordinary integrated circuit devices, for example, SiO ₂ films, Si ₃ N ₄ films,
In the case of a PSG film or the like, this is because the alignment mark 5 can be detected therethrough. For this purpose, the material of the alignment mark 5 is made different from that of a general insulating film in an integrated circuit device. In particular, in the case of a translucent material, the refractive index is different and the shape thereof is changed. Preferably, it can be easily detected. Here, note that, in the case of manufacturing a three-dimensional integrated circuit device, a first-layer integrated circuit device is manufactured as a positioning mark regardless of the number of stacked semiconductor substrates. It is indispensable for the formation of a fine element to use the one provided at the time to the last.
Therefore, if the alignment mark is formed in the scribe line area as shown in the above-described embodiment, its detection is always easy. However, the formation of the alignment mark in the scribe line area is not essential. As long as the integrated circuit device has a plurality of blocks each having a required number of elements in a chip, the integrated circuit device may be formed in a space between the element blocks. In such a case, in order to apply the technique of the above-described embodiment, a recess such as a groove or a void is formed at a position where the alignment mark can be seen with respect to the semiconductor substrate to be bonded and formed as an upper layer. It is preferable to use a material whose recess is filled with an insulating film of a material different from that of the alignment mark, or a structure in which the insulating film covering the alignment mark can be selectively and easily removed. preferable.

As described above, in order to form a fine element with high precision, even when an integrated circuit device of the second layer or an integrated circuit device of a higher layer is formed, the first layer Alignment marks formed on the integrated circuit device of the eye must be used. Therefore, after laminating two semiconductor substrates, it is not possible to implement an integrated circuit device on one side of the semiconductor substrate and also to integrate an integrated circuit device on the other side of the semiconductor substrate. It is. The reason is that the alignment mark formed when the integrated circuit device is formed on the semiconductor substrate on one side cannot be detected through the semiconductor substrate on the other side.

In the first embodiment and various modifications thereof, a recess such as a groove is formed in the second silicon semiconductor substrate to be bonded to the first silicon semiconductor substrate, and the recess is formed. The alignment mark is filled with an insulator made of a material different from that of the alignment mark. However, a silicon semiconductor substrate having no such a recess can be used, which will be described below.

FIGS. 8 to 13 are cut-away side views of a main part of an integrated circuit device at important points in a process for explaining a second embodiment of the present invention. This will be described in detail. The same symbols as those used in FIGS. 1 to 7 represent the same parts or have the same meaning. Also, in this embodiment, the first silicon semiconductor substrate in which the integrated circuit device is fabricated is the same as that shown in FIG. 1 described in the first embodiment, so that the description is omitted.

FIG. 8 8- (1) SIMOX (separation by impla)
By applying the oxidized oxygen method, the dose is set to, for example, 1 × 10 ¹⁷ [cm ⁻² ], the ion acceleration energy is set to, for example, 40 [keV], and O ⁺ is used as a second silicon semiconductor substrate. It is injected into the substrate 11. In this step, if necessary, the dose of O ⁺ is set to 1 ×
The ion acceleration energy is in the range of 10 ¹⁷ [cm ⁻² ] to 1 × 10 ¹⁸ [cm ⁻² ] and the ion acceleration energy is in the range of 80 [keV] to 200.
Each can be selected in the range of [keV].

8- (2) Heat treatment is performed in an Ar atmosphere at a temperature of 1300 ° C. and a time of 6 hours. According to this process,
A buried oxide layer 20 having a thickness of 100 [nm] is formed at a depth of 50 [nm] from the surface. 8- (3) The SiO ₂ film 2 having a thickness of, for example, 30 [nm] is formed on the surface of the n-silicon semiconductor substrate 11 by applying the thermal oxidation method.
Form one.

9- (1) SiO ₂ film 10 on p-silicon semiconductor substrate 1 and SiO ₂ film 21 on n-silicon semiconductor substrate 11
Are adhered to each other and heated in a nitrogen (N ₂ ) atmosphere at a temperature of 900 ° C., for example. In this case, the p-silicon semiconductor substrate 1 and n
-Approximate alignment of the facet with the silicon semiconductor substrate 11 is sufficient.

10- (1) For example, the n-silicon semiconductor substrate 11 is thinned from the back side by applying a selective polishing method using colloidal silica as an etchant. Here, the thinning of the n-silicon semiconductor substrate 11 progresses, and the buried oxide layer 20 is formed.
Is displayed, the selective polishing is substantially stopped.

10- (2) The buried oxide layer 20 is formed by applying a chemical wet etching method using hydrofluoric acid as an etchant.
Is removed by etching. Here, the hydrofluoric acid used as an etchant etches SiO ₂ , but silicon is hard to etch, so that the etching of the buried oxide layer 20 progresses and n-
When the silicon semiconductor substrate 11 is exposed, the etching is substantially stopped.

After this step, a thickness of 35 nm is formed on the integrated circuit device formed on the p-silicon semiconductor substrate 1 via an insulating film such as the SiO ₂ film 10 or the SiO ₂ film 21.
Is formed, which is also referred to as n-silicon semiconductor substrate 11.

11- (1) The resist process and the etching gas in the lithography technique are CCl ₄ / O ₂ (for silicon) and C
RIE with F ₄ / CHF ₃ (for SiO ₂ and PSG)
By applying the method, the n-silicon semiconductor substrate 11, SiO ₂ film 21, S
The iO ₂ film 10, the PSG film 8, and the gate insulating film 3 are removed by anisotropic etching to expose the alignment marks 5 made of polycrystalline silicon.

For the positioning of the patterning in the resist process at the time of performing this etching, rough positioning using infrared rays is sufficient because the width of the scribe line region is as large as 80 μm. Needless to say, visible light may be used for alignment in the subsequent steps.

11- (2) The thinned n-silicon semiconductor substrate 11 is formed into a mesa shape by applying a resist process in lithography and an RIE method using CCl ₄ / O ₂ as an etching gas. To perform insulation separation. 11- (3) A gate insulating film 13 made of SiO _{2 having} a thickness of, for example, 25 [nm] is formed by applying a thermal oxidation method at a temperature of, for example, 900 [° C.].

Referring to FIG. 12, 12- (1) The SiO ₂ film 21, the SiO ₂ film 10, and the resist process in the lithography technique and the RIE method in which the etching gas is CF ₄ / CHF ₃ are applied.
The PSG film 8 and the gate insulating film 3 are anisotropically etched to form an electrode contact hole corresponding to the n ⁺ -drain region 7. 12- (2) The thickness is, for example, 300 [n] by applying the CVD method.
m] is formed.

12- (3) The W polycide film formed in the step 12- (2) by applying a resist process in lithography and an RIE method using CCl ₄ / O ₂ as an etching gas. To form an interlayer wiring 15 connecting the gate electrode 14 and the n ⁺ -drain region 7 formed on the p-silicon semiconductor substrate 1 to the p ⁺ -drain region formed on the n-silicon semiconductor substrate 11 later. Form. 12- (4) By applying the ion implantation method, the dose is set to, for example, 1 × 10 ¹⁵ [cm ⁻² ], the ion acceleration energy is set to 15 [keV], and B ⁺ is implanted to perform p ⁺ Forming a source region 16 and ap ⁺ -drain region 17;

Referring to FIG. 13, 13- (1) The thickness is, for example, 600 [n] by applying the CVD method.
m] is formed. 13- (2) A temperature of 900 [° C.] and a time of 30 in an N ₂ atmosphere
Annealing for [minutes] is performed to smooth the PSG film 18. 13- (3) The PSG film 18 is selectively etched by applying the resist process in the lithography technique and the RIE method in which the etching gas is CF ₄ / CHF _3, and Then, an electrode contact hole corresponding to the p ⁺ -source region 16 formed in the step (a) is formed.

13- (4) A thickness of, for example, 1
[Μm] Al film is formed, and then the resist process and etching gas in lithography are
By applying the RIE method of l ₂ / BCl ₃ ,
The wiring 19 is formed by patterning the Al film. Also in the second embodiment described above, in order to laminate three or more layers, the second layer forming step may be repeated. Although silicon is used as the semiconductor material in any of the above-described embodiments, the present invention can be implemented when other semiconductor materials are used.

[0058]

In the method for manufacturing a three-dimensional integrated circuit device according to the present invention, an alignment mark made of a material different from that of a normal insulating film is formed in the space between the element groups in which the integrated circuit device is formed. An insulating film is deposited on the formed first semiconductor substrate and then planarized, and the second semiconductor substrate having the flat insulating film on the surface and the first semiconductor substrate are in close contact with each other so that the insulating films face each other. Attachment, stop when the insulating film is exposed by thinning from the back surface of the second semiconductor substrate, detect alignment marks and align with the integrated circuit device formed on the first semiconductor substrate. An integrated circuit device is fabricated on a thin second semiconductor substrate.

According to the above configuration, regardless of the number of stacked semiconductor substrates, when the integrated circuit device is formed on the second or higher semiconductor substrate, the integrated circuit device is always formed on the first semiconductor substrate. Since the alignment can be performed by using the alignment mark formed at that time, the alignment accuracy is no different from that in the ordinary integrated circuit device manufacturing process, and therefore, the Au / In pool method or the like can be used. A large alignment margin is not required as described above, and the semiconductor substrate of the second layer or more can be set to the minimum limit thickness for forming an element, so that the amount of etching at the time of patterning is small and the step is small. Due to the small size, fine elements, electrodes, wirings, and the like can be highly integrated three-dimensionally with high accuracy.

Further, the alignment mark formed on the first semiconductor substrate can be accurately detected irrespective of whether it is exposed or not, and is generally used in integrated circuit devices. It is possible to detect even when covered with an insulating film. Furthermore, even if the number of stacked semiconductor substrates increases, there is no danger that the crystallinity of the semiconductor will be reduced, and the productivity will be higher than that of annealing by an energy beam. Many similar benefits can be enjoyed.

[Brief description of the drawings]

FIG. 1 is a cutaway side view of a main part of an integrated circuit device at a key point in a process for explaining a first embodiment.

FIG. 2 is a cutaway side view of a main part of the integrated circuit device at a key point in the process for explaining the first embodiment;

FIG. 3 is a cutaway side view of a main part of the integrated circuit device at a key point in the process for explaining the first embodiment;

FIG. 4 is a cutaway side view of a main part of the integrated circuit device at a key point in the process for explaining the first embodiment;

FIG. 5 is a cutaway side view of a main part of the integrated circuit device at a key point in the process for explaining the first embodiment;

FIG. 6 is a cutaway side view of a main part of the integrated circuit device at a key point in the process for explaining the first embodiment;

FIG. 7 is a cutaway side view of a main part of the integrated circuit device at a key point in the process for explaining the first embodiment;

FIG. 8 is a cutaway side view of a main part of the integrated circuit device at a key point in the process for explaining the second embodiment;

FIG. 9 is a cutaway side view of a main part of the integrated circuit device at a key point in the process for explaining the second embodiment;

FIG. 10 is a cross-sectional side view of a main part of an integrated circuit device at a process key point for explaining a second embodiment;

FIG. 11 is a cutaway side view of a main part of the integrated circuit device at a key point in the process for explaining the second embodiment;

FIG. 12 is a cross-sectional side view of a main part of an integrated circuit device at a process key point for explaining a second embodiment;

FIG. 13 is a cutaway side view of a main part of the integrated circuit device at a key point in the process for explaining the second embodiment;

[Explanation of symbols]

Reference Signs List 1 p-silicon semiconductor substrate 2 field insulating film 3 gate insulating film 4 gate electrode 5 alignment mark 6 n ⁺ -source region 7 n ⁺ -drain region 8 PSG film 9 inter-device wiring 10 SiO ₂ film 11 n-silicon semiconductor substrate 11A grooves 12 SiO ₂ film 13 gate insulating film 14 gate electrode 15 layer interconnects 16 p ⁺ - source region 17 p ⁺ - drain region 18 PSG film 19 wiring 20 buried oxide layer 21 SiO ₂ film

Claims (6)

(57) [Claims] An insulating film is formed on a first semiconductor substrate in which an integrated circuit device is formed and an alignment mark made of a material different from a normal insulating film used in an integrated circuit device is formed in a space between element groups. planarizing the deposited film, then, the insulating film after forming the entire surface insulating film so as to fill the recess to form a concave plant at a location corresponding to the cavity on the surface A step of closely bonding each of the planarized second semiconductor substrate and the first semiconductor substrate so that the respective insulating films face each other, and then performing thinning from the back surface of the second semiconductor substrate, A step of stopping at a stage where the insulating film embedded in the recess is exposed, and then, after detecting the alignment mark and aligning with the integrated circuit device formed on the first semiconductor substrate, The thinned second semiconductor Method for producing a three-dimensional integrated circuit device characterized by comprising contains the steps to fabricate an integrated circuit device to the substrate. 2. The method according to claim 1, further comprising the step of thinning the second semiconductor substrate and then selectively removing each of the insulating films stacked over the space to expose the alignment mark. The method for manufacturing a three-dimensional integrated circuit device according to claim 1, wherein 3. An insulating film is formed on a first semiconductor substrate in which an integrated circuit device is formed and an alignment mark made of a material different from a normal insulating film used in the integrated circuit device is formed in a space between element groups. A step of depositing a film and then planarizing, and then a second semiconductor substrate having a buried oxide layer on the surface at a required depth from the surface and having a flat insulating film on the surface, and the first semiconductor substrate. A step of adhering and bonding them so that the respective insulating films face each other, and then a step of performing thinning from the back surface of the second semiconductor substrate and stopping at a stage where the buried oxide layer is exposed, Removing the buried oxide layer and removing the second semiconductor
The body substrate comprising the steps of expose the semiconductor layer obtained by thinning, then after the alignment of the said alignment mark detected formed on the first semiconductor substrate integrated circuit device Semiconductor obtained by thinning the second semiconductor substrate
Manufacturing a three-dimensional integrated circuit device in a body layer . 4. A thin film obtained by thinning the second semiconductor substrate.
After exposing the semiconductor layer, the respective insulating films and the second semiconductor substrate that are stacked to cover the voids are thinned.
4. The method for manufacturing a three-dimensional integrated circuit device according to claim 3, further comprising a step of selectively removing the obtained semiconductor layer to expose an alignment mark. 5. The method according to claim 1, wherein said element group is a block in which a plurality of required elements are formed, and said space is a line region for separating each block independently. 5. The method for manufacturing a three-dimensional integrated circuit device according to claim 1, further comprising a step of flattening. 6. A step of depositing an insulating film on a first semiconductor substrate in which said element group forms one chip and said space is a scribe line region for separating each chip independently, and then planarizing said insulating film. The method of manufacturing a three-dimensional integrated circuit device according to claim 1, wherein the method comprises: