JP3197920B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit with high integration and high speed. In recent years, in order to achieve high integration and high speed of a semiconductor integrated circuit, in a MOS transistor, a gate width is reduced, and a thickness of an oxide film is made thinner than usual, for example, 130 to 140 ° or less. Type LSI (La
rge Scale Integrated circuit) has been developed.

However, the power supply voltage of MOS-type LSIs in recent years is mainly 5 V, and in fields where the power consumption needs to be reduced, 5 V or less, for example, 3.
Since a power supply voltage of 3 V is used, when mixed with an LSI used with a mainstream power supply voltage of 5 V, it cannot be used as it is because of the breakdown voltage of the MOS circuit.

Therefore, an LSI having a breakdown voltage equal to or lower than a reference voltage is used.
Therefore, a semiconductor integrated circuit in which measures are taken for the case of mixing in a circuit is required.

[0004]

2. Description of the Related Art Conventionally, the following measures have been taken in semiconductor integrated circuits in fields requiring high breakdown voltage. That is, in order to improve the breakdown voltage between the source and the drain together with the breakdown voltage of the gate oxide film, the gate oxide film T _ox
And the electric field E of the diffusion layer is lowered (E = V /
_Tox ), the diffusion layer is deepened, and the electric field E applied to the diffusion layer is reduced.

However, in order to improve the speed, the thickness of the gate oxide film of the MOS transistor to be used is made thinner than usual. In this case, only the oxide film in the portion to which a high voltage is applied is thickened. Technology is used. To explain this in detail, first, after forming an oxide film once,
The oxide film is formed twice by removing the necessary portion of the oxide film and oxidizing it again to form an oxide film thicker than usual.

[0006]

However, in such a conventional semiconductor integrated circuit, an oxide film is formed twice so that an oxide film thicker than usual is formed. There was a problem as described. That is, 1. Since the oxide film once applied is removed and oxidized again, contamination occurs in the oxide film applied first.

[0007] 2. Fine holes are formed during etching,
This causes a decrease in withstand voltage. 3. Since the manufacturing process becomes complicated, the manufacturing cost increases. Further, when the diffusion layer is made deeper, the diffusion layer also spreads in the lateral direction and the gate width is increased, so that the speed and the degree of integration are reduced, and there is a problem that high integration and high speed cannot be achieved. .

[0008] Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit having a sufficient withstand voltage while reducing the thickness of a gate oxide film.

[0009]

According to the present invention, in order to achieve the above object, an external signal is input to an internal circuit through an input terminal.
In a semiconductor integrated circuit, the drain of a MOS transistor
And the input terminal of the MOS transistor.
A source connected to the internal circuit;
A CR time constant circuit is provided between the gate of
Has a configuration was.

[0010]

[0011]

[0012]

According to the present invention, even when a signal having a voltage level higher than the withstand voltage of the internal circuit is input to the input terminal by the MOS transistor provided between the input terminal and the internal circuit, the maximum voltage level of the MOS transistor is reduced. The predetermined voltage value applied to the gate of the transistor is suppressed.

That is, even if the gate oxide film inside the semiconductor integrated circuit is formed thinner with emphasis on high speed, a sufficient withstand voltage is ensured.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 4 are diagrams showing a first embodiment of a semiconductor integrated circuit according to the present invention, FIG. 1 is a circuit diagram showing a configuration of a main part thereof, FIG. 2 is a diagram showing characteristics at each node in FIG. , 4 are enlarged views of main parts of FIG.

First, the configuration will be described. The semiconductor integrated circuit of this embodiment is roughly classified into a pad 1 as an input terminal, an ESD protection circuit 2 as an input protection circuit, a level conversion circuit 3,
The level conversion circuit 3 includes an N-channel MOS transistor 5, and the inverter 4 includes a P-channel MOS transistor 6 and an N-channel MOS transistor 6.
It comprises a channel MOS transistor 7.

In FIG. 1, the symbols "-" indicate nodes at respective points. The N-channel MOS transistor 5 constituting the level conversion circuit 3 is provided in series between the pad 1, the ESD protection circuit 2 and the inverter 4, and a voltage of 3.3 V is applied to its gate. Next, the operation of this embodiment will be described with reference to FIGS.

The characteristics at each node in FIG. 1 are as shown in FIG. 2, FIG. 3 is an enlarged view of a portion indicated by section A in FIG. 2, and FIG. 4 is a portion indicated by section B in FIG. FIG. First, “L” = 0 input from the pad 1
An input signal of V, “H” = 5V is input to the level conversion circuit 3 via the ESD protection circuit 2.

In the level conversion circuit 3, the same potential as the operating voltage 3.3V of the inverter as an internal circuit is applied to the gate, and "L" = 0V and "H" =
As shown in the waveform of the node in FIG. 2, the voltage of 5 V is "L" = 0 V and "H" = 3.3 V by the level conversion circuit 3.
The voltage level is converted to a voltage level of −V _th ≒ 2.4 V, and the inverter 4 obtains prescribed voltage values of “L” = 0 V and “H” = 3.3 V.

As described above, in the present embodiment, both the potential difference between the gate and the node of the N-channel MOS transistor 5 forming the level conversion circuit 3 and the potential difference between the gate and the node are 3 V at the maximum. Therefore, a sufficient withstand voltage can be ensured even if the gate oxide film of the internal circuit is formed thinner with emphasis on high speed. FIG.
8 are diagrams showing a second embodiment of the semiconductor integrated circuit according to the present invention, FIG. 5 is a circuit diagram showing a main part configuration thereof, and FIG.
7 and 8 are enlarged views of a main part of FIG.

In FIG. 5, the same numbers as those of the first embodiment shown in FIG. 1 indicate the same parts. The N-channel MOS transistor 5 constituting the level conversion circuit 3 in this embodiment is provided in series between the pad 1, the ESD protection circuit 2 and the inverter 4, and has a gate connected to the drain and a back gate. The gate is connected to the source.

Next, the operation of this embodiment will be described with reference to FIGS. FIG. 6 shows the characteristics of each node to in FIG.
FIG. 7 is an enlarged view of a portion indicated by a section C in FIG. 6, and FIG. 8 is an enlarged view of a portion indicated by a section D in FIG. First, similarly to the above-described embodiment, the input signal of “L” = 0 V and “H” = 5 V input from the pad 1 is E.
The signal is input to the level conversion circuit 3 via the SD protection circuit 2.

In the level conversion circuit 3, the same potential as that at the input terminal side is applied to the gate, and the voltage of "L" = 0V and "H" = 5V at the node is as shown in the waveform of the node in FIG. In addition, “L” =
0.7V, “H” = 5V−V _th変 換 4.2V, which is converted into a voltage level.
A voltage value of “H” = 3.3 V is obtained.

As described above, in the present embodiment, the N-channel MOS transistor 5 forming the level conversion circuit 3 performs the same operation as the triode. Generally, in a MOS transistor in a triode operation, a channel and a depletion layer are formed on a silicon surface under a gate and an electric field is dispersed, so that a potential of 5 V is not directly applied between the gate and the channel.

That is, after the N-channel MOS transistor 5 is turned on, the potential of the node rises, and the potential difference between the node and the gate decreases. 9 to 12 are views showing a third embodiment of the semiconductor integrated circuit according to the present invention, FIG. 9 is a circuit diagram showing a main part configuration, FIG. 10 is a view showing characteristics at each node in FIG. , 12 are enlarged views of main parts of FIG.

In FIG. 9, the same reference numerals as those of the second embodiment shown in FIG. 5 indicate the same parts. An N-channel MOS transistor 5 constituting the level conversion circuit 3 in this embodiment is provided in series between the pad 1, the ESD protection circuit 2 and the inverter 4, and has a gate connected to the drain via the resistor 8. And is connected to a low-potential power supply via a capacitor 9. That is, the configuration is such that the CR time constant circuit is added to the level conversion circuit 3 of the second embodiment. In this embodiment, the resistance value of the resistor 8 is 4 kΩ, and the capacitance value of the capacitor 9 is 0.2 pF.

Next, the operation of this embodiment will be described with reference to FIGS. The characteristics at each node to in FIG. 9 are as shown in FIG. 10, FIG. 11 is an enlarged view of a portion indicated by section E in FIG. 10, and FIG. 12 is an enlarged view of a portion indicated by section F in FIG. It is. First, similarly to the above-described embodiment, “L” = 0 V, “H” = 5 input from the pad 1
The V input signal is input to the level conversion circuit 3 via the ESD protection circuit 2.

In the level conversion circuit 3, the same potential as that at the input terminal side is applied to the gate with a predetermined time delay by a CR time constant circuit, and "L" = 0V and "H" =
The voltage of 5V is applied as shown in the waveform of the node in FIG.
“L” = 0V, “H” = 5V−
V _th ≒ 4.2 V
As a result, prescribed voltage values of “L” = 0 V and “H” = 3.3 V are obtained.

As described above, in the present embodiment, the second embodiment is used.
"L" can be set to 0 V as compared with
By changing the time constant in the R time constant circuit, an arbitrary output waveform can be obtained. Further, since the rising waveform of the node of the second embodiment shown in FIG. 13 is steeper than the rising of the node of the present embodiment shown in FIG. 14, a potential of 5 V is instantaneously applied to the gate, and destruction occurs. However, in this embodiment, the potential of 5 V is instantaneously applied to the gate by dulling the rising waveform of the node by the CR time constant circuit.

FIGS. 15 to 18 are diagrams showing a fourth embodiment of the semiconductor integrated circuit according to the present invention. FIG. 15 is a circuit diagram showing a main part configuration thereof, and FIG. 16 is a diagram showing characteristics at each node in FIG. 17 and 18 are enlarged views of a main part of FIG. In FIG. 15, the same numbers as those of the second embodiment shown in FIG. 5 indicate the same parts.

The level conversion circuit 3 in this embodiment is provided so as to be connected in series between the pad 1, the ESD protection circuit 2 and the inverter 4, and in the level conversion circuit 3, the gate is connected to the drain. N channel MOS transistor 5 having a back gate connected to the source
And a second M having a predetermined voltage of 3.3 V applied to the gate.
An N-channel MOS transistor 10 as an OS transistor is connected in parallel.

That is, the level conversion circuit 3 of this embodiment
Is a combination of Example 1 and Example 2 described above, whereby, as shown in FIGS.
The voltage characteristics at the time of the low level and the voltage characteristics at the time of the high level, which are advantages of the first and second embodiments, are improved. As described above, in the above-described embodiment, a circuit capable of inputting an input voltage higher than the withstand voltage of the gate oxide film can be obtained in the process of manufacturing a highly integrated and high-speed device, and the conventional interface voltage of 5 V It can be incorporated in an LSI employing a power supply.

In the above embodiment, the current mainstream 5 V
The case where a semiconductor integrated circuit that operates at a power supply voltage of 3.3 V is mixed in a semiconductor integrated circuit that operates at a power supply voltage of 3.3 V has been described.
When the power supply voltage becomes mainstream, the present invention can be applied to a case where a semiconductor integrated circuit having a withstand voltage of 3 V or less is mixed, that is, a semiconductor integrated circuit operating at a predetermined power supply voltage has a withstand voltage of 3 V or less. This is applicable to a case where semiconductor integrated circuits are mixed.

[0033]

According to the present invention, even when a signal having a voltage level higher than the withstand voltage of the internal circuit is input to the input terminal by the MOS transistor provided between the input terminal and the internal circuit, the maximum voltage level can be reduced. It can be suppressed to a predetermined voltage value applied to the gate of the MOS transistor.

Therefore, even if the gate oxide film inside the semiconductor integrated circuit is formed thinner with emphasis on high-speed performance, it is possible to provide a semiconductor integrated circuit which can secure a sufficient withstand voltage and achieve high integration and high speed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part of a first embodiment.

FIG. 2 is a diagram showing characteristics at each node in FIG. 1;

FIG. 3 is an enlarged view of a section A in FIG. 2;

FIG. 4 is an enlarged view of a section B in FIG. 2;

FIG. 5 is a circuit diagram showing a configuration of a main part of a second embodiment.

FIG. 6 is a diagram illustrating characteristics at each node in FIG. 5;

FIG. 7 is an enlarged view of a section C in FIG. 6;

FIG. 8 is an enlarged view of a section D in FIG. 6;

FIG. 9 is a circuit diagram showing a main part configuration of a third embodiment.

FIG. 10 is a diagram showing characteristics at each node in FIG. 9;

FIG. 11 is an enlarged view of a section E in FIG. 10;

FIG. 12 is an enlarged view of a section F in FIG. 10;

FIG. 13 is a view showing a rising waveform in the second embodiment.

FIG. 14 is a view showing a rising waveform in the third embodiment.

FIG. 15 is a circuit diagram showing a configuration of a main part of a fourth embodiment.

FIG. 16 is a diagram showing characteristics at each node in FIG. 15;

FIG. 17 is an enlarged view of a section G in FIG. 16;

18 is an enlarged view of a section H in FIG.

[Explanation of symbols]

Reference Signs List 1 pad (input terminal) 2 ESD protection circuit (input protection circuit) 3 level conversion circuit 4 inverter (internal circuit) 5 N-channel MOS transistor 6 P-channel MOS transistor 7 N-channel MOS transistor 8 resistor 9 capacitor 10 N-channel MOS transistor ( Second MOS
Transistor)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-276249 (JP, A) JP-A-5-36919 (JP, A) JP-A-3-52 (JP, U) (58) Survey Field (Int.Cl. ⁷ , DB name) H01L 21/8234-21/3238 H01L 27/08-27/092

Claims (1)

(57) [Claims] An external signal is input to an internal circuit via an input terminal.
In semiconductor integrated circuits, MOS transistors
A drain is connected to the input terminal and the MOS transistor
The source of the MOS transistor is connected to the internal circuit.
A CR time constant circuit between the gate of the
A semiconductor integrated circuit characterized by being provided .