JP3195489B2 - External storage control device and bus switching control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage system in an information processing device, and more particularly to a bus switching method in an external storage control device.

[0002]

2. Description of the Related Art In recent years, a multiprocessor architecture has been actively employed for the purpose of high performance and high reliability of a storage device. In this case, by using a plurality of common buses, not only high expandability of the system function can be achieved, but also reliability can be improved. For example, FUJITSU 42, 1, pp12-20 (19
The file control device described in 91) divides the function exercised by the control device into a plurality of modules, arranges a microprocessor in each module, and realizes mutual communication through a common bus.

[0003]

In general, when a data signal and a control signal in a certain storage controller are transferred by only one common bus, control signals are exchanged by other modules while a large amount of data is transferred. Is delayed.
Conversely, if data transfer and control signal transfer are to be completely separated and performed on different bus systems, hardware that satisfies the required peak capacity of each performance is required. In general, the number of control signals issued relatively decreases when sequential access with a large amount of data transfer is performed, and conversely, when random access occurs in which commands occur frequently, the total transfer data amount often decreases. Even if one of the bus systems operates at the marginal performance, the other bus system becomes empty.

[0004] The technology described in the above-mentioned conventional literature multiplexes each module and a common bus as a measure against a failure, but does not solve the problem of the bus configuration due to such a difference in the purpose of using the bus.

The present invention has been made in view of the above problems, and has been developed in consideration of the above problems. An external storage control system capable of switching a bus in accordance with an instruction and dynamically changing a bus configuration most suitable for an access pattern of a host computer while the device is operating. An apparatus and a bus switching method are provided.

[0006]

In order to achieve the above-mentioned object, a bus switching control method according to the present invention comprises a first storage device for storing data, a second storage device for storing control information, In a storage system having three or more sets of buses for accessing the first and second storage devices, at least one set of the three or more sets of transfer buses is used for any of data transfer and control information transfer. Regardless of whether the storage system is running or not,
The at least one set of transfer buses is switched to one of the applications based on a switching instruction.

In this method, when the use of the at least one set of buses is switched during the operation of the storage system, use of the at least one set of buses is prohibited until processing for the switching is completed. It is desirable that the operation can be continued using another bus.

An external storage control device according to the present invention is connected to an external storage device, a cache memory for temporarily storing input / output data to / from the external storage device, and the second and third buses. A shared memory for storing control information including management information of data stored in the cache memory, channel adapter means for controlling data transfer between a host device and the cache memory using the content of the shared memory, A disk adapter for controlling the transfer of data between the external storage device and the cache memory using the contents of the shared memory; and a channel adapter for interconnecting the channel adapter, the disk adapter, and the cache memory. 1 bus, the channel adapter means, the disk adapter means, and the cache memo. And a second bus interconnecting the shared memory, and a third bus interconnecting the disk adapter, the channel adapter, and the shared memory, the channel adapter and the disk. The adapter is characterized in that the second bus is selectively used by switching between the cache memory access and the shared memory access.

In this device, the second bus is preferably used for cache memory access at the time of sequential access where the data transfer amount is larger than the control information transfer amount or at the time of heavy use. Conversely, the second bus is used for the shared memory. It is preferable to use for access at the time of random access where the control information transfer amount is larger than the data transfer amount or at the time of heavy use.

Each of the first to third buses is provided with an arbiter for arbitrating at the time of contention for a bus use request from a plurality of adapter means.

An instruction to switch the use of the second bus is issued from external input means by monitoring the operation information of the storage system, or the operation information is monitored by the storage system itself, and the obtained value is thresholded. This can be automatically performed by making a determination using a value determination or the like.

[0012] Even when the first or third bus cannot be used due to a failure or other causes, the second bus can operate in place of the bus.

[0013]

According to the present invention, in a storage system, a plurality of transfer buses can be selectively used for data transfer or control information transfer. For example, by monitoring and predicting the access pattern of the host computer,
It is possible to switch to a bus configuration with high data transfer capability when the amount of access data is large, and to a configuration with many control information transfer buses when performing multiplex operation in parallel. This is effective in improving the performance by maximizing the transfer capability of the bus.

That is, since the data access bus and the control bus are not completely separated from each other, at least one set of buses can be switched and used for both purposes. In this case, even when the load on the control bus is large and the amount of access data is small, the bus configuration can be effectively used by switching the bus configuration.

At the time of switching the bus configuration, the transfer method is changed so as to operate on the remaining buses without issuing a new transfer instruction for the corresponding bus, and hardware setting for switching is performed on the bus to be switched. Switch software from. By providing a transient degenerate state in the switching process in this way, it is not necessary to temporarily suspend the operation of the entire system during the bus switching operation. That is,
Without interrupting the access request from the host device,
Since the above-described bus switching can be realized, it can be used for a nonstop system.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a storage system to which the present invention is applied. An ESCON (Enterprise System Connection) cable connection system 1 connected to a host computer (not shown), a cache memory 2 which also serves as a buffer for temporarily storing input / output data, and between the host side and the cache memory 2, respectively. A plurality of CHAs (C) which are adapters with a processor (CPU) for controlling data transfer
Hanel Adapter) 3, a disk array 4, which is an external storage device, a plurality of DKAs (Disk Adapters) 5, each of which is an adapter with a processor for controlling data transfer between the cache memory 2 and the disk array 4, for managing the cache memory 2. The shared memory 6 stores control information including directory information and communication information between the processors of the respective CHAs 3 and the DKA 5, and a bus system 7 for accessing the cache memory 2 or the shared memory 6 from the respective CHAs 3 and the DKA 5. In this embodiment, the bus system 7 includes three buses that can operate independently.

FIG. 2 shows details of the main part of FIG. Here, the three systems of the bus system 7 are respectively referred to as a bus a, a bus b, and a bus c. Three buses a,
Both b and c are connected to each CHA3 and each DKA5. The bus a and the bus b are connected to the cache memory 2.
The bus b and the bus c are connected to (the control unit 61 of) the shared memory 6. Therefore, read / write access to the cache memory 2 is possible from any processor via the bus a or the bus b, and read / write to the shared memory 6 is possible via the bus b or the bus c. That is, the bus a is used exclusively for accessing the cache memory 2 and the bus c
Is used exclusively for accessing the shared memory 6, whereas
The bus b can be used by switching between both accesses. The functions of the CHA 3 are roughly divided into a host connection system control unit, a cache memory control unit, and a shared memory control unit, and the CPU 31 controls these controls. CHA
Reference numeral 3 has bus adapters BSAa and BSAb corresponding to buses a, b and c, respectively, and a shared memory port SMP. BSAa belongs to the cache memory control unit and SM
P belongs to the shared memory controller and BSAb belongs to both controllers. The functions of the DKA 5 are roughly divided into a disk connection system control unit, a cache memory control unit, and a shared memory control unit, and these controls are controlled by the CPU 51. DKA5
Also bus adapters B corresponding to buses a, b, and c, respectively.
It has SAa, BSAb, and SMP. BSAa belongs to the cache memory control unit, SMP belongs to the shared memory control unit, and BSAb belongs to both control units. Both BSAs and SMPs have a requester 75 that requests the right to use the corresponding bus.

Each system has a request line 72 (72a, 72b, 72c) and a grant ID line 73 (73a, 73b) in addition to the input / output bus lines 71 (71a, 71b, 71c) for transferring data and the like. , 73c) and hardware called bus arbiters 74 (74a, 74b, 74c) for arbitrating bus access rights. Each arbiter 74 is connected to requesters 75 in all CHAs 3 and DKAs 5 through two signal lines, receives a plurality of bus use right requests, and determines the priority order of bus use. Although the buses a, b, and c have respective arbiters 74a, 74b, and 74c, the arbiter 74a and the bus b can be collectively arbitrated and managed by the same arbiter 74a as one resource.

The shared memory 6 stores management directory information and the like of the cache memory 2 (a hierarchical table for searching cache segments and the state of each segment, etc.), and communication messages between processors of each CHA 3 and DKA 5 (inter-processor messages). Communication information for coordination, synchronization, etc.), switching statistical information, system configuration information (CHA, DKA mounting state, blockage state, etc., common information of system configuration, cache memory 2 capacity, disk array disk Number).

FIG. 6 shows each of CHA3 and DKA5,
That is, an internal configuration common to adapters with processors is shown. Adapters with each processor are BSAa, BSAb
And SMP are as described above. BSA
a is a buffer 77 for temporarily storing transfer data, I / F controllers 78 and 79 for controlling interfaces between the internal CPU and the bus, a requester 80 for issuing a bus use right request, and a mode switching mode to be described later. Is set. BSAb is
It has the same configuration as BSAa. The configuration of the SMP is the same, but the internal register 76 for mode switching is not included because it is unnecessary.

The BSA has the following mode setting function.

(1) Setting of Sequential Mode In this mode, the requester of BSAa or BSAb
Use only one of the requesters. However, a requester belonging to the same bus system as the enabled arbiter is always used. If the mode is set to the sequential mode, the bus system a and the bus system b are managed as one resource, and the right to use can be simultaneously secured to both bus systems by one request.

When setting the sequential mode,
Further, the following three bus modes can be used by setting software.

(I) 2-bus mode: Simultaneous transfer by bus a and bus b (128-bit transfer) (ii) System transfer by bus a only (64-bit transfer) such as when bus b fails, (iii) Bus a failure (2) Setting of transaction mode In this mode, both the BSAa requester and the BSAb requester are valid. When the bus b is switched to the shared memory access (32-bit transfer) for random access, the bus a and the bus b operate differently, so it is necessary to switch both BSAs to the transaction mode. In this case, the bus a and the bus b are managed as separate resources.

Next, SMP will be described. As described above, the SMP is hardware connected to the bus c in each adapter. The bus c is an independent resource that is always used for control information access (32-bit transfer), and does not use mode switching as in BSA.

Now, a specific procedure for performing an actual transfer in response to a bus request will be described below.

An adapter (CHA) trying to use a certain bus
3 or DKA 5) is the corresponding request line 72
To output the bus request to the corresponding bus arbiter 74. At this time, if a plurality of requests conflict, the arbiter 74 outputs the ID number of the adapter with the highest priority to the grant ID line 72 in accordance with a predetermined priority determination algorithm. The confirmed processor obtains the right to use the bus. When the right to use the bus is obtained, if the write is to the cache memory 2 or the shared memory 4, the address, command, and data are output in chronological order on the transfer bus, and the operation is performed by receiving the error phase (transfer completion status). finish. In the case of reading from the cache memory 2 or the shared memory 4, the address and the command are output, and the received read data and an error phase (transfer completion status) are received. The control unit 21 or 61 of the memory
If an error is detected in step (1), the information is transferred in an error phase.

Next, a data transfer processing procedure will be briefly described by taking as an example a case where stored data is read from the disk array 4 of the present embodiment and transferred to a host computer at a higher level.

One CH that has received a read instruction from a higher order
A3 first accesses the cache management information in the shared memory 6 to determine whether or not the data to be read exists in the cache memory 2. If the data is already loaded in the cache memory 2, the data is read. Is transferred to the upper level as it is. If the data is not in the cache memory 2, the DKA 5 is requested to read from the disk array 4 by inter-processor communication using the shared memory 6. Upon receiving this request, the DKA 5 calculates which part of the disk array 4 has the read data,
The data is transferred to the cache memory 2. that time,
After transferring data for each fixed block length, the shared memory 6
The upper management information area is accessed to indicate that the corresponding data block has been established on the cache memory 2. At the same time as the data transfer between the disk array 4 and the cache memory 2, the CHA 3 polls the shared memory 6 and transfers data from the cache memory 2 to the higher-level channel connection system 1 for the established data block.

As described above, reading / writing from / to the cache memory 2 or the shared memory 6 is performed a plurality of times during the processing for one command. Also shared memory 6
Is almost proportional to the number of I / O operations, whereas the access amount to the cache memory 2 is not necessarily proportional to the number of I / O operations since it corresponds to the actual transfer data amount. That is, in the case of sequential access in which long data is read and written collectively, the amount of data transfer to and from the cache memory 2 is large, and in the case of random access in which many short data reads and writes are issued in parallel, the amount of access to the shared memory 6 is reduced. Relatively high.

In this storage system, the bus a has a transfer width of 64 bits and is used only for accessing the cache memory 2. The bus c has a transfer width of 32 bits and is used only for accessing the shared memory 6. On the other hand, since the bus b has the same data transfer capacity (64 bits) as the bus a and is connected to both the cache memory 2 and the shared memory 6, the use is switched by changing the mode setting. Is possible. The mode is set by instructions from a maintenance service terminal personal computer (not shown) connected by a local area network LAN connected to the CPUs 31 and 35 in each adapter.

The switching procedure will be described below by taking as an example the case where the bus b set for accessing the cache memory 2 is changed to access the shared memory 6.

When the bus b is set for the cache memory 2, the read / write for the shared memory 6 is performed on the bus c
The read / write to the cache memory 2 is performed using both the bus a and the bus b at the same time. Since the address and command system of the present system is composed of 64 bits, the same address and command are duplicately transferred when simultaneous transfer is performed on the bus a and the bus b.
However, for data, the total of buses a and b
The transfer is performed in an 8-bit width, and the transfer time is shortened.

Referring to the flowchart of FIG.
First, one of the adapters (CHA3 or D1) receiving the bus mode switching instruction from the maintenance service personal computer.
First, the processor (switching processor) in the KA5) sets a degeneration instruction not using the bus b in a communication area (not shown) of the shared memory 6 (S1). Other adapters (slaves) periodically share the shared memory 6 even during operation.
(S21), and when a degeneration instruction for bus switching is received, a reception report is set in the shared memory 6 (S22), and subsequent accesses to the cache memory 2 are made using only the bus a. Do. The switching determination processor checks the communication area of the shared memory 6, and if all the reception reports from the other adapters can be confirmed (S2), performs the hardware setting for switching (S2).
3). In this hardware setting, the mode setting of the internal register 76 and the ON / OFF setting of an internal register (not shown) for setting the operation availability information of the arbiters 74a and 74b are performed. Next, an instruction to change the bus b for the shared memory 6 is set in the communication area (S4). The other adapter that has confirmed this instruction switches its own access mode (S23). In the switching of the access mode, the mode of the internal register 76 is set. The I / F control units 78 and 79 of the BSAa and BSAb in each adapter perform an operation according to the mode set in the internal register 76. As a result, the bus b can be used from the next access to the shared memory 6.

It should be noted that, contrary to the procedure of FIG.
Can be changed in the same procedure when changing from "for accessing shared memory 6" to "for accessing cache memory 2".

As shown in FIG. 5B, from the state of the bus b for using the bus b for cache access to the state of the cache memory, the bus b for temporarily prohibiting the use of the bus b is temporarily stopped.
The state shifts to the bus b shared memory state in which the bus b is used for shared memory access via the degenerate state. By this method, switching of the bus application can be realized without stopping the operation of the system.

The flow of information on each bus in the bus b cache memory mode will be described with reference to FIG.
In this mode, all the 64 bits of the bus b are used for accessing the cache memory.

First, in the case of read access, the adapter (CHA / DKA) issues a read address in the address phase (ADR) and then issues a read command in the command phase (CMD) on each bus. The address for cache memory access is
The same address is double-transferred simultaneously in the two systems of the bus a and the bus b. The same applies to commands. In response, each memory transfers data of 128-bit width to the adapter in both the bus a and the bus b in the data phase (DATA).
After the data transfer is completed, status information (transfer completed or error) is returned to the adapter in an error phase (ERR). Also in this error phase, the same status is double-transferred on both buses a and b.

Next, in the case of write access, the adapter issues a write address in each address bus in each bus, and then transfers write data in the data phase. In response, the status is returned from the memory to the adapter in the error phase. As in the case of the read access, data is transferred with a 128-bit width.

In FIG. 3, for convenience of explanation, the same kind of access to the bus c is performed at the same time as the buses a and b, but the memory access via the bus c is performed by the memory access by the buses a and b. And independent.

The flow of information on each bus in the bus b shared memory mode will be described with reference to FIG. In this mode, the three bus systems perform transfer independently. Unlike the case of FIG. 3, the bus b is used for shared memory access, and the 64-bit bus uses only half of the 32-bit bus. In read access, different addresses are transferred in parallel in the address phase to the shared memory in the bus b and the bus c. In the command phase, different addresses are transferred in parallel on the bus b and the bus c. Also in the data phase and the error phase, separate data and status are transferred on each bus. The same applies to write access.

For convenience of explanation, FIG.
b and c are the same command at the same time (read or write)
Is performed, the memory accesses of the buses a, b, and c are mutually independent.

As described above, when the access data from the host computer is large and the read / write to the cache memory is large, the bus b is switched to the cache memory. On the contrary, if it is determined that the parallel random access frequently occurs, the bus b is switched. By switching to shared memory, it is possible to maximize the overall bus marginal performance.

In the storage controller of this embodiment, the switching of the bus is also used as a countermeasure when a bus failure occurs. For example, if the bus a becomes inoperable due to a fault, the bus b is switched to the cache memory 2 so that the operation of the system can be continued even if the performance is slightly reduced. Similarly, bus b,
Even if one of the buses c fails, by switching the appropriate bus configuration, reading / writing to both the cache memory 2 and the shared memory 6 can be continued, and the operation until the maintenance staff rushes can be guaranteed. In a system having a plurality of buses having the same function as the bus b,
Even during the degenerate operation, if only three or more bus systems operate normally, the above switching method can be realized. In the above embodiment, only a part of the transfer bus is used for switching between data transfer and control information transfer. However, the switching can be performed for all buses.

Although the switching operation in the above embodiment is started by a maintenance staff command via the maintenance service personal computer, the operation status of the storage control device is monitored in the maintenance service personal computer and the threshold value is monitored. It is also conceivable to make a determination and issue the relevant instruction to the storage control device. For example, within a certain period of time, the data amount of the sequential access is detected based on the size of the transfer data, and if the data amount is larger than a predetermined amount, the sequential mode is set. If this logic is provided in the main body of the storage controller,
A storage control device that can automatically switch a bus suitable for a host access pattern is also conceivable.

[0047]

According to the present invention, it is possible to switch a specific bus for data access or control information access in response to an instruction from a maintenance service panel or a terminal personal computer therefor. As a result, the transfer bus owned by the system can be reconfigured into a desired system, the bus can be used efficiently, and the load on each bus can be averaged to increase the marginal performance. For example, in an operating environment with a high ratio of online processing, high response performance can be realized by giving priority to communication of control information, and in an operating environment with a high ratio of sequential processing, data transfer capability can be prioritized. Becomes

Further, a bus system suitable for the purpose of the system can be constructed without interrupting access processing from the host.

[Brief description of the drawings]

FIG. 1 is a block diagram of a storage control device to which the present invention is applied;

FIG. 2 is a block diagram showing a bus configuration of a main part of FIG. 1;

FIG. 3 is an explanatory diagram of an operation when a bus b is used for accessing a cache memory in the device of FIG. 1;

FIG. 4 is an explanatory diagram of an operation when the bus b is used for accessing a shared memory in the device of FIG. 1;

FIG. 5 is a flowchart showing a bus switching procedure in the apparatus shown in FIG.

FIG. 6 is a block diagram showing an internal configuration of the adapter of FIG. 1;

[Explanation of symbols]

1: host connection hardware, 2: cache memory,
3: CHA (channel adapter), 4: disk array, 5: DKA (disk adapter), 6: shared memory, 7: shared transfer bus, 75: requester, BSA: bus adapter, SMP: shared memory port

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hisashi Takeuchi 2880 Kozu, Kozuhara, Kanagawa Pref.Hitachi, Ltd.Storage Systems Division (72) Inventor Hisao Honma 2880 Kozu, Kozu, Odawara, Kanagawa Hitachi, Ltd.Storage Systems Business Within the department (72) The inventor, Nozomi Shimosako 2880 Kozu, Odawara-shi, Kanagawa Pref. Hitachi, Ltd. Storage Systems Division (56) References JP-A-3-176754 (JP, A) JP-A-2-310787 (JP, A) JP-A-2-76054 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12 / 02,12 / 08 G06F 13 / 12,13 / 16 G06F 13 / 36,13 / 38

Claims (3)

(57) [Claims] An external storage device and a key for temporarily storing input / output data to / from the external storage device.
Management of cache memory and at least data stored in the cache memory
A shared memory for storing control information including information, and a host device and the cache using the contents of the shared memory.
Channel adapter that controls the transfer of data to and from
And the external storage device using the contents of the shared memory.
A directory that controls the transfer of data to and from the cache memory.
Disk adapter, the channel adapter, and the disk adapter
Stage and a first interconnecting said cache memory
Bus, said channel adapter means, said disk adapter hand
Stage, the cache memory, and the shared memory.
A second bus connected to each other, the disk adapter means, and the channel adapter means.
Stage and a third bus interconnecting said shared memory
And the first bus is a read address of the cache memory.
Address and read data, or the cache memo
That can transfer the write address and write data of
And the second bus is used for accessing the cache memory.
When using, read address of the cache memory
And read data, or the cache memory
Transfer the write address and write data of
When used for memory access, the shared memory
Read address and read data, or
Transfer the write address and write data of the
And the third bus has a read address and a read address of the shared memory.
And read data, or write
Address and write data, and the input / output data transfer amount is larger than the control information transfer amount.
The second bus is connected to the cache memory.
For access, the amount of control information transfer entering-output data
If the transfer amount exceeds the transfer amount, the second bus is shared.
Switching control method, wherein the bus switching control method is used by switching for bus access . 2. When the use of the second bus is switched during operation of the storage system, use of the second bus is prohibited until processing for the switching is completed,
2. The bus switching control method according to claim 1, wherein the operation is continued using another bus. 3. A external storage device, the shared storing a cache memory for storing input and output data to the external storage device temporarily, even without least control information including management information of data stored in the cache memory A memory, channel adapter means for controlling the transfer of data between a host device and the cache memory using the contents of the shared memory, and the external storage device and the cache memory using the contents of the shared memory. A disk adapter unit for controlling data transfer between the disk adapter unit, the channel adapter unit, the disk adapter unit, and the cache memory ;
Cache memory read address and read data
Or the write address of the cache memory and
And a first bus for transferring write and write data, the channel adapter means, the disk adapter means, the cache memory, and the shared memory, which are used for accessing the cache memory.
The read address of the cache memory and
And read data or the cache memory
Address and write data, and
When used for reaccess, the shared memory
Address and read data, or the shared memo
Second for transferring the write address and write data of the
And bus, the disk adapter means, said channel adapter means, and connecting the shared memory mutually, the shared main
Memory read address and read data or previous
Transfer the write address and write data of the shared memory.
A third bus for transmitting the I / O data , wherein the channel adapter means and the disk adapter means are adapted to control the transfer of the input / output data by the control information transfer rate.
If it is larger, the second bus is used for the cache memory access, and the
The second bus
External storage controller, wherein said using shared memory switch to selectively for access.