JP3193802B2 - Method and apparatus for designing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for designing a semiconductor integrated circuit, and more particularly to a layout of a semiconductor integrated circuit using a gate array.

In recent years, the scale and speed of gate arrays have been increased. Along with this, for example, the number of internal cells that require a clock signal tends to increase dramatically, and the driving capability of the clock driver cannot keep up,
The problem of increased clock skew has arisen.

[0003]

2. Description of the Related Art In order to solve this problem, a clock distribution circuit using fixed arrangement wiring has been widely used.

As shown in FIG. 2, a clock distribution circuit 41
Are a main driver 42 for inputting a clock signal from outside the semiconductor chip 36, and a plurality of sub-drivers 43a to 43b connected to the main driver 42 and having equivalent outputs.
43j are fixedly defined. Each sub driver 4
Outputs of the sub-drivers 3a to 43j include fixed signal lines 44a to
44j are each fixedly defined.

[0005] Each of the sub-drivers 43a to 43j distributes clocks to clock-distributed logic cells, for example, load cells such as flip-flop cells, which are arranged in the coverage area. Therefore, each sub driver 4
If the clock distribution logic cells are allocated so that the load amounts of the sub-drivers 3a to 43j are balanced,
The clock skew of the clock distribution logic cell assigned to 43j can be reduced.

In designing a semiconductor integrated circuit, a logical design is first performed based on specifications to create logical design data having a hierarchical structure. In this case, for example, as shown in FIG. 12, the chip of the first hierarchy is composed of the functional blocks A to D of the second hierarchy.
Is defined by The function blocks A to D are defined by the function blocks EG, H, I, J, and K of the third hierarchy. Less than,
Each of the functional blocks EK is sequentially defined by each lower functional block, and the lowest hierarchical level is defined by a basic cell such as AND or OR.

Thereafter, a floor plan is made using a design apparatus (floor planner) based on the logical design data, and as shown in FIG. The blocks are divided into a plurality of arrangement areas 37 to 40 by CL1 to CL3, and the respective functional blocks A to D are assigned to the respective arrangement areas 37 to 40.

[0008]

However, the conventional floor planner does not consider the clock distribution circuit 41 shown in FIG. Therefore, in order to perform floorplanning of the logic design data using the gate array in which the clock distribution circuit 41 shown in FIG. 2 is defined, the designer must calculate the clock skew on his own, which is very troublesome. Was. In addition, when the calculated clock skew is equal to or larger than the allowable value, the designer must re-estimate the clock skew after redoing the floor plan, which causes a problem that the work efficiency is reduced. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to reduce the time and effort required for a designer to estimate a signal delay time or a signal delay time difference, thereby improving a work efficiency. An object of the present invention is to provide a method and an apparatus for designing an integrated circuit.

Another object of the present invention is to provide a method and an apparatus for designing a semiconductor integrated circuit, which can reduce the signal delay time difference in the whole semiconductor chip and can further improve the work efficiency.

[0011]

According to a first aspect of the present invention, a plurality of drive circuits for outputting the same type of signal are arranged at predetermined positions on a semiconductor chip, and the output of each drive circuit is Displays on a display a semiconductor chip on which a fixed signal line indicating a range of responsibility on the semiconductor chip of each drive circuit is respectively displayed on a display device, and corresponding to each functional block constituting the integrated circuit, the semiconductor chip is externally provided. In a semiconductor integrated circuit design method in which a plurality of arrangement regions are divided by a cut line generated by an operation and each functional block is assigned to each arrangement region, each arrangement region is connected to a fixed signal line of each drive circuit. The signal delay time or the signal delay time difference between the load cells is calculated. The calculated signal delay time or signal delay time difference is displayed on the display corresponding to each fixed signal line in each arrangement region.

In the second invention, the calculated signal delay time or signal delay time difference is displayed near each fixed signal line in each arrangement area. The third invention is configured to highlight the largest signal delay time or signal delay time difference.

According to a fourth aspect of the present invention, a cut line to be moved and a moving amount of the cut line among the cut lines dividing each arrangement region are calculated so that a signal delay time difference in the entire semiconductor chip is reduced, and based on the calculation result. To move the cut line.

According to a fifth aspect of the present invention, a cut line to be moved for an arrangement area where the signal delay time or the signal delay time difference is the largest or the arrangement area where the signal delay time is the smallest is calculated.

According to a sixth aspect of the present invention, a plurality of drive circuits for outputting the same type of signal are arranged at predetermined positions on a semiconductor chip, and the output of each drive circuit indicates the range of each drive circuit on the semiconductor chip. The semiconductor chips on which the fixed signal lines are respectively wired are displayed on a display device, and the semiconductor chips corresponding to each functional block constituting the integrated circuit are arranged in a plurality of arrangement areas by cut lines generated by an external operation. In a semiconductor integrated circuit design device which divides and assigns each functional block to each placement area, calculates a signal delay time or a signal delay time difference due to a load cell connected to a fixed signal line of each drive circuit in each placement area. And a signal delay time or a signal delay time difference calculated by the delay calculation unit corresponding to each fixed signal line in each arrangement area. Constructed by a display control unit for displaying on the vessel.

In a seventh aspect, the display control section displays the signal delay time or the signal delay time difference near each fixed signal line in each arrangement region. In an eighth aspect, the display control section highlights the largest signal delay time or signal delay time difference.

According to a ninth aspect of the present invention, a cut line to be moved and an amount of the cut line to be moved among cut lines dividing each arrangement region so that a signal delay time difference in the entire semiconductor chip is reduced based on a calculation result of the delay calculating unit. , And the display control unit moves and displays the cut line corresponding to the calculation result by the cut line moving unit.

In a tenth aspect, the cut line moving section calculates a cut line to be moved for an arrangement area where the signal delay time or the signal delay time difference is the largest or an arrangement area where the signal delay time difference is the smallest, and the movement amount thereof.

[0019]

Therefore, according to the first and sixth aspects of the present invention, when each functional block constituting the integrated circuit is allocated to each layout area, the load cells connected to the fixed signal lines of each drive circuit in each layout area. A signal delay time or a signal delay time difference is calculated. The calculated signal delay time or signal delay time difference is displayed on the display corresponding to each fixed signal line in each arrangement area. Therefore, the designer does not need to calculate the signal delay time or the signal delay time difference, and the work efficiency is improved. Further, the designer can re-designate each arrangement area based on the displayed signal delay time or signal delay time difference so as to approach a desired time difference.

According to the second and seventh aspects of the present invention, the signal delay time or the signal delay time difference is displayed near each fixed signal line in each arrangement region, so that the designer can reduce the signal delay time of each fixed signal line. Alternatively, the signal delay time difference can be recognized at a glance.

According to the third and eighth aspects of the present invention, the largest signal delay time or signal delay time difference is highlighted, so that the designer can easily determine whether or not it is within the allowable value.

Further, according to the fourth, fifth, ninth, and tenth aspects of the present invention, the difference in signal delay time in the entire semiconductor chip is easily reduced, and the working efficiency is further improved.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a design apparatus 1 of the present embodiment. The design apparatus 1 includes an apparatus main body 2, a disk system 9,
A display device 10 including a CRT, a keyboard 11, a mouse 12, and the like are provided. The apparatus main body 2 includes a file access unit 3, a semiconductor memory 4, a display control unit 5, a data input unit 6, a delay calculation unit 7, a cut line moving unit 8, and the like.

The disk system 9 is connected to the file access unit 3. The disk system 9 stores pattern data and arrangement data for displaying the semiconductor chip 36 and the clock distribution circuit 41 as shown in FIG. The clock distribution circuit 41 includes the main driver 4
2. Consists of sub-drivers 43a to 43j as drive circuits and fixed signal lines 44a to 44j. The main driver 42 inputs a clock signal from outside the chip 36.
Each of the sub-drivers 43a to 43j is connected to the main driver 42 and has an equivalent output. Each of the fixed signal lines 44a to 44j is connected to the output of each of the sub-drivers 43a to 43j. Each fixed signal line 44a-4
Reference numeral 4j designates the range of each sub-driver on the semiconductor chip 36. Each fixed signal line 44a to 44j has a flip-flop (hereinafter, referred to as a load cell) as shown in FIG.
FF) cell 50 is connected.

The disk system 9 stores logical design data having a hierarchical structure as shown in FIG. The data of each of the functional blocks A to K includes data such as the type and the number of the logic cells constituting the functional blocks A to D, the type of the FF cell included in each of the functional blocks A to K,
Data such as the load capacity for each number and type is stored.

The file access unit 3 is provided from the disk system 9 to the semiconductor chip 36 and the clock distribution circuit 4.
1. The data of each of the functional blocks A to K is read, and the read data is stored in the semiconductor memory 4. Further, the file access unit 3 can store data of the semiconductor memory 4 in the disk system 9.

A display 10 is connected to the display controller 5. The display control unit 5 reads the pattern data and the arrangement data of the semiconductor chip 36 from the semiconductor memory 4. The display controller 5 displays the semiconductor chip 36 on the display 10 based on the read pattern data and arrangement data as shown in FIG.

The display controller 5 reads the pattern data and the arrangement data of the clock distribution circuit 41 from the semiconductor memory 4. Based on the read pattern data and arrangement data, the display control unit 5 includes a clock distribution circuit including a main driver 42, sub-drivers 43a to 43j, and fixed signal lines 44a to 43j on a semiconductor chip 36 as shown in FIG. 41 is displayed.

A keyboard 11 and a mouse 12 are connected to the data input unit 6. Based on the operation of the keyboard 11 or the mouse 12, it is possible to select a floor plan process as shown in FIG. 3 or a cut line moving process as shown in FIGS. When the keyboard 11 or the mouse 12 is operated, the data input unit 6 outputs a signal based on the operation to the display control unit 5 and the delay calculation unit 6.

In the floor plan, for example, the keyboard 1
1, the coordinate values of the cut lines CL1 to CL3 are input. Then, the display control unit 5 sets the cut lines CL1 to CL
The data for displaying 3 is created. Display control unit 5
Generates cut lines CL1 to CL3 indicated by broken lines on the semiconductor chip 36 displayed on the display 10 based on the data as shown in FIG. To divide. Thereafter, for example, functional blocks A to D are respectively selected for the arrangement areas 37 to 40 based on the operation of the keyboard 11. Then, the display control unit 5 sets each placement area 37 as shown in FIG.
The function blocks A to D are arranged for.

Each of the arrangement areas 37 to 4 in the floor plan
Functional blocks A to D are arranged for 0. Then
The delay calculation unit 7 converts the clock distribution circuit 4
1 and data such as the type and number of FF cells included in each of the functional blocks A to D, and the load capacity for each type.

The delay calculating section 7 determines whether each of the fixed signal lines 44a to 44a in each of the arrangement areas 37 to 40 based on the read data.
The total load capacity connected to 44j is calculated.
The delay calculator 7 calculates the fixed signal lines 44a to 44j in the respective placement areas 37 to 40 based on the calculated total load capacities.
The delay (signal delay time) of the FF cell connected to is calculated.

The calculation of the delay will be described. It is assumed that the FF cell of one functional block is connected to the sub-driver. For example, suppose that 30 Lu (FF units) of FF cells 50 are connected in the placement area 37. These FF cells 50 are connected to the respective fixed signal lines 44 as shown in FIG.
Assume that the connections are averaged to a to 44f. Then
Each fixed signal line 44a-44f has a 5 Lu FF
The cell 50 is connected. The unit resistance and unit capacitance of the fixed signal line 44a are known. Therefore, as shown in FIG. 8, the line lengths a1 and b1 are calculated by a well-known RC path delay calculation.
Approximate calculation of the delay between driver cells between the sub-driver 43a and the FF cell 50 can be performed based on the load capacitance and the load. The delay between driver cells between each of the sub-drivers 43b to 43f and the FF cell 50 can be similarly calculated.

It is also assumed that FF cells of a plurality of different functional blocks are connected to the sub-driver. For example, as shown in FIG. 9, the FF cells 50 are connected to the fixed signal lines 44a to 44d in the placement areas 37 and 38, and the placement area 3
8, the FF cell 50 is connected to each of the fixed signal lines 44e and 44f.
Is connected. Therefore, as shown in FIG. 10, the delay between the driver cells between the sub-driver 43a and the FF cell 50 is determined by the line lengths a2, b2, c,
At 38, an approximate calculation can be performed based on the load capacitance connected to the fixed signal line 44a. The delay between driver cells between each of the sub-drivers 43b to 43d and the FF cell 50 can be calculated in the same manner. Each sub driver 4
The delay between the driver cells between 3e, 43f and the FF cell 50 can be calculated based on the line length (a2 + b2), c, and the load capacitance connected to the fixed signal lines 44e, 44f in the arrangement area 38. Note that, in the case of FIG.
In 8, the inter-driver cell delay between each of the sub-drivers 43a to 43d and the FF cell 50 is different from the inter-driver cell delay between each of the sub-drivers 43e and 43f and the FF cell 50.

The delay calculation section 7 is provided with a main driver 42
Then, the inter-driver delay between the sub-drivers 43a to 43j is calculated. The delay calculator 7 calculates the FF delay between the main driver 42 and each FF cell 50 by adding the delay between each driver and the delay between each driver cell.

The delay calculator 7 calculates each clock skew (signal delay time difference) by subtracting the minimum FF delay from each calculated FF delay, and outputs the calculation result to the display controller 5. Further, the delay calculating section 7 calculates the clock skew every time the cut line is moved.

Based on the calculation result of the delay calculation unit 7, the display control unit 5, for example, as shown in FIG.
Each clock skew is displayed on each fixed signal line at 0. The display control unit 5 highlights the maximum clock skew among the clock skews, for example, with high brightness or blinking. In FIG. 4, since the FF delay of the FF cell 50 of the fixed signal line 44e in the placement area 37 is minimized, the clock skew is 0 PS (picosecond), and the clock skew 215PS of the fixed signal line 44e in the placement area 40 is Highlighted as maximum clock skew.

After the floor plan, for example, the keyboard 11
Is selected based on the operation of (1). Then, the cut line moving unit 8 executes a process of moving the cut line displayed on the floor plan, and reduces the clock skew in the entire semiconductor chip 36.

The cut line moving process executed by the cut line moving section 8 will be described in detail with reference to FIG. First, an arrangement area of a hierarchy including the maximum clock skew is selected. (Step 20). Next, any one of the cut lines dividing the selected arrangement area is selected (step 21), and the cut line is moved (step 22).

Based on the movement of the cut line, the clock skew of each fixed signal line in the placement area has been recalculated by the delay calculating section 7, and it is determined whether or not the clock skew of the entire chip has decreased. Step 23).

If it is determined that the clock skew has decreased, it is determined whether or not the cell usage rate of the functional block disposed in the placement area satisfies a predetermined usage rate limit (step 24). This determination is because the size of the arrangement area changes when the cut line is moved, and the cell usage rate changes. If it is determined in step 24 that the usage rate limit is satisfied, the cut line is changed to that position (step 25).

Next, it is determined whether or not the movement of the cut line has been completed (step 26). If the movement has not been completed, the steps after step 22 are repeatedly executed. If it is determined in step 23 that the clock skew has not decreased, or if it is determined in step 24 that the usage rate limit has not been satisfied, the steps after step 22 are repeatedly performed.

If it is determined in step 26 that the movement of the cut line has been completed, whether or not the selection of the cut line has been completed is determined.
That is, it is determined whether there is an unprocessed cut line (step 27). If it is determined in step 27 that there is an unprocessed cut line, the processes in and after step 21 are repeatedly executed.

If it is determined in step 27 that the selection of the cut line has been completed, the arrangement area of the hierarchy including the minimum clock skew is selected. (Step 28). Next, one of the cut lines dividing the selected arrangement area is selected (step 29),
The cut line is moved (Step 30).

The clock skew of each fixed signal line in the entire chip is recalculated by the delay calculating section 7 based on the movement of the cut line, and it is determined whether or not the clock skew in the entire chip has been reduced (step). 3
1).

If it is determined that the clock skew has decreased, it is determined whether or not the cell usage rate of the functional block disposed in the placement area satisfies a predetermined usage rate limit (step 32). If it is determined in step 32 that the usage rate limit is satisfied, the cut line is changed to that position (step 33).

Next, it is determined whether or not the movement of the cut line has been completed (step 34). If the movement has not been completed, the steps after step 30 are repeatedly executed. If it is determined in step 31 that the clock skew has not decreased, or if it is determined in step 32 that the usage rate limit has not been satisfied, steps after step 30 are repeatedly performed.

When it is determined in step 34 that the movement of the cut line has been completed, whether or not the selection of the cut line has been completed is determined.
That is, it is determined whether there is an unprocessed cut line (step 35). If it is determined in step 35 that there is an unprocessed cut line, the processes in and after step 29 are repeatedly executed.

If it is determined in step 35 that the selection of the cut line has been completed, the processing is terminated. Accordingly, in the cut line moving process, the arrangement area 40 shown in FIG.
Is selected as the placement area including the maximum clock skew. The cut line CL1 in the arrangement area 40 is selected, and is moved right and left in FIG. In this case, clock skew can be reduced only slightly. Next, the cut line CL
3 is selected and moved up and down in FIG. In this case, as shown in FIG. 6, the cut line CL is within a range that satisfies the usage rate limit of the functional blocks arranged in the arrangement area 38.
By moving 3 upward, clock skew in the entire chip can be reduced.

In the process of moving the cut line,
The placement area 37 shown in FIG. 4 is selected as the placement area including the minimum clock skew. The cut line CL1 in the arrangement area 37 is selected and moved left and right in FIG.
In this case, clock skew can be reduced only slightly.
Next, the cut line CL2 is selected and moved up and down in FIG. In this case, as shown in FIG. 6, the clock skew in the entire chip can be reduced by moving the cut line CL2 upward within a range that satisfies the usage rate limit of the functional blocks arranged in the arrangement area 37. .

As described above, in this embodiment, when the designer specifies a floor plan and allocates each functional block to each of the layout areas 37 to 40, each of the sub-drivers 43a to 43j in each of the layout areas 37 to 40 Each fixed signal line 44
Each clock skew by the FF cells connected to a to 44j is calculated. The calculated clock skews are displayed on the fixed signal lines 44a to 44j. Therefore, the designer does not need to calculate the clock skew.
Work efficiency can be improved.

Further, in this embodiment, by selecting the processing for moving the cut line, the cut line in the arrangement area including the maximum and minimum clock skews is moved, and the clock skew in the entire semiconductor chip 36 is easily reduced. be able to. Thereby, work efficiency can be further improved. If the processing of moving the cut line is not selected, the designer can re-designate the floor plan based on the displayed clock skew so as to approach the desired clock skew.

In this embodiment, each of the arrangement areas 37 to 40
, The clock skew is displayed on each of the fixed signal lines 44a to 44j.
The clock skew of 44j can be recognized at a glance.

Further, in this embodiment, the maximum clock skew among the clock skews is highlighted with high brightness or blinking, so that the designer can easily determine whether or not the clock skew is within the allowable value.

In this embodiment, the cut line of the arrangement area including the maximum clock skew is moved, and then the cut line of the arrangement area including the minimum clock skew is moved. However, the order may be changed.

In this embodiment, the cut line of the arrangement area including the maximum and minimum clock skews is moved. However, only the cut line of the arrangement area including the maximum or minimum clock skew may be moved. .

In this embodiment, the fixed signal lines 44a-44 in the respective placement areas 37-40 of the semiconductor chip 36 are also provided.
Clock skew is displayed on j. Alternatively, if each clock skew corresponds to each of the fixed signal lines 44a to 44j of each of the arrangement areas 37 to 40, the position is close to each of the fixed signal lines or the display 10 outside the semiconductor chip 36. It may be displayed at any position.

In this embodiment, each of the arrangement areas 37 to 40
Although the clock skew is displayed corresponding to each of the fixed signal lines 44a to 44j in the above, the delay may be displayed.

[0059]

As described in detail above, according to the present invention,
The work efficiency can be improved by eliminating the time and effort required for the designer to calculate the signal delay time or the signal delay time difference.

Further, according to the present invention, it is possible to reduce the signal delay time difference in the entire semiconductor chip and to further improve the work efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a design apparatus according to an embodiment.

FIG. 2 is an explanatory diagram of a clock distribution circuit displayed on a display.

FIG. 3 is an explanatory diagram showing a floor plan of a semiconductor chip.

FIG. 4 is an explanatory diagram showing a display of a clock skew.

FIG. 5 is an explanatory diagram showing movement of a cut line.

FIG. 6 is an explanatory diagram showing redisplay of clock skew after moving a cut line.

FIG. 7 is an explanatory diagram showing an example of connection of a flip-flop cell to a fixed signal line.

FIG. 8 is an explanatory diagram of delay calculation in FIG. 7;

FIG. 9 is an explanatory diagram showing an example of connection of a flip-flop cell to a fixed signal line.

FIG. 10 is an explanatory diagram of delay calculation in FIG. 9;

FIG. 11 is a flowchart showing the operation of one embodiment.

FIG. 12 is a structural diagram showing logical design data.

FIG. 13 is an explanatory diagram of a floor plan.

[Explanation of symbols]

 Reference Signs List 5 display control unit 7 delay calculation unit 8 cut line moving unit 10 display 36 semiconductor chip 37-40 placement area 43a-43j sub-driver 44a-44j as drive circuit fixed signal line A-D function block CL1-CL3 cut line

Continuation of the front page (56) References JP-A-3-114257 (JP, A) JP-A-5-47932 (JP, A) JP-A-1-93144 (JP, A) JP-A-4-151185 (JP) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 27/118 G06F 17/50

Claims (10)

(57) [Claims] A plurality of driving circuits (43a-43) for outputting the same type of signal to a predetermined position on a semiconductor chip (36).
j) is defined, and the semiconductor chip (3) of each drive circuit (43a to 43j) is output to the output of each drive circuit (43a to 43j).
6) Fixed signal lines (44a-44)
44j) displays the defined semiconductor chip (36) on the display (10), and the semiconductor chip (36) corresponding to each functional block (A to D) constituting the integrated circuit.
To the cut line (CL
1 to CL3), the functional blocks (A to D) are divided into a plurality of layout areas (37 to 40), and
40) The method for designing a semiconductor integrated circuit, wherein the load cells connected to the fixed signal lines (44a to 44j) of each of the drive circuits (43a to 43j) in each of the arrangement regions (37 to 40). A signal delay time or a signal delay time difference is calculated, and the calculated signal delay time or the signal delay time difference is calculated for each of the fixed signal lines (44a to 44a) in each of the arrangement regions (37 to 40).
44j) A method for designing a semiconductor integrated circuit, comprising displaying on the display unit (10) in accordance with 44j). 2. The fixed signal lines (44a to 44a) in each of the arrangement areas (37 to 40) according to claim 1, wherein the calculated signal delay time or the signal delay time difference is calculated.
44j) A method for designing a semiconductor integrated circuit, wherein the display is performed in the vicinity. 3. The method for designing a semiconductor integrated circuit according to claim 1, wherein the largest signal delay time or signal delay time difference is highlighted. 4. The cut line (CL1) according to any one of claims 1 to 3, which divides each of the arrangement regions (37 to 40) such that a difference in signal delay time across the semiconductor chip (36) is reduced. CL3) A method of designing a semiconductor integrated circuit, comprising calculating a cut line to be moved and a movement amount thereof, and moving the cut line based on the calculation result. 5. The design of a semiconductor integrated circuit according to claim 4, wherein a cut line to be moved in an arrangement area where the signal delay time or the signal delay time difference is largest or an arrangement area where the signal delay time difference is smallest is calculated. Method. 6. A plurality of driving circuits (43a-43) for outputting the same type of signal to a predetermined position on a semiconductor chip (36).
j) is defined, and the semiconductor chip (3) of each drive circuit (43a to 43j) is output to the output of each drive circuit (43a to 43j).
6) Fixed signal lines (44a-44)
44j) displays the defined semiconductor chip (36) on the display (10), and the semiconductor chip (36) corresponding to each functional block (A to D) constituting the integrated circuit.
To the cut line (CL
1 to CL3), the functional blocks (A to D) are divided into a plurality of layout areas (37 to 40), and
40) In the semiconductor integrated circuit design apparatus to be assigned to (40), a load cell connected to a fixed signal line (44a to 44j) of each of the drive circuits (43a to 43j) in each of the arrangement areas (37 to 40). A delay calculating unit (7) for calculating a signal delay time or a signal delay time difference, and a signal delay time or a signal delay time difference calculated by the delay calculating unit (7) being used for each fixed signal in each of the arrangement areas (37 to 40). An apparatus for designing a semiconductor integrated circuit, comprising: a display control unit (5) for displaying an image on the display (10) corresponding to the lines (44a to 44j). 7. The display control unit (5) according to claim 6, wherein the display control unit (5) displays the signal delay time or the signal delay time difference near each of the fixed signal lines (44a to 44j) in each of the arrangement areas (37 to 40). An apparatus for designing a semiconductor integrated circuit, comprising: 8. The semiconductor integrated circuit designing apparatus according to claim 6, wherein the display control section (5) highlights the largest signal delay time or signal delay time difference. 9. The arrangement area according to claim 6, wherein a signal delay time difference across the entire semiconductor chip is reduced based on a calculation result of the delay calculation section. The display control unit (5) includes a cut line moving unit (8) for calculating a cut line to be moved and an amount of the cut line to be moved among the cut lines (CL1 to CL3) dividing the (37 to 40). A design apparatus for a semiconductor integrated circuit, wherein a cut line corresponding to a calculation result by a section (8) is moved and displayed. 10. The cut line moving section (8) according to claim 9, wherein the cut line moving section (8) calculates a cut line to be moved for an arrangement area where the signal delay time or the signal delay time difference is the largest or an arrangement area where the signal delay time difference is the smallest. An apparatus for designing a semiconductor integrated circuit, comprising: