JP3192220B2 - Circuit module redundancy architecture - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer-scale integrated semiconductor device having a plurality of semiconductor circuit modules all integrated on an entire wafer and to the manufacture of a wafer. The present invention relates to an architecture and a method enabling economical realization of a wafer-scale integrated circuit with high performance.

More specifically, the present invention provides a new configurable interconnect architecture, (2) a new high-speed parallel on-wafer bus system, and (3) a simple probe. (4) a special coding method to establish a unique address for each circuit module, (5) a novel power switch, 6) The present invention relates to a wafer-scale integrated system technology having a unique algorithm for forming a circuit of a whole wafer or a part of a wafer.

[0003]

2. Description of the Related Art In the manufacture of integrated circuits, a plurality of identical circuits such as memory cells are simultaneously manufactured on a wafer. The wafer is then split into multiple dies or chips along scribe lines, which are separately tested and packaged. Typically, yield from a given wafer is less than 100%. This is because many of these chips are discarded. Wafer surface area is not used economically because significant area is required for scribe lines and bonding pads. The costs associated with packaging individual chips represent a significant portion of the total cost of a termination product, and the "footprint" of a packaged chip is much larger than the chip itself. In addition, as the level of integration increases, manufacturing larger chips results in lower yields for the same defect density. In the prior art, many attempts have been made to use useful or operable circuitry on a wafer without physically separating the chips and bypassing the inoperative circuitry. For example,
N. MacDonald et al. "200M
b Wafer Memory (200Mb Wafer Memory)
y) ", IEEE 1989 ISSCC Technical
Digest, pp. References 240-241; J.
Cabillet al. "Wafer-scale integration (Wafer-scale Integration)"
n), "Microelectronics Manufacturing Technology, pp. 55-59, 1991 5
Moon, U.S. Pat. No. 4,007,452; E. FIG.
Hoff, Jr. , Title of invention "Wafer Scale Integrated System (Wafer Scale Integra)
ation System) ", US Patent No. 4,033.
8,648, Inventor G. D. Chesley, entitled "Self-Configurable Circuit Construct for Achieving Wafer-Scale Integration (Self-Configura)
ble Circuit Structure for
Achieving Wafer Scale In
reference).
Other multi-chip module approaches that can approximate the high circuit density and high speed performance of true wafer-scale integration are also known. For example, U.S. Pat.
No. 6,501, title of invention "Wafer Scale Integration (W
afer Scale Integration) ",
U.S. Patent Nos. 4,884,122 and 4,937,2
No. 03, entitled "Method and Configuration for Testing Integrated Circuit Chips and Electronic Circuits Using Removable Overlay Layers (Method and Configurator)"
ation for Testing Electro
nic Circuits and Integrat
ed Circuit Chips Using a
RemovableOverlay Layer) ",
U.S. Pat. No. 4,907,062 entitled "Semiconductor Wafer Scale Integrated Device (Semicon) Consisting of Interconnected Multichips with Integrated Circuit Chips
ductor Wafer-Scale Integra
added Device Committed of I
nterconnected Multiple Ch
ips Each Having an Integr
ation Circuit Chip). However, these approaches do not address yield and cost issues and are very expensive.

Generally, by using one or more optional connections, operable circuits or devices on a wafer are electrically isolated from inoperable devices. These optional connections can be made using masks, fuses or fusible links. See, for example, U.S. Pat. Nos. 3,835,530 and 3,810,301 in this regard. Special serial identification buses and circuits have been developed to address and operate modules operable with relative connection methods. This approach, like most other conventional approaches, assumes that the bus itself and its associated incremented circuits are defect-free. However, in practice, if the bus extends through the entire wafer, there is considerable probability that there will be at least one defect that renders the entire wafer useless. Similarly, defects in the power distribution bus, either in the form of an open circuit or a short circuit, render the entire wafer useless or render a significant portion of it useless. For example, H. Stopper, "Wafer-Scale Integration (Wafer-Scale Integration)"
n)], pp. 354-364, Electronic Materials Handbook, ASM 1989. To minimize defects and their impact on the bus, one recent approach (Ma
cDonald) relies on minimizing the number of wires in the bus and routes the bus in a spiral serial fashion through the wafer. This has the advantage of confining the effects of the defect to the bus itself. However, its serial nature has severely limited performance. This is because data from any module must propagate through the spiral path in order to reach the outside.

[0005]

According to the present invention, a plurality of circuit modules are formed on a wafer, grouped into a plurality of blocks, and arranged in a rectangular grid. An interconnect network with built-in redundancy and with signal and power lines surrounds each block. Each segment and each module of the interconnect network is tested, and then the fault free segments of the interconnect network are integrally connected to available circuit modules by fusible links.

Accordingly, the present invention provides a wafer scale integration device having the following features.

(1) It provides a highly redundant, configurable and segmented interconnection network that supports very high yield and high speed parallel bus architectures.

(2) To provide a configurable or form-identifiable segmented power supply network that minimizes yield loss due to power supply line defects.

(3) To provide a special power switch circuit present in a circuit module for separating defective modules with low power dissipation.

(4) Provides a high-speed parallel bus architecture with special transceiver and repeater circuits.

(5) Provides a special coding sequence to establish a unique address for the circuit module.

(6) A special layout configuration is provided which enables simple probe operation and configuration (specification of form).

(7) A special configuration (form specification) algorithm capable of specifying a form in either the whole wafer or a part of the wafer is provided.

The combination of these features makes it economical to provide high performance, low power, highly integrated semiconductor devices on either a full or partial monolithic wafer having one or more types of circuit modules. It is possible to realize it.

In one embodiment of the present invention, there is a segmented interconnect and power distribution network, which is highly fault tolerant and, once the configuration is specified, the wafer Or establish a high-speed parallel bus system that connects to all operable circuit modules on some of them. Each circuit module includes a memory circuit (DRAM, SRAM, EPROM, EEPROM)
M, flash EPROM or other type of memory), logic circuit (microprocessor, microcontroller, floating point processor, DSP processor or other coprocessor, program logic, field programmable gate array, glue logic or other type of logic) or It is possible to combine a memory and a logic circuit.

In the case of wafer scale or partial wafer or large die size integrated circuits, defect management or redundancy circuits as described above are among the more important parameters to ensure reasonable and high yield and low cost. One.
The techniques described above provide redundant architectures and techniques for very large chips with efficient defect management that overcome the limitations of conventional redundant circuits.

One embodiment of the present redundancy architecture is particularly suitable for medium die size integrated circuits (chip sizes of 2-3 square inches or less). In this embodiment, the chip has one or more circuit blocks, and each circuit block has a plurality of circuit modules. At least one redundant circuit module is provided in one of the circuit blocks, which can be used to replace another circuit module in one of the circuit blocks. The redundant circuit module and the circuit module can be replaced with a redundant circuit module, wherein each redundant circuit module has an identification circuit, wherein each of these circuit modules is The unique identification code (which is part of the address) can be selected by matching the address signal sent to each of these circuit modules.

This method of operating a memory-mapped type address
A separate serial identification bus (U.S. Pat. No. 4,007,404) is different from conventional fully decoded memory configurations that do not allow for efficient circuit module replacement, and creates area and performance penalties. No. 452). The redundant circuit module includes a fuse, an anti-fuse, an EPROM, an E
It has a programmable identification code that can be implemented using an EPROM, flash EPROM cell or other programmable switch. Circuit modules that can be replaced by the redundant circuit module have preset, decoded, or programmable identification codes that further indicate that certain circuit modules are defective. And has a disable switch that can be activated if it is to be replaced. The disable switch includes a fuse, an anti-fuse, an EPROM, an EEPROM, a flash EPROM.
It can be implemented using cells or other programmable switches. The redundant circuit modules and these other circuit modules can be identical for a more regular configuration. Also, it is possible to distribute the address, data and control signals using either conventional methods or a high speed bus. This embodiment provides significantly improved chip yield compared to conventional redundancy architectures which only provide redundancy replacement capability for defects in the memory array area which is typically only about 50% of the chip area. , It is possible to provide efficient circuit module level replacement redundancy.

[0019]

FIG. 1 shows a plurality of circuit chip modules 16-1, 16-2,. . . ,
16-i,. . . , 16-k and transceiver / repeater modules 18-1, 1 each indicated as "T"
8-2,. . . , 18-i,. . . , 18-1 on the surface thereof. FIG. Modules 16-1, 16-2,. . . , 16-
k and 18-1,. . . , 18-1 is provided with an interconnect network 22 having a power and signal bus (not shown). Each circuit chip module 16
-I are associated module / bus interface sections 24-1, 24-, each designated as "I" and capable of being connected to the interconnect network 22.
2,. . . , 24-i,. . . , 24-n. Interface section 24-i may further include a power switch circuit. Transceiver / repeater module 18-i (shown as M) has circuitry that is part of a parallel bus architecture. Although each is shown in FIG. 1 as being identical and of the same dimensions, the circuit chip modules 16-i, indicated as "M", may be one or more types of modules of different dimensions (e.g. , DRAM module, SRAM module, MPR module, or logic module).

The dimensions and locations of the transceiver / repeater module 18-i, shown as "T" in FIG. 1, are only shown schematically. Physically, each of the transceiver / repeater modules can be located in one cluster or distributed along or as part of the interconnect network. The interconnect network may extend partially through or around the circuit block.

However, in order to enable easy probing and configuration in testing, the module blocks 32-1 and 3-2
2-2,. . . , 32-i,. . . , 32-m (modules 16-1, 1 surrounded by the interconnection network 22).
6-2, 16-3, 16-4, 16-5, 18-1) in a layout structure having a regular grid pattern as shown in the main interconnection network 22. Is preferred. Each module block 32-i
Are 1 to 100 modules 16-1, 16-
2,. . . , 16-i,. . . , 18-1 and each wafer has several to hundreds of module blocks 32-1,. . . , 32-m. While all modules on the wafer 12 can be connected together to form a single device (a device for the entire wafer), the wafer 12 may further include a predetermined scribe line (not shown) and And / or split into small pieces along an interconnect bus (not shown), one or more whole or partial module blocks 32-
1,. . . , 32-m (hence, a partial device of the wafer). Although not shown in FIG. 1, the connection of the whole wafer or a part of the wafer from the device to the outside is made by bonding pads or pads in an interconnection network at the peripheral portion of the wafer, or wire bonding, TAB (tape automation bonding). Or, it can be accessed via pads in the transceiver / receiver module (T) using other wiring means.

Interconnect System FIG. 2a shows an enlarged portion of the wafer 12 of FIG. 1 with details of the segmented interconnect network 22. FIG. Each horizontal interconnect segment 22-H has a VCC line, a VSS line, and lines 22-1, 22-22, respectively.
-2,. . . , 22-i,. . . , 22-p. Similarly,
Each vertical interconnect segment 22-V also has a VC
C line, VSS line, and a plurality of signal segments 22V-1, 22V-2,. . . , 22V-
i,. . . , 22V-q. The signal segments 22-1,. . . , 22-P or 22V-
1,. . . , 22V-q is the sum of the number of signals required by the bus architecture and the number of additional redundant wires for better segment yield. It is possible to provide vertical and horizontal interconnect segments. Interconnect segments running in the same direction are connected by antifuses to lateral connection points 40-1, 40-.
2,. . . , 40-i,. . . , 40-r, and the antifuse is normally open but can be short circuited by a laser beam, electrical pulse, or other energy method.

Multi-interconnect segments are connected at an interconnect junction box 42, within which there is simply a set of lateral connection points 44-1, 44-2, along each of the horizontal and vertical directions. . . . , 44-
i,. . . , 44-s and 40-1, 40-
2,. . . , 40-i,. . . , 40-r. Between the horizontal and vertical segments, there are crossover connection points 46-1, 46- between signal segments.
2,. . . , 46-i,. . . , 46-t, which in one embodiment are also configured using antifuses. The crossover connection points 46-1,... Between the signal and power supply segments from the vertical interconnection point. . . , 46-t may be provided entirely or partially. This particular configuration of junction box 42 allows for a complete electrical test for defects (especially shorts) between any adjacent wiring segments, while providing efficient and high-yield interconnects. It is useful because it allows for electrical connection between segments while allowing connection routing and configuration identification. As shown in FIG. 2a, each module 16-i can be connected to an interconnect segment 22-p via a module interface box 48-i having a combination of hardwired connections and crossover connections. It is. The lower part of FIG. 2a shows the description of the symbols of the horizontal connection points and the crossover connection points.

FIG. 2b illustrates the interconnection segment 2 described above.
2 and junction boxes 42-1 and 42-
2,. . . , 42-4 are shown. In this example, four wires 22-1, 22 per segment 22S are used.
-2,. . . , 22-4 to form a signal bus consisting of two wires (A and B). For example, 22-
Defective wires such as 1 are labeled "X" and are connected (short-circuited) connection points 46-i, 46-i + 1.
Are indicated by black dots. It should be noted that the sequence and position of the bus signals (A and B) are irrelevant.
Because they are connected to the correct input / output pins of a circuit module (not shown) via the module interface box 48-i. In general, to effectively configure an interconnect segment, the number of redundant signal segments in the interconnect segment must be equal to the total number of defective segments in two adjacent interconnect segments-
It should be equal to or greater than the number of defective segments that happen to be arranged between the adjacent interconnect segments.

FIG. 2c illustrates interconnect segments 22V, 2V
2S and circuit modules 16-i, 16-i + 1, 16
14 shows more detailed layouts of −i + 3 and 16−i + 2. Three sets of probe pads are shown, ie:
Pads 50-1, 50-2,... For the circuit module (shown as A). . . , 50-i,. . . , 50
-U, pads 52-1, 52-2,... For horizontal interconnect segments (denoted by B). . . , 52-
i,. . . , 52-w, and pads 54-1 and 54- for vertical interconnect segments (denoted by C).
2,. . . , 54-i,. . . , 54-v. Partial interconnect junction boxes 42-i and module interface boxes 48-i are also shown.
Each signal segment 22V, 22S is connected to the probe pad 5
It is possible to directly access from 2-1 and 54-1 (pads marked with B or C). Power supply segments are not shown, but they can be similarly accessed from probe pads 50-1, 52-1, 54-1 and the like. This configuration is useful because it allows each wiring segment to test for a short circuit condition on all of its possible adjacent wire segments.

In a parallel bus architecture, any short circuit in the bus signal lines (the power supply is also a parallel bus system in nature) renders all devices non-functional, so the short circuit is extremely destructive. And their occurrence must be minimized. The highly regular arrangement of the probe pads, especially the pads 52-1, 52-w, and 54-1,. . . , 54-v (labeled B and C) allow easy access using conventional test probes or probe cards on conventional probe stations. It should be noted that pad groups A, B, C are shown in FIG. 2c in one column and three rows, but they are the number of pads required by the particular circuit implemented. Can be arranged to form one to three columns and / or one to three rows. For a typical test and configuration, the first probe card (not shown) includes the circuit modules 16-i, 16-i + 2, 1
6-i + 3 and transceiver / repeater module 16
Used to test i + 1, a second probe card (not shown) used to test all interconnect segments, and then the computer performs calculations and generates an interconnect map operable. Set up the connection and power supply network and all operable modules. The configuration of the selected junction (antifuse) is then programmed using a laser beam, electrical or other energy means.

FIG. 2d shows a variation of the lateral junction box of FIG. 2b, which comprises adjacent segments 22-1, 22-2,. . . , 22-p directly or at cross-connect points 47-1, 47-2,. . . , 47-x allows for lateral connections to segments at different locations. All segments in this horizontal junction box are
A connection can be made to a probe pad (not shown) to allow a complete test to be performed prior to configuration. In this case, the horizontal connection points 44-1, 44-2,. . . , 44-r are actually redundant and can be omitted (leaving an open circuit there).

The intersections 47-1, 47-2,. . . ,
47-x need not be completely provided, which allows for a simpler layout and / or ensures reduced parasitic capacitance. FIG. 2e shows one such embodiment, where intersections 47-1, 47-
2,. . . , 47-x are provided only in half. In fact, within each interconnect segment 22-S, the wire segments 22-1, 22-2,. . . , 22-p is
It is possible to divide into two or more groups, and therefore, within each group, in view of the balance between wiring flexibility and reduced parasitic capacitance,
It is possible to provide all, half or part. To allow for repeated configuration and further reduce the effects of undetected defects, additional fuses (which are normally connected but programmed to open by, for example, a laser beam) Can be provided in the signal segment and / or the power supply segment.

The two-dimensional segmented interconnect system described above is highly fault tolerant. Any short circuit defects can be avoided by using another redundant segment. If all wiring is inadequate or unavailable for use in a particular segment, that segment is separated with minimal yield loss without affecting the rest of the equipment. (Thus, only the modules attached to the segment are lost).
The interconnect system is defect tolerant, especially for open defects. This is because any interconnect segment can be reached from both ends. Power supply networks that are similarly arranged in a segmented manner are also highly fault tolerant.

FIG. 2f shows the arrangement or arrangement of test transistors for testing open defects in interconnect segments. As shown, the N-channel transistors 43-1, 43-2,. . . , 43-
k,. . . , 43-t are wires (wiring) 45-1, 4
5-2,. . . , 45-e,. . . , 45-s near the ends of the interconnect segments and their common gates are coupled to VSS. During the interconnect open defect test, the gate of the transistor is turned on, thereby connecting the ends of these wires.
Open defects can be detected and located by checking for discontinuities between pads of adjacent wires 45-1, 45-2. Similar configurations can be implemented using P-channel transistors or other active devices.

The power supply network shown in FIG. 2a juxtaposed with the signal segments can be placed away from the signal segments in an actual layout and in circuits with high power dissipation, It can be located on a metal layer or a plurality of layers.

Power Switch Circuit Additional power fault tolerance is achieved by isolating individual modules that have power line shorts. FIG.
a is a power switch 58 existing in each circuit module.
FIG. A VCC node 60 and a VSS node 62 connect to the associated power supply segment outside the module, while a VCCM node 64 and a VSSM node.
Node 66 is connected to the module's internal power supply. Nodes C1 and C2 are normally open (anti-fuse) and R1 and R2 are high value resistors, which bias the gates of N-channel transistor N1 and P-channel transistor P1, respectively, to turn on each transistor. Keep fully turned on. If there is a short circuit or a high leakage current in a particular module, the transistors N1 and P1
Acts as a current clamp, limits the current flowing in the module, and during configuration, the nodes C1 and C2 are programmed into a short circuit state to shut off the transistors N1 and P1 It is possible to bring the condition and to isolate the defective module. This circuit is different from the conventional circuit and is an improvement of the conventional circuit. In this regard,
U.S. Pat. No. 4,855,613; Yama
da and H .; Miyamoto, Title of Invention "Wafer Scale Integrated Semiconductor Device with Improved Chip Power Supply Connection Configuration (WaferScale Integrati)
on Semiconductor Device H
aving Improved Chip Power
-SupplyConnection Arrange
ment) ". Because the power switch circuit itself only dissipates power (R1 and R2) when it is disabled (i.e., nodes C1 and C2 are shorted). Through). In a typical wafer-scale integration, this circuit dissipates compared to conventional circuits because the majority of the modules are good and only a small portion of the modules are defective. The power is very small.

FIG. 3a shows a power switch circuit having both transistors N1 and P1, and uses two (VCC, VSS) or three (plus VBB substrate back bias not shown) power supplies. It is possible to isolate the power supply short circuit in the circuit. If only two power supplies (VCC, VSS) are used in the device, an N-channel transistor set (N
1, C1, R1) or a P-channel transistor set (P1, C2, R2) alone can be used to implement a simpler power switch. Further, the configuration of resistors R1 and R2 can be an active device (eg, a transistor) that connects to a load element or a simple resistor element.

For circuit modules consuming high supply currents, such as when the dimensions of transistors N1 and P1 are too large to be economical, a simpler direct connection method is shown in FIG. 3b. I have. in this case,
Nodes C3 and C4 each provide one or more parallel nodes 70-1, 70-, respectively, that provide a low series resistance when programmed.
2,. . . , 70-i,. . . , 70-y and 72-
1, 72-2,. . . , 72-i,. . . , 72-x. Note that if the defective module is not connected to it, the leakage current flowing through this power supply network will be very low. Two modules (VCC, VS
If only the power supply of S) is used, the connection point C3
Or only C4 is needed. Additional fuses (not shown), which are normally short-circuited and open when programmed, are provided in series with nodes C3 and / or C4 and, after connecting them, It is possible to subsequently remove the module from the power supply network. On the other hand, the connection points C3 and / or C4 can be realized using a programmable or writable fuse which is normally short-circuited.

A schematic diagram of the bus architecture and circuit hierarchy parallel bus system is shown in FIG. 4a. The bus is said to be "parallel." Because the data on the bus is not required to pass through one module 16-1 or one module group before being received by another module 16-i or module group, the transceiver 80-i
1,. . . , 80-i,. . . , 80-a (marked with T) and repeaters 82-1,. . . , 82-
i,. . . , 82-b (labeled R), all modules 16-1,. . . , 16-k can be broadcasted simultaneously and received simultaneously by the module. This feature is very useful for high-speed operation and differs from the conventional configuration. However, data transmission and reception on the bus can be performed in a parallel (data is transmitted on several wires at a time) or serial (data is transmitted in a sequential manner on a timing basis). ) Or a combination of both. The communication mode between the modules and between the module and the outside world can be a mode of broadcasting (broadcast), one-to-one, or one-to-one selected group. Three levels of bass hierarchy are shown, in which case BUS0
Communicates from the bus controller 86 to the outside world (marked with C), and BUS1
And transceivers 80-1,. . . , 80-a (marked with a T) and a repeater 82-a for buffering the signal for maximum performance.
1,. . . , 82-b (labeled R), and BUS2 is the transceiver 80-b.
1,. . . , 80-a and modules 16-1,. . . ,
16-k (marked with M). Each transceiver 80-2 drives a plurality of circuit modules 16-i + 1, 16-i + 1 and each controller 86 drives a plurality of transceivers and / or repeaters. The bus controller 86 can be located on the wafer or on a chip outside the wafer. Several wafer devices and / or some wafer devices can be connected in parallel at BUS0 or BUS1 to form larger systems or systems with special requirements (eg, very fast operation). .

On the other hand, several wafer devices and / or partial wafer devices can be connected in series in BUS1 to form a larger system, in which case the second device is connected to a controller. Instead, it is connected to the branch of BUS1 of the first device via a repeater (for example, 82-b shown in FIG. 4a).

For smaller systems or systems where speed is less of a concern, the repeater can be omitted. In general, BUS0 can have a variety of different widths, formats and protocols to communicate with external circuits, and BUS1 and BUS2 typically have the same number of wires and signal definitions. Can have different drive characteristics and voltage swings. In a simple wafer scale system, BUS1 and BUS2 can be the same, and the transceiver (T) is exactly the same, if a repeater (R) is present. In addition, both levels of the bass hierarchy (BUS1
And BUS2) are preferably implemented with the same segmented regular interconnect network as shown in FIGS. 2a-2c to provide maximum configuration flexibility.

FIG. 4B shows the electrical specifications for implementing a parallel bus. Both BUS1 and BUS2 are
The majority of the bus signals are shared, and CTL is used only by BUS1. CTL, RCK, WCR are unidirectional signals, and D0-D7 and PA are bidirectional signals. This configuration uses nine data signals, but any other number of data lines (eg, 1-6)
4) can be used. Two (three) unidirectional signals (RCR, WCK, CTL) are the main control and timing lines, which govern communication on the bus. The two main timing reference signals are RCK (receive clock) and WCR (write clock). WCK acts as a synchronization clock for data or commands generated from the controller and sent from the controller to the circuit module. RCK acts as a synchronous clock for data or commands generated from the active circuit module and sent from the circuit module to the controller.
This unique self-synchronous synchronous data transmission mode (also referred to as source-synchronous transfer mode) provides very high bandwidth data communication (500 MHZ in a wafer scale integrated environment).
z). This is because it minimizes the timing distortion between the data and the synchronization clock, and thus allows for the highest clock and data rates physically possible in a uniform wafer environment. RCK and WCK share one bidirectional line while maintaining the operation and benefits of a self-synchronous source-synchronous transfer mode in configurations where only one set of data transfers is allowed at a time. It is possible to realize.

FIG. 4e shows another embodiment of the signals on BUS1 and BUS2. In addition to bidirectional data lines,
One bidirectional clock line (CLK), one unidirectional control line (CTL), and two optional control lines (CT
L1: bidirectional, CTL2: single direction). This timing method also uses a minimum number of wires for the reference signal, while minimizing overhead in the interconnect system. Typically,
To minimize the yield loss from the interconnect network,
The bus width (the number of conductors) needs to be as low as possible, while from a performance standpoint, the wider the bus width, the greater the bus throughput. Thus, the choice of data width depends on the optimal balance between cost and performance.

Although the data wires in FIGS. 4b and 4e are all shown as bidirectional to minimize the number of wires, some of them may be single in either direction dedicated to the data transfer mode. It can be configured as one-way or configured to allow multi-port operation.

FIG. 4c shows a variation of the hierarchical bus architecture, in which transceiver 80-
1, 80-2,. . . , 80-a and the repeater (not shown) are the same, and buses BUS1 and BUS2 make no difference in connecting modules and / or transceivers. This configuration provides greater flexibility in interconnecting and morphing the wafer scale devices, while maintaining near optimal performance. FIG. 4d shows an example of interconnect routing on a wafer scale device 12 using the architecture shown in FIG. 4c. It should be noted that all good modules, for example 16-1, 16-2, are connected to the bus and that there are more than three transceivers between the module and the chip I / O port 90. 80-1, 80-2, and 80-3 do not exist. “X” indicates a defective module such as 16-i.

FIG. 4f shows a wafer scale (whole wafer, partial wafer, wafer scale) using the architecture shown in FIG. 4a.
5 illustrates another example of interconnect routing on a single or multiple lithography fields). Repeaters are indicated by R, transceivers are indicated by T, chip I / O ports are indicated by C, circuit modules are indicated by M and interfaces are indicated by I. It should be noted that the transceiver / repeater (TR) module circuit is distributed and part of the interconnect network, and each interface I, such as 81, for example, has two It is shared by the circuit modules 83 and 85.

FIG. 5a shows a schematic diagram of the module interface circuit. In this example, a memory module is shown. A memory core 94 having an associated row 96 and column circuit 98 is connected via a module interface 100 to an interconnect network (BUS2). The parallel-to-serial and serial-to-parallel conversion circuit blocks 102 allow the reception and transmission of data, commands, and addresses that may be wider than the data bus width (9 in the example of FIG. 4b). The register file 106 is provided in an interface that generates and tracks byte counts, row, column addresses, and base addresses for memory accesses. The control circuit 108 decodes and executes commands, controls and generates the data stream and input / output buffers 110, along with other tasks such as, for example, bus protocols and memory refreshes. Since all circuit modules are connected to a parallel bus, a unique identification (ID) is required by each module for proper data communication on the bus. Two ID circuit blocks are shown in FIG. One ID
Block 114 sets up the initial communication network,
Programmable or writable fuses (or antifuses, E fuses) for system configuration, diagnostics and (optional) normal operation
PROM cell, EEPROM cell, Flash EPRO
M cells or other programmable switches). The second (optional) ID circuit 118 is
It sets up software programmable ID codes for subsequent memory accesses and is useful in memory space mapping, self-test and self-reconfiguration.

This ID circuit is also a key element in implementing the highly efficient redundancy architecture and circuits described herein. FIG. 5b shows a schematic diagram of a generalized redundant circuit module 16-i that can be used to replace another defective circuit module. The redundant circuit module 16-i has a programmable ID circuit 115-a and an (optional) software programmable ID circuit 115-b, wherein the modules 16-i have their unique ID codes. (Which is part of the address) can be selected by matching the address signal sent to each of these circuit modules 16-i. It should be noted that this memory-mapped addressing method uses the conventional fully-decoded memory redundancy method (which provides redundant rows and columns separately and allows for efficient circuit module replacement). Not something)
And different from conventional methods using a separate serial ID bus (as in U.S. Pat. No. 4,007,452) at the expense of area and performance.
Circuit modules that can be replaced with redundant circuit modules have a preset, decoded or programmable ID code, wherein the module is further characterized in that certain circuit modules are defective and replaceable. It has a disable switch 116 that can be activated when it is to be done. Programmable I
The D circuits 115-a and 115-b and the disable switch 116 include a fuse, an anti-fuse, and an EPRO.
It can be implemented using M, EEPROM, flash EPROM cells or other programmable switches. The redundant circuit modules and their replaceable circuit modules can be identical for a more regular configuration. Also, the address, data, and control signals on buses 1-17 can be distributed using any of the conventional methods or the high speed bus described herein. This embodiment employs conventional redundancy as used in memory devices that only provide redundancy replacement capability for defects in the memory array area that is typically only about 50% of the memory chip area. It allows for efficient circuit module level replacement redundancy for a further improved chip yield compared to the architecture.

To maintain the full redundancy characteristics of a signal segment, all circuits associated with the interconnect network are uniform with respect to any wire in the segment, and therefore any wire in the segment It is possible to take a specific form for any signal in the bus. FIG.
Shows a schematic diagram of a transceiver circuit linking buses BUS1 and BUS2. Each wire 102-1, 102-2,... On one side of the transceiver. . . , 10
2-c are the transceivers 80-1, 80-2,. . . ,
80-i, two internal control signals (R: receive,
T: transmit) and wires 122-1, 12 on the other side
2-2,. . . , 122-d. The control logic 126 may be configured to provide appropriate signal wires 120-1, 120-2,. . . ,
120-c and 122-1, 122-2,. . . , 12
2-d connected to three input signals (CTL, RC
K, WCK).

FIG. 6b shows the control logic 12 of the transceiver circuit.
6 shows the state diagram of FIG. The six states of transceiver operation are as follows. (I) IDLE (idle): the transceiver has been reset and is ready to receive data from BUS1. (Ii) REC
EIVE WRITE: BUS1 is trying to write data into a certain circuit module. (I
ii) RECEIVE: The specified module is attached to the transceiver and accepts data from BUS2. (Iv) RECEIVE READ
(Reception reading): BUS1 is trying to read data from a certain circuit module. (V) TRANSMIT
(Transmit): The specified module is attached to the transceiver and transmits data into BUS2. (V
i) TRI-STATE: The specified module is not attached to the transceiver and the transceiver is inactive.

Although this state diagram is relatively complex, the transceiver operates in three basic modes of operation (see bottom of FIG. 6b): (R = 1, T = 0), (R = 0, T = 1). ) And (R = 0, T = 0). Reception mode (R = 1, T
= 0) has been divided into four states to better illustrate the typical sequence of communication operations on the bus. The signal transitions and / or levels used in this state transition diagram are exemplary and many different variations are possible.

The repeater circuits 82-1,. . . , 82-i
Is schematically shown in FIG. 7a. Each wire 124-1, 124-2,... On one side of the repeater. . . , 124
-E together with two internal control signals (R: receive, T: transmit) on the other side 128-1, 128-2,. . . , 128-f
Connected via transceiver. Control logic 13
2 generates two internal control signals having one input signal (RCK) connected to the appropriate signal wire together with the configuration. The state diagram of the control logic is shown in FIG. 7b.
Since the repeater circuit is smaller than the transceiver circuit, the transceiver circuit shown in FIGS. 6a and 6b as a repeater to further reduce the number of different circuits on the wafer for further simplicity and regular arrangement It is also possible to use a part of.

For another embodiment having the bus signals defined in FIG. 4a, a transceiver / repeater circuit embodiment is shown in FIG.
c and 7d. It should be noted that, except for differences in state transitions and input lines to the control logic, the basic operation and form of the transceiver / repeater 83-i with control logic 133 are shown in FIGS. 6a, 6b, 7
a, 7b.

In operation, the bus signals shown in FIG. 4e, the hierarchical tree bus architecture shown in FIG. 4a, and the transceiver / bus shown in FIGS. 7c and 7d
The repeater circuit allows efficient communication (whether on-chip or off-chip) between the circuit module and the controller and only requires one circuit module, one transceiver group and communication path. Along with only a minimum number of repeater groups are activated, enabling efficient power management.

For a read operation, the following sequence is used.

(1) CTL = 0, CTL
1 = 1, CTL2 = 0, and broadcast the command packet to all circuit modules.

(2) Next, the controller sets CTL1 =
Set to 0, causing all repeaters and transceivers to be tri-stated.

(3) Next, the controller sets CTL = 1.
And turn the bus over.

(4) If the selected circuit module is CT
Pull L1 = 1 to turn on only the path along the bus tree between the controller and the selected circuit module and send the data packet to the controller.

(5) After receiving all the data packets, the controller sets CTL2 = 1 and sets CTL1 = 1 for all unselected circuit modules.
And turn on the rest of the bus tree.

(6) Next, the controller sets CTL = 0.
And returns to the idle state.

In the case of the writing operation, the following sequence is used.

(1) CTL = 0, CTL
Set 1 = 1, CTL2 = 0, and broadcast the command packet to all circuit modules.

(2) Next, the controller sets CTL1 =
Set to 0 to tristate all repeaters and transceivers.

(3) Next, the controller sets CTL = 1.
And turn the bus over.

(4) The selected circuit module is CTL
Pull 1 = 1 to turn on only the path along the bus tree between the controller and the selected circuit module.

(5) Next, the controller sets CTL = 0.
Is set and the data packet is sent to the selected circuit module.

(6) After all data packets have been transmitted, the controller sets CTL = CTL2 = 1 and sets CTL for all unselected circuit modules.
Notify to pull TL1 = 1 and turn on the rest of the bus tree.

(7) Next, the controller sets CTL = 0.
And return to the idle state.

For applications where partial power savings are sufficient (eg, only read operations use the power saving mode while write operations always use the broadcast mode), the transceiver / repeater group And the control logic for the read / write operation sequence can be further simplified.

The bus signals shown in FIGS. 4b and 4e have both bidirectional and unidirectional signals. 6a, 7
The configuration of these unidirectional signals using the transceiver / repeater shown in FIGS. 7a, 7c can be achieved by using directional programmable switches (not shown, eg, fuses,
This can be achieved by using an EPROM, an EEPROM cell, etc., where one of the receivers or transmitters of the transceiver circuit can be permanently disabled.

FIGS. 6, 7a, 7b, 7c, 7d show the minimum functionality and protocol of the bus transceiver and repeater configuration for minimum area (ie, overhead) and maximum yield. More complex bus protocols and access modes (e.g., protocols to allow multiple controllers within each whole wafer or partial wafer device, protocols to enable circuit modules with variable hierarchy and priority, and Additional functions and states can be added to handle protocols that allow more than one type of bus to exist on a wafer, etc.). In these cases, only the number of input signals and the internal function of the control logic block are different, making all input (output) wires identical to each other and thus providing maximum configuration flexibility. The connection that allows this should not be changed.

Other Embodiments The components described above in accordance with the present invention make it possible to build very large chip size devices with very high yield and high performance. Many components, such as high-performance bus architectures, scalable device architectures, and high-yield module-level redundancy architectures, are new and useful themselves. Some of them are described below.

1. High performance, low power devices For devices with medium to small chip dimensions, a hierarchical tree bus architecture provides very fast data transfer capability, whether the device uses any of the redundancy features of the present invention. Nevertheless, it provides very low power dissipation with small area overhead. In applications where the redundancy circuits are minimal or non-existent, the interconnect circuits and transceiver / repeater circuits can be hard-wired with minimal optional or no such connections.

2. The grid structure of expandable device circuit blocks and segmented interconnect networks allows one or more circuit blocks to be combined together into a single device. It is possible to manufacture devices with different capabilities and chip sizes on one mask set or on the same completed wafer. This capability can significantly reduce product development cycles and minimize inventory levels. The device itself can be with or without redundancy.

[0072] 3. Redundant Medium Dimension Devices For medium chip size devices, using only intermediate levels of redundancy may be sufficient to achieve high yields. The interconnection network can be hardwired without redundancy. Redundancy (ie,
It is possible for the device to use a high-speed hierarchical tree bus architecture without a hardwired transceiver / repeater circuit) or any other conventional bus method.

[0073] Configuration (morphological identification) Procedure FIG. 8 shows a flow chart for testing and morphological identification of the wafer-scale device. With the help of the probe pads, at step 140, all circuit modules are individually 100% tested. Similarly, with the help of the probe pads, in step 142, all interconnect signal segments and power supply segments are placed within segment groups and between adjacent and crossover segment groups and between segment groups and circuit modules. 10 for defects at
0% tested. It should be noted that all interconnect segments are fully patterned to perform testing, and that the tests are valid and as complete as possible. Secure.

The configuration steps described below only generate connected junctions without adding wire segments or traces that may cause additional short-circuit defects. Should be. Any faulty modules, interconnect segments and especially short circuit faults are detected and recorded by a computer, which then generates an interconnect routing map, which in step 144, generates partial segments and modules. Only those which are defective and those which are defective are bypassed or isolated. The routing map specifies which connection points are to be connected and the configuration process is performed. Upon completion of the configuration process (or during a configuration, even during a dynamic test), the entire wafer or a portion of the wafer may be tested again at step 146. Previously undetected or newly created defects can be bypassed or isolated using an optional reconfiguration step 148 (eg, a blown fuse or (Using a laser cutter or other repair system such as a focused ion beam device) or simply using a controller initiated software reconfiguration program. An important feature of this configuration procedure is that the interconnect segments are completely formed and tested for short-circuit defects prior to the generation of the routing map in step 144, and thus, after configuration, a very high yield interconnect circuit. The point is that it is possible to secure a network.

Junction Configurations and Programming Junctions used in segmented interconnect networks can be implemented in a variety of physical processes (fuse, antifuse and / or EPROM, EEPROM, flash EPROM, static RAM cell, and others). ) And programmed using a variety of processing, electrical or energy means. In the preferred embodiment, the junction is configured as an antifuse (ie, normally open or has a high resistance and is shorted after programming or writing and has a low resistance). .

FIGS. 9a to 9d illustrate the process using a conventional masking step to construct a programmable or writable connection point. FIG. 9a shows a cross-sectional view of a typical wafer 12 on a silicon substrate 151 with all interconnect layers 152, 154 already patterned. The first interconnect layer 152 can be metal (in a two or more layer metal process) or silicide / polycide and the second interconnect layer 154
Is typically a metal having an interlayer insulating layer 156 (which can be silicide / polycide). Testing of the circuit modules and interconnect segments is performed at this point, with or without the optional protective insulating layer 160 of FIG. 9b. Having determined the connection points to be connected, they are patterned and each is etched into a through hole 164 as shown in FIG. 9b. It should be noted that the patterning of the through holes 164 can be performed in various ways. That is,
(1) Manufacturing a conventional mask for a particular wafer and then exposing the photoresist using a custom made mask. (2) Use an electron beam or laser beam to expose the photoresist directly at the desired spot on the wafer without fabricating a mask. (3)
Chemical etching or removal of photoresist using laser, ion or electron beam. Or
(4) Direct chemical etching or removal of metals and insulators using lasers, ions or electron beams. After forming the through-hole 164, a layer of plug metal 168 is deposited and patterned using a conventional mask (all wafers share the same photomask) and programming is performed as shown in FIG. 9c. That is, the writing is completed. The plug metal 168 can be an aluminum alloy, a refractory metal, or a metal silicide.

Another embodiment of making a junction that can be programmed using energy means is shown in FIGS. 10a and 10b. In this case, the energy means can be one of the following energy sources or any combination thereof. (1) Using a probe pad to apply an electrical pulse to break down and melt the antifuse connection between the two segments. (2) Use a laser beam to locally heat the connection point and create an electrical connection between the top conductor and the bottom conductor. (3) Use an ion beam to drill holes through the metal and antifuse layers, then deposit a conductive material to connect the top and bottom conductors.

FIG. 10 a shows an antifuse layer 172 sandwiched between a top metal layer 152 and a bottom metal layer 154. The antifuse material 172 can be amorphous silicon or oxide or a combination thereof. The conductors 152 and 154 may be provided with barrier metals 174 (refractory metal or silicide) on both sides of the antifuse layer 172 to prevent unwanted reactions (eg, aluminum alloying with silicon). It is possible. All or some of the aluminum in the upper conductor can be removed from inside the connection point 176 to increase the energy coupled into the connection inside the connection point 176.

FIG. 10 b shows another embodiment in which the antifuse layer 172 is deposited in the through hole 180 at the connection point 176 and covered with the plug metal 184. The selection of the antifuse layer 172 may be such that the plug metal 184 is heated during normal alloying (no barrier metal is present) or at the same time that the bottom of the connection point is heated by the energy means 186. It is like being connected to the upper conductor 154 at the side wall. The plug metal 184 and the bottom conductor 152 can have a barrier metal 174 (refractory metal or silicide) on each side of the antifuse layer, with an optional top insulating layer 160.

Although the specific embodiments of the present invention have been described in detail, the present invention should not be limited to these specific examples, but may be variously modified without departing from the technical scope of the present invention. Of course is possible.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing an embodiment of a wafer-scale integrated semiconductor device having a plurality of semiconductor circuit chips which have VCC, VSS power supply interconnections and signal bus interconnections and are all formed on one wafer. .

FIG. 2a is a schematic diagram illustrating an interconnect segment with a junction box and a module interface box.

FIG. 2b is a schematic diagram illustrating two-dimensional routing using a segmented interconnect system.

FIG. 2c is a schematic diagram showing a detailed layout for a probe pad for performing a simple and complete test.

FIG. 2d is a schematic diagram illustrating another configuration for a connecting horizontal segment (vertical or horizontal) capable of changing the wiring position between adjacent segments.

FIG. 2e is a schematic diagram showing another configuration for a connecting horizontal segment (vertical or horizontal) having the ability to change the wiring position between adjacent segments.

FIG. 2f is a schematic diagram illustrating the configuration of a test transistor for testing open defects in an interconnect segment.

FIG. 3a is a schematic diagram showing a power switch.

FIG. 3b is a schematic diagram showing a direct connection power switch.

FIG. 4a is a schematic diagram illustrating a hierarchical bus architecture embodiment.

FIG. 4b is a schematic diagram showing signals related to BUS1 and BUS2.

FIG. 4c is a schematic diagram illustrating the configuration of a hierarchy bus architecture configured without distinction between transceivers and repeaters.

FIG. 4d is a schematic diagram illustrating an example of a wafer scale device that has been specified in accordance with the architecture of FIG. 4c.

FIG. 4e is a schematic diagram showing another signal related to BUS1 and BUS2.

FIG. 4f is a schematic diagram showing an example of a wafer-scale apparatus whose configuration is specified according to the bus architecture of FIG. 4a.

FIG. 5a is a schematic diagram illustrating an embodiment of a module interface circuit.

FIG. 5b is a schematic diagram showing a generalized redundant circuit module.

FIG. 6a is a schematic diagram illustrating a transceiver circuit embodiment.

FIG. 6b is a state diagram of the control logic of FIG. 6a.

FIG. 7a is a schematic diagram of a repeater circuit embodiment.

FIG. 7b is a state diagram showing the control logic of FIG. 7a.

FIG. 7c is a schematic diagram illustrating a transceiver / repeater circuit embodiment.

FIG. 7d is a state diagram showing the control logic of FIG. 7c.

FIG. 8 is a flowchart showing a procedure for testing the wafer scale apparatus and specifying the configuration.

FIG. 9a is a schematic cross-sectional view showing a state in one stage of a processing flow for forming a connection point using a semiconductor processing technique.

FIG. 9B is a schematic cross-sectional view showing a state in one stage of a processing flow for forming a connection point using a semiconductor processing technique.

FIG. 9c is a schematic cross-sectional view showing a state in one stage of a processing flow for forming a connection point using a semiconductor processing technique.

FIG. 10a is a schematic cross-sectional view showing a state in another process of forming a connection point using energy means.

FIG. 10b is a schematic sectional view showing a state in another processing for forming a connection point using energy means.

[Explanation of symbols]

12 semiconductor wafer 16-i circuit chip module 18-i transceiver / repeater module 22 interconnection network 24-i module / bus interface section 32-i module block

 ────────────────────────────────────────────────── ─── Continuing on the front page (73) Patentee 592142049 Wingyu Lung United States, California 95014, Cupertino, Orange Avenue 10450 (72) Inventor Fu Chi Two United States, California 95070, Saratoga, Congress Hall Lane 21775 (72) Inventor Wing Ryung United States, California 95014, Cupertino, Orange Avenue 10450 (56) References JP-A-3-204957 (JP, A) JP-A-60-95641 (JP, A) JP-A-60 -65545 (JP, A)

Claims (12)

(57) [Claims] 1. A semiconductor device formed on a substrate, wherein a plurality of circuit blocks are provided on the substrate.
Each circuit block has substantially the same dimensions and is arranged in a lattice shape extending along the first and second directions. Each circuit block has a plurality of circuit modules. An interconnect circuit having a plurality of interconnect segments extending along at least one of said first and second directions;
Each interconnect segment has a plurality of signal lines and a redundant signal line, and a first plurality of connection points for coupling the interconnect segments are provided, and the first plurality of connection points are A plurality of segment probe pads coupled to each of the interconnect segments, the interconnect segments being initially open and initially separating the interconnect segments from each other, wherein the interconnect segments are separated. Testing of the interconnect segments for defects in and between the interconnect segments by probing the segment pads in the closed state, wherein a plurality of interconnects are coupled to each of the circuit modules. A module probe pad is provided for connecting the interconnect segment to the module probe pad. A second plurality of connection points is provided, the second plurality of connection points being normally open and initially separating the circuit module from the interconnect segment Testing the circuit module for defects by probing the module probe pad with the module separated from the interconnect segment. 2. The power supply circuit according to claim 1, further comprising a power supply circuit for supplying power to each circuit module, wherein said power supply circuit has one or more power supply lines positioned parallel to said interconnect segment. A plurality of power switches are provided, and one power switch is coupled between each circuit module and the power line. 3. The method of claim 2, wherein a first line of the interconnect segment is connected to a first probe pad and a second line of the interconnect segment is connected to a second probe pad. A crossover connection point connecting the first line and the second line is provided, and a test for an open defect of the first line and the second line is performed on the first and second lines.
A semiconductor device, which can be implemented by probing a probe pad. 4. The semiconductor device according to claim 1, wherein at least one transceiver is connected between at least one of the interconnect segments and an I / O port of the circuit. 5. The circuit of claim 1, wherein the interconnect circuit is connected between at least one of the signal lines in the first circuit block and some of the signal lines in the second circuit block. A semiconductor device having one transceiver. 6. The semiconductor device according to claim 4, wherein the transceiver has a receiver and a transmitter, each of which is tri-state controlled. 7. The first clock signal line according to claim 1, wherein the signal line has a data line, two clock signal lines, and a control line. Wherein a second clock signal line carries a timing signal from the circuit block and a second clock signal line carries a timing signal from the circuit block. 8. The transceiver of claim 6, further comprising control logic for generating a control signal for the tri-state control, wherein the control logic is connected to one of the transceivers via a programmable connection. A semiconductor device characterized by being connectable to a semiconductor device. 9. The semiconductor device according to claim 8, wherein the control logic has three states including reception, transmission, and tri-state, each of which is controlled by the control signal. 10. The semiconductor device according to claim 1, wherein each power switch has a plurality of connection points to an associated circuit module. 11. The semiconductor device according to claim 10, wherein the plurality of connection points are initially short-circuited. 12. The power supply switch according to claim 1, wherein each power switch includes a transistor having a control terminal and a resistor, wherein the resistor is connected between the control terminal and a predetermined power supply voltage. A semiconductor device.