JP3191529B2 - Semiconductor device with ceramic capacitor and ceramic capacitor mounted - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bypass ceramic capacitor used for semiconductor elements such as ICs and LSIs, and a semiconductor device provided with the ceramic capacitor.

[0002]

2. Description of the Related Art In recent years, there has been no end to the trend toward miniaturization and high-speed digitalization of electronic devices. Accordingly, there is an increasing demand for smaller and higher-density mounting of electronic components used in these electronic devices. Conventionally, a bypass capacitor used for a semiconductor device such as an IC or an LSI, which is the basis for downsizing and high-speed digitalization of this electronic device, has been mounted around a semiconductor device such as an IC or an LSI on a circuit board. . For this reason, this bypass capacitor is laminated,
A device has been devised to reduce the area occupied by the substrate by reducing the size by chipping or the like. As a result, chip-type multilayer ceramic capacitors are mainly used for these applications.

[0003]

However, in the conventional method of mounting a bypass capacitor around a semiconductor element such as an IC or an LSI on a circuit board, even if the size of the bypass capacitor is reduced, IC and L
Around the semiconductor element such as SI, a bypass capacitor itself and a mounting space for its wiring are required, and there has been a limit to miniaturization as a circuit board.

Further, there is a problem that an inductance component generated in a wiring portion from a semiconductor element such as an IC or LSI to a bypass capacitor cannot be ignored, and a high-speed circuit cannot completely remove noise.

SUMMARY OF THE INVENTION An object of the present invention is to provide an IC or L / L device which does not require mounting space or wiring space on a circuit board, has a small inductance of a capacitor body and wiring, and has a sufficient noise removing function even in a high-speed digital circuit.
An object of the present invention is to provide a bypass capacitor used for a semiconductor element such as an SI and a semiconductor device provided with the capacitor.

[0006]

That is, the first aspect of the present invention is as follows.
Ceramic capacitors are invention, one capacitor electrode of smaller area than the main surface of this is formed in a central portion of one main surface of the ceramic dielectric substrate, the other on the other main surface of said ceramic dielectric substrate A capacitance electrode is formed, and the other capacitance electrode is electrically connected to a lead electrode formed around one main surface of the ceramic dielectric substrate with a gap from the one capacitance electrode. And an insulating layer is formed on the lead-out electrode and the one capacitance electrode,
At least one pair of solder bumps penetrating the insulating layer and electrically connected to the lead electrode and the one capacitor electrode, respectively, are formed close to each other .

Further, Sr is used as a ceramic dielectric substrate.
By using a substrate for a TiO ₃ -based grain boundary insulating semiconductor capacitor, a ceramic capacitor having a large capacity and excellent frequency characteristics can be obtained.

Further, in a semiconductor device to which a ceramic capacitor according to the second invention of the present invention is mounted, the ceramic capacitor according to the first invention is provided such that solder bumps of the ceramic capacitor are provided on the surface of the semiconductor element having external connection electrodes. Are fixed with an insulating layer interposed therebetween, with the surface having the side facing outward.

[0009]

The ceramic capacitor of the present invention is used as follows. That is, first, the ceramic capacitor of the present invention was placed so that
It is fixed to a surface of a semiconductor element such as C or LSI having an electrode for external connection via an insulating layer. Next, the capacitance electrode and the lead-out electrode of the ceramic capacitor and the electrode for external connection of the semiconductor element are connected to the electrodes of the circuit board by solder bumps and mounted.

Therefore, no special mounting space or wiring space is required when mounting the capacitor. Further, an increase in the inductance component due to the wiring at the time of mounting can be suppressed to a minimum.

Further, the ceramic capacitor of the present invention has a structure in which a capacitance electrode facing a flat ceramic dielectric is provided, and the internal inductance of the capacitor can be almost ignored. Also, solder bumps for input and output
Are provided close to each other, so the magnetic flux is canceled
And low inductance.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the ceramic capacitor of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing a first embodiment, FIG. 2 is a cross-sectional view taken along line XX of FIG. 1, and FIG. 3 is a cross-sectional view showing a manufacturing process.

1 and 2, reference numeral 1 denotes SrTiO.
A ceramic dielectric substrate for a ₃ system grain boundary insulating semiconductor capacitor, 3a is one capacitor electrode made of Cu formed on one main surface of the ceramic dielectric substrate 1, and 3b is the other of the ceramic dielectric substrate 1. This is the other capacitor electrode made of Cu formed on the main surface. Reference numeral 3c denotes a lead electrode made of Cu formed around the ceramic dielectric substrate 1, and is connected to the capacitor electrode 3b. Reference numerals 4a and 4b denote insulating layers having solvent resistance, and 6 denotes a solder bump made of Pb-Sn.

Next, a method for manufacturing the ceramic capacitor of the present invention will be described with reference to FIG. First, 10mm square,
A 0.4 mm thick ceramic dielectric substrate 1 for SrTiO ₃ -based grain boundary insulating semiconductor capacitors was prepared by a conventionally known method. On one main surface of the ceramic dielectric substrate 1, a pitch-based resist ink dissolved in an organic solvent but not dissolved in a plating solution was printed and dried to form a square-shaped resist layer 2 as viewed from the surface. . Thereafter, the ceramic dielectric substrate 1 on which the resist layer 2 has been formed is subjected to a sensitizing and activating treatment as a pre-treatment, and then to an electroless Cu.
Plating was performed, and a capacitor forming electrode 3 made of Cu was formed on the entire surface of the ceramic dielectric substrate 1. Next, on both surfaces of the ceramic dielectric substrate 1 on which the capacitance forming electrodes 3 were formed, a masking paste having an insulating property and not dissolved in an organic solvent after printing was printed and dried, and the resist layer 2 was formed first. An insulating layer 4a provided with small holes 5 for forming solder banks was formed on the entire surface except for the resist layer 2 on one main surface, and an insulating layer 4b was formed on the entire surface of the other main surface. . The ceramic dielectric substrate 1 treated as described above is immersed in an organic solvent to dissolve the resist layer 2, and the capacitance forming electrode 3 is
The capacitor electrode 3a and the capacitor electrode 3b connected to the lead-out electrode 3c shown in FIG. 2 were separated.

Next, after the solder paste is applied on the small holes 5 of the insulating layer 4a by screen printing, the solder paste is heated in an H ₂ atmosphere to melt the solder, and the solder bumps 6 shown in FIGS. Was formed.

FIG. 4 shows a mounting example of the ceramic capacitor thus obtained. The ceramic capacitor 11 of the present invention is attached to the surface of the semiconductor element 12 having the electrodes for external connection with the adhesive 13 with the surface having the solder bumps 6 on the outside through the insulating layer made of the insulating layer 4b. After fixing, ceramic capacitor 1
1 and the external connection electrode (not shown) of the semiconductor element 12 with the circuit board 14 and the solder bump 6.
Connected with.

By employing the above mounting method, a special space for mounting and wiring a ceramic capacitor on a circuit board is not required, while a sufficient noise removing effect has been recognized.

When the noise removal characteristics were tested by changing the capacitance of the ceramic capacitor, the capacitance was reduced by about 20% compared to the conventional case where the ceramic capacitor was mounted on a substrate around a semiconductor element. The noise removal effect equivalent to the conventional was obtained with the capacitance. This is because an increase in inductance due to the mounting of the ceramic capacitor 11 is suppressed by fixing the ceramic capacitor 11 having a simple structure to the semiconductor element 12 and connecting both to the circuit board by solder bumps to shorten the wiring. It is because.

In the above embodiment, the ceramic dielectric substrate is made of SrTiO ₃ -based ceramics for the grain boundary insulating semiconductor capacitor. However, the material is not limited to this. For example, BaTiO ₃ -based ceramics may be used. Various materials such as a ceramic dielectric can be used.

In the above embodiment, Cu is used as the material of the capacitor electrode. However, the present invention is not limited to this. For example, Ag, Pd, Ni, etc., which are well-known as electrodes of a ceramic capacitor, alone or in combination, or Ag-Ni, Cu
-A multilayered material such as Ni can be used as appropriate.
Further, Au, Sn, or the like having good solder bump connectivity can be formed as an outer layer electrode on the capacitor electrode.

The insulating layer formed on the other main surface of the ceramic capacitor having no solder bump is not essential. In terms of performance, there is no particular need if the surface of a semiconductor element such as an IC or LSI to which the ceramic capacitor of the present invention is fixed during mounting is insulated.

Further, the method for manufacturing the ceramic capacitor of the present invention is not limited to the above embodiment. For example, an electrode is directly formed on the entire surface in advance without using a resist ink, and then the electrode is formed by acid etching. It is also possible to dissolve and remove a part of it to separate it into a capacitor electrode for a capacitor. The method for forming the electrodes is not limited to electroless plating, and the electrodes can be formed by a thin film method such as vapor deposition or a thick film method such as screen printing.
Further, as for the method of forming the solder bumps, in addition to the method of melting only the Pb-Sn-based solder paste as in the present embodiment, a Sn-Pb-based or Sn-Ag-based solder using Cu or Ag as a core material is used. Various known methods, such as forming by melting, can be adopted.

The shape of the capacitor, including the shape of the electrodes, is not limited to this embodiment. Hereinafter, another embodiment will be described. FIG. 5 shows a second embodiment, in which an insulating layer 4a formed at the center of one main surface of a ceramic dielectric substrate 1 is formed.
Is divided into two parts, 3aa and 3ab, so that two different capacitances can be obtained in the same ceramic capacitor. Other parts are the first
1 and FIG. 2 which are the embodiments of the present invention, the same reference numerals are given and the description is omitted.

FIG. 6 shows a third embodiment, in which a lead electrode formed around a capacitor electrode on one main surface of a ceramic dielectric substrate 1 and a capacitor electrode formed on the other main surface are connected to a ceramic dielectric substrate. The connection is made not through the end face of the substrate 1 but through the through hole 7. The other parts are the same as those in the first embodiment shown in FIGS. 1 and 2, and therefore, the same reference numerals are given and the description is omitted.

FIG. 7 shows a fourth embodiment, in which a lead electrode 3c formed around one main surface of a ceramic dielectric substrate 1 is shown.
The protrusions 8 are provided on a lower layer (not shown in FIG. 7 below the insulating layer 4a) to increase the area so that solder bumps can be easily formed. The other parts are the same as those in the first embodiment shown in FIGS. 1 and 2, and therefore, the same reference numerals are given and the description is omitted.

FIG. 8 shows a fifth embodiment, in which a lead electrode 3c (FIG. 8) formed on one main surface of the ceramic dielectric substrate 1 is shown.
In this case, the lower layer (not shown) under the insulating layer 4a is formed not on the entire periphery of one main surface but on a part of the periphery. The other parts are the same as those in the first embodiment shown in FIGS. 1 and 2, and therefore, the same reference numerals are given and the description is omitted.

[0027]

As is apparent from the above description, the ceramic capacitor of the present invention can be fixedly mounted on a circuit board below a semiconductor element such as an IC or LSI.
Therefore, high-density mounting is possible without requiring any special mounting space or wiring space during mounting.

Also, the ceramic capacitor of the present invention
It has a simple structure in which a capacitance electrode facing a flat dielectric is provided, and the internal inductance of the capacitor can be almost ignored. In addition, when connecting to a semiconductor element such as an IC or LSI, the capacitance electrode and the lead-out electrode of the ceramic capacitor fixed to the semiconductor element are close to each other.
By connecting to the circuit board with solder bumps, the magnetic flux
Thus, the increase in inductance due to wiring can be minimized. Therefore, a sufficient noise removing effect can be obtained even in a high-speed digital circuit.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a first embodiment of a ceramic capacitor according to the present invention.

FIG. 2 is a cross-sectional view taken along line XX of FIG.

FIG. 3 is a cross-sectional view showing a process of manufacturing the ceramic capacitor of the present invention.

FIG. 4 is a sectional view showing a semiconductor device to which the ceramic capacitor of the present invention is attached.

FIG. 5 is a perspective view showing a second embodiment of the ceramic capacitor of the present invention.

FIG. 6 is a perspective view showing a third embodiment of the ceramic capacitor of the present invention.

FIG. 7 is a perspective view showing a fourth embodiment of the ceramic capacitor of the present invention.

FIG. 8 is a perspective view showing a fifth embodiment of the ceramic capacitor of the present invention.

[Explanation of symbols]

 Reference Signs List 1 ceramic dielectric substrate 2 resist layer 3 capacitor forming electrode 3a, 3b capacitor electrode 3c lead electrode 4a, 4b insulating layer having solvent resistance 5 small hole for forming solder bump 6 solder bump 7 through hole 8 protrusion of lead electrode Part 11 ceramic capacitor 12 semiconductor element 13 adhesive 14 circuit board

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01G 4/00-4/40 H01G 13/00-13/06

Claims (3)

(57) [Claims] 1. In one main surface of a ceramic dielectric substrate
Central portion one capacitor electrode of smaller area than the main surface of this is formed on the ceramic dielectric other main surface of the substrate is formed with the other capacitor electrode, the other capacitor electrode is the one capacitance deriving electrode electrically formed around the one main surface of the ceramic dielectric substrate at a gap between electrodes
And an insulating layer is formed on the lead electrode and the one capacitor electrode , and at least electrically connected to the lead electrode and the one capacitor electrode respectively through the insulating layer. A ceramic capacitor in which a pair of solder bumps are formed close to each other . 2. The ceramic capacitor according to claim 1, wherein the ceramic dielectric substrate is a substrate for an SrTiO ₃ -based grain boundary insulating semiconductor capacitor. 3. The ceramic capacitor according to claim 1, which is fixed to a surface of the semiconductor device having an external connection electrode with an insulating layer having a surface of the ceramic capacitor having a solder bump outside. Semiconductor device.