JP3184061B2 - Test circuit and test method for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit and a test method for a semiconductor integrated circuit, and more particularly to a test circuit for a semiconductor integrated circuit using a linear feedback shift register.
The present invention relates to an improvement of a test circuit and a test method of a semiconductor integrated circuit for testing (abnormal).

[0002]

2. Description of the Related Art In recent years, in a test of a large-capacity memory realized by a semiconductor technology which is highly integrated and miniaturized, how to perform the test efficiently and in a short time has become a major problem. Also, many chips with built-in memories, such as microprocessors and DSPs, are manufactured, and it is difficult to test the built-in memories using only external terminals, which is also a major problem.

Therefore, as one of the test methods for solving the above-mentioned problem, there has been proposed a method of performing an automatic test by incorporating a test circuit for a semiconductor integrated circuit on a chip. According to this proposed method, if the automatic test is performed every time the power is turned on, the test result can be determined by the user for each use, which is advantageous in that maintenance or reliability in the market is improved.

In the automatic test method, as a kind of compact test method, an output series of a semiconductor integrated circuit such as a memory is compressed using a linear feedback shift register (hereinafter, referred to as LFSR). There is. Here, the LFSR generally includes a plurality of registers, a plurality of two-input exclusive OR gates arranged in front of the registers, an output of a register in the last stage, and an output of a register in a middle stage. And feedback information generating means for generating feedback information from the control information. Hereinafter, an automatic test method using LFSR will be described.

First, data read from a memory such as a ROM, a RAM, or a PLA is input to a parallel input LFSR, and such input information is compressed by the parallel input LFSR to obtain a compressed value (signature) of the output sequence. .

Next, the signature obtained by the parallel input LFSR is compared with an expected signature inside the chip to judge whether the output sequence is correct, or the obtained signature is scanned out using a scan path, and the chip is scanned out of the chip. Then, the correctness of the output sequence is determined by comparing with the expected signature, and the normality of the memory is determined.

A method for determining the correctness of data inside the chip is described in, for example, "Design by Patrick P. Gelsinger".
and Test of the 80386 "(IEEE, Design & Test of Comp
t., vol.4 no.3, pp.42-50 June 1987), the obtained signature and the pre-stored expected signature are input to the ALU, and the exclusive logical operation by the ALU is performed. This can be realized by storing the result in the diagnostic register. In this case, if the obtained signature matches the expected signature, that is, if the memory is normal, zero is stored in the diagnostic register. If not, that is, if the memory is not normal, a non-zero value is stored in the diagnostic register. Is stored.

[0008]

However, in the test circuit and the test method for a semiconductor integrated circuit as described above, the correctness of an output sequence of a memory or an internal functional block is determined by comparing the signature with an expected signature inside the chip. Requires (1) comparison means for comparing the compressed value of the output sequence with the expected signature in addition to the parallel input LFSR. (2) If the ALU is used as the comparison means, the expected signature is stored in advance. In addition to the need for storage means, it is necessary to connect the parallel LFSR to the ALU via a data bus, and a layout is restricted in order to obtain a compact arrangement.
This is not always easy as a test circuit and method for a semiconductor integrated circuit due to factors such as an increase in the number of blocks to be controlled, such as the comparing means and the storing means, which necessitate complicated control by a microprogram. There are drawbacks.

In order to determine whether the output sequence of the memory is correct or not by comparing the signature with the expected signature outside the chip,
(4) The expected signature of the chip to be determined is required outside the chip, but a user who cannot know the expected signature cannot use the built-in test. (5) Even if the chips are functionally identical, they are built-in. ROM and R
It is necessary to prepare and manage each expected signature according to the type of data written in the AM, and to compare it with the corresponding expected signature. There was a problem of lack of flexibility.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a test circuit and a test method for a semiconductor integrated circuit using a parallel input LFSR for inputting and compressing parallel data. While adopting a method that compares the signature with the expected signature inside the chip,
An object of the present invention is to provide a test circuit and a test method capable of performing a test of a semiconductor integrated circuit with a simple control without a comparison means.

[0011]

In order to achieve the above object, according to the present invention, a test circuit is provided with an operation for comparing a compression signature obtained by compression by a parallel input LFSR with an expected signature, and the calculation operation is performed by a test circuit . An operation circuit for performing compression , for example, a two-input exclusive OR gate of the parallel input LFSR is used to perform the compression .

That is, a test circuit for a semiconductor integrated circuit according to the first aspect of the present invention uses a compact test circuit which receives a plurality of parallel data sequentially from the semiconductor integrated circuit and compresses the input plurality of parallel data. a test circuit of the integrated circuit, the expected compression value storage means for storing an expected compressed value, originally provided in the test circuit, the parallel de
An arithmetic circuit for compressing the data, and information collecting means for giving to the arithmetic circuit the compressed value obtained by the compression by the compact test circuit and the expected compressed value of the expected compressed value storage means to the arithmetic circuit. The comparison circuit for comparing the compressed value and the expected compressed value is also used by the arithmetic circuit originally provided.

According to a second aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the first aspect, the compact test circuit includes a parallel input linear feedback shift register.

According to a third aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the second aspect, the parallel input linear feedback shift register is arranged in front of the plurality of registers and each of the registers. A plurality of two-input exclusive-OR gates; and feedback information generating means for generating feedback information from the output of the last-stage register and the output of the middle-stage register. The outputs of the exclusive-OR gates are respectively input, and the first input of each of the two-input exclusive-OR gates except the two-input exclusive-OR gate located at the preceding stage of the first-stage register is the register of the preceding stage. And a first input of a two-input exclusive OR gate located before the first register is connected to the feedback information selecting means. The operation circuit originally provided is a plurality of two-input exclusive OR gates provided in the parallel input linear feedback shift register, and the information collecting means includes a feedback of the parallel input linear feedback shift register. Feedback information selecting means for selecting one of the output of the information generating means and the output of the last-stage register by a control signal; and data to be given to the second input of each register of the parallel input linear feedback shift register. It is characterized by comprising input selection means for selecting one of the parallel data and the expected compression value of the expected compression value storage means by a control signal.

According to a fourth aspect of the present invention, in the test circuit of the semiconductor integrated circuit according to the first, second, or third aspect, the semiconductor integrated circuit to be tested is a memory. .

According to a fifth aspect of the present invention, in the semiconductor integrated circuit test circuit according to the first, second, or third aspect, the semiconductor integrated circuit to be tested is an internal functional block. Features.

According to a sixth aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the third aspect, the input selecting means is constituted by a two-input multiplexer.

According to a seventh aspect of the present invention, in the test circuit of the semiconductor integrated circuit according to the third aspect, one test data bus is provided, and each of the data buses has a two-input exclusive-input of a parallel input linear feedback shift register. The OR gate is directly connected, and the semiconductor integrated circuit and the expected compression value storage means are connected via output buffers, respectively.
The input selection means is a control circuit which controls each output buffer of the semiconductor integrated circuit and the expected compression value storage means so as to output any one of the data of the semiconductor integrated circuit and the expected compression value storage means to the data bus. It is characterized by comprising.

According to an eighth aspect of the present invention, in the semiconductor integrated circuit test circuit according to the seventh aspect, a plurality of semiconductor integrated circuits are connected to the data bus.

According to a ninth aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the third or seventh aspect, the input selecting means compresses parallel data from the semiconductor integrated circuit by a control signal. In the compression cycle, parallel data from the semiconductor integrated circuit is selected, and when comparing the obtained compression value with the expected compression value, the expected compression value of the expected compression value storage means is selected.

According to a tenth aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the third aspect,
The expected compression value storage means stores the expected compression value by rotating only one bit in advance in the shift direction of the parallel input linear feedback shift register.

According to the eleventh aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the third aspect,
The parallel input linear feedback shift register includes an output buffer for connecting the output of each register and the output of the feedback information selection means to the data bus, and the first of the two-input exclusive OR gates. Are directly connected to the data bus, and the first input of each of the two-input exclusive-OR gates except the two-input exclusive-OR gate located at the preceding stage of the first-stage register is respectively connected to the first-stage register. Is provided through the output buffer and the data bus, and the output of the feedback information selecting means is provided to the first input of a two-input exclusive OR gate located in front of the first register. And provided via the data bus.

According to a twelfth aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the eleventh aspect,
The parallel input linear feedback shift register includes another data bus. The parallel input linear feedback shift register further includes another output buffer for connecting an output of each register and an output of the feedback information selection unit to the other data bus. The second input of the exclusive OR gate is connected directly to the data bus, and the second input of each two-input exclusive OR gate except for the two-input exclusive OR gate located in front of the first register. The output of the preceding register is provided via the other output buffer and the other data bus, respectively, and the second input of the two-input exclusive OR gate located before the first register is provided to the second input. The output of the feedback information selecting means is provided through the other output buffer and the other data bus.

According to a thirteenth aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the twelfth aspect, the data bus and the other data bus each include:
A semiconductor integrated circuit and an expected compression value storage unit are connected, the semiconductor integrated circuit and the expected compression value storage unit each include an output buffer, and the input selection unit inputs one of the two data buses in parallel. The semiconductor integrated circuit is used to output data from one of a semiconductor integrated circuit and expected compressed value storage means connected to the other data bus to the other data bus while being used for compression of the linear feedback shift register. The circuit comprises an output buffer incorporated in each of the circuit and the expected compressed value storage means, and a control circuit for controlling each output buffer incorporated in the parallel input linear feedback shift register.

[0025] In addition, in the invention according to claim 14,
13. The test circuit for a semiconductor integrated circuit according to claim 12, wherein the data bus and the other data bus are respectively connected to a semiconductor integrated circuit, the semiconductor integrated circuit includes an output buffer, and the input selection unit includes: Outputting data from the semiconductor integrated circuit connected to the one data bus to one data bus, and outputting data from the semiconductor integrated circuit connected to the other data bus to the other data bus, The output buffer and the parallel input linear feedback shift register incorporated in the semiconductor integrated circuit are arranged so that the data output to both data buses are compared by each two-input exclusive OR gate of the parallel input linear feedback shift register. It comprises a control circuit for controlling each built-in output buffer.

According to the fifteenth aspect, the third aspect is provided.
8. The test circuit for a semiconductor integrated circuit according to claim 7, wherein each of the two parallel input linear feedback shift registers is connected to a corresponding one of the parallel input linear feedback shift registers.
It is characterized by comprising correctness judgment means for inputting the output of the input exclusive OR gate, judging the correctness of the semiconductor integrated circuit from the value of each input, and outputting the judgment result.

According to a sixteenth aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the third or seventh aspect, the output of each two-input exclusive OR gate of the parallel input linear feedback shift register is input. And a diagnostic register for storing the input content and outputting the input content.

Further, in the invention according to claim 17, in the test circuit for a semiconductor integrated circuit according to claim 7, scan-in information is input to the feedback information selection means, and the feedback information selection means is configured to output the scan-in information during the scan operation. The scan-in information is selected, and the output of the last register of the parallel input linear feedback shift register is connected to a scan path as scan-out information, and each register of the parallel input linear feedback shift register performs a scan operation as parallel data. It is characterized in that it is provided with a zero output means which sometimes gives zero, so that the outputs of all the registers of the parallel input linear feedback shift register can be observed from outside the test circuit.

In addition, in the invention according to claim 18, in the test circuit for a semiconductor integrated circuit according to claim 14, each of the two parallel input linear feedback shift registers is provided.
There is provided a correctness / judgment means for inputting a result of comparison between the two data at the input exclusive OR gate, determining a match or a mismatch between the two data, and outputting a result of the determination.

In addition, in the method of testing a semiconductor integrated circuit according to the present invention, data is sequentially read from the semiconductor integrated circuit in accordance with the same address sequence as when the expected compression value determined in advance is generated, and the read is performed simultaneously. The parallel data is sequentially input to each register of the parallel input linear feedback shift register in parallel, and the shift is repeated, thereby repeatedly compressing the parallel data sequentially. The output is obtained as a compressed value of the parallel data, and thereafter, the output of the last stage register is given to the first input of the two-input exclusive OR gate located before the first stage register, and the first stage register is excluded. A first input of a two-input exclusive OR gate located at the preceding stage of each register is provided with the output of the register at each preceding stage. In both cases, the expected compression value is input to the second input of each two-input exclusive OR gate of the parallel input linear feedback shift register, and the compressed value of the parallel data and the expected compression value are input by each two-input exclusive OR gate. A comparison operation is performed between bits corresponding to a value and a normality of the semiconductor integrated circuit is tested based on a result of the comparison operation.

According to the twentieth aspect of the present invention, the first aspect is provided.
9. The method for testing a semiconductor integrated circuit according to claim 9, wherein any one of the plurality of semiconductor integrated circuits is connected to one data bus via an output buffer, and data is sequentially transmitted from the connected semiconductor integrated circuit to the data bus. And compressing the read data, calculating the compression value, and comparing the obtained compression value with the expected compression value. Then, the other one of the plurality of semiconductor integrated circuits is used. Is connected to one data bus via an output buffer, data is sequentially read from the connected semiconductor integrated circuit via the data bus, compression of each read data, calculation of a compression value, and obtained compression value And repeating the comparison with the expected compression value.

According to a twenty-first aspect of the present invention, in the method for testing a semiconductor integrated circuit according to the nineteenth aspect,
When the data from the semiconductor integrated circuit is repeatedly compressed by the parallel input linear feedback shift register, the output and feedback information of the registers except for the last stage register of the parallel input linear feedback shift register for each compression of the data. Is input or stored as test data of a semiconductor integrated circuit connected to the data bus via the data bus.

Further, according to the invention of claim 22, in the method of testing a semiconductor integrated circuit of claim 19,
An initial value is scanned into the parallel input linear feedback shift register before the test is started.

According to a twenty-third aspect of the present invention, in the semiconductor integrated circuit test method according to the twenty-second aspect, the semiconductor integrated circuit to be tested is a plurality of memories, and each of the memories has a capacity and data to be written. The data or written data is different, and the initial value scanned in the parallel input linear feedback shift register is obtained in advance so that each expected compression value obtained by reading data from each memory becomes the same value. Is a predetermined initial value.

In addition, in the invention according to claim 24,
23. The method for testing a semiconductor integrated circuit according to claim 22, wherein the semiconductor integrated circuit under test is a plurality of internal function blocks, and each of the internal function blocks has a different function or a given input sequence. The initial value scanned into the linear feedback shift register is a predetermined initial value obtained in advance so that each expected compression value obtained from the output of each internal function block for each of the input sequences has the same value. And

[0036]

According to the above construction, the test circuit for a semiconductor integrated circuit according to any one of claims 1 to 18, and a 19th aspect.
In the semiconductor integrated circuit test method according to the twenty-fourth aspect, data from the semiconductor integrated circuit that is read or output in the same order as the expected value (expected signature) is obtained is input to the parallel input LFSR as parallel data. . By shifting the parallel data input to the parallel input LFSR in synchronization with the clock, the compressed value of the output sequence is sequentially stored in each register of the parallel input LFSR. When all the data is read and the repetition of the compression is completed, a desired compressed value (signature) obtained by compressing the output sequence of the data from the semiconductor integrated circuit is obtained.

In order to compare the obtained signature with the expected signature, the two signatures are provided to an arithmetic circuit originally provided in the test circuit and compressing parallel data . For example, the first input of a two-input exclusive OR gate arranged before the first register of the parallel input LFSR is supplied with the output of the last register and each register except the first register. The first input of the two-input exclusive OR gate arranged at the preceding stage is supplied with the output of the register located at each preceding stage. Also,
An expected signature is input to a second input of each of the two-input exclusive OR gates.

As a result, the corresponding bits of the compression signature composed of the respective outputs of all the registers and the expected signature for comparison are compared by the respective two-input exclusive OR gates of the parallel input LFSR. , The comparison result is stored in the register.

Therefore, based on the comparison result stored in each register, it is determined whether the compression signature matches the expected signature for comparison, and whether the semiconductor integrated circuit (memory or internal function block) is normal or abnormal. Will be.

Therefore, the test circuit originally provided in parallel
An arithmetic circuit for compressing data, for example, the parallel input LFSR itself used for data compression can compare the compression signature with the expected signature and determine whether the output sequence of the semiconductor integrated circuit is correct or not.

In particular, in the semiconductor integrated circuit test circuit according to the present invention, the semiconductor integrated circuit is connected to each of the two data buses and each of the parallel input LFSRs is connected to the two data buses.
Since the input exclusive OR gate is connected, data from each semiconductor integrated circuit connected to each data bus can be compared by each two-input exclusive OR gate of the parallel input LFSR.

In the test circuit for a semiconductor integrated circuit according to the seventeenth aspect of the present invention, the comparison result between the compressed value and the expected value at the two-input exclusive OR gate of the parallel input LFSR is scanned out, so that the chip Even when externally observing the correctness of the output sequence of the semiconductor integrated circuit, there is no need to manage the expected signature for each type of semiconductor integrated circuit,
And even if the user does n’t know the expected signature,
A true / false test of a semiconductor integrated circuit is possible.

Further, in the method for testing a semiconductor integrated circuit according to the present invention, when testing the semiconductor integrated circuit using the parallel input LFSR (more specifically, when data compression is repeated).
In parallel with this test, the intermediate compression information from the parallel input LFSR, that is, the output and feedback information of the registers other than the last stage register, are fed to the semiconductor integrated circuit connected to the data bus via the data bus. (A semiconductor integrated circuit different from the semiconductor integrated circuit under test) is stored as test data. Therefore, there is no need to connect a data generating means for generating test data and storing it in the semiconductor integrated circuit to the data bus, so that the data generating means becomes unnecessary and a cycle of storing test data in the semiconductor integrated circuit becomes unnecessary. .

In addition, in the semiconductor integrated circuit test method according to the present invention, the semiconductor integrated circuit to be tested is a plurality of memories or internal function blocks, and the memories have different capacities and the like. Even if the function of each internal function block is different, the expected compression value to be input is one, so the capacity of the expected compression value storage means can be reduced, and a flexible automatic test can be performed with a small area. be able to.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A test circuit and a test method for a semiconductor integrated circuit according to one embodiment of the present invention will be described below with reference to the drawings. The same numerals and symbols in the drawings used in the following description indicate the same elements throughout the drawings.

(First Embodiment) FIG. 1 is an overall configuration diagram of a test circuit of a semiconductor integrated circuit according to an embodiment of the present invention.

In FIG. 1, 1 is a parallel input linear feedback shift register (hereinafter referred to as a parallel input LFSR) as a compact test circuit, 2 is an expected signature storage register as expected compression value storage means for outputting an expected signature 21, 3 is a read data register.

The parallel input LFSR1 is provided with the expected signature 21 output from the expected signature storage register 2.
, Read data 31 output from the read data register 3, a test control signal (control signal) 12 output from the control circuit 10, and a clock signal 13. Gate XOR1 ~ XOR4
(Described later) is output.

Reference numeral 4 denotes a memory array which decodes the address 61 given by the address input 62 and stored in the address register 6 by the address decoder 5 and stores the contents of the word corresponding to the word line output from the address decoder 5. It is read as read data 41.
The read data 41 is stored in the read data register 3 and is read as the read data 31 by the parallel input LFSR.
1 is output.

Reference numeral 7 denotes a diagnostic register, which is an output 11 of a two-input exclusive OR gate (described later) and a test control signal 12.
And the clock signal 13 as inputs, and output the contents as output 7.
Output to 1.

Reference numeral 8 denotes a right / wrong judgment circuit which judges whether the memory is right or wrong by using the output 11 of each two-input exclusive OR gate (described later) of the parallel input LFSR1 as an input and outputs the judgment result 81. . The circuit configuration of FIG.
On-chip on one chip.

FIG. 2 shows a concrete example of a test circuit for comparing a compression signature obtained by compression by the parallel input LFSR 1 with an expected signature of the expected signature storage register 2 and determining whether the obtained compression signature is correct or not. FIG.

In the figure, the parallel input LFSR1 has 4
Registers S1 to S4 and their respective registers S1 to S4
Two-input exclusive-OR gates XO arranged in front of
R1, XOR2, XOR3, XOR4 and a two-input exclusive-OR gate XOR0 that receives the output of the last-stage register S4 and the output of the middle stage (register S3 in case of fourth order) as inputs.
It is a parallel input LFSR of bits. The parallel input LFS
The four 2-input exclusive OR gates XOR1 to XOR4 of R1 are:
The pressure of parallel data originally provided in the test circuit of this embodiment is
This is an arithmetic circuit that performs compression . The output of the two-input exclusive-OR gate XOR0 becomes feedback information to the register S1 at the first stage, and the two-input exclusive-OR gate XOR0 constitutes feedback information generating means.

[0054] The parallel input LFSR1 is for calculating realize 4-order primitive polynomial ^{g (X) = x 4 +} x + 1 of the following formula.

In the parallel input LFSR1, data is shifted from left to right in synchronization with the clock signal. In the following description, the leftmost register S1 is referred to as a first stage and the rightmost register S4 is referred to as a last stage register.

Read data 31 (I1, I2, I3, I4) from the memory array 4, which is an input of the parallel input LFSR1,
The expected signature 21 of the expected signature storage register 2 (E
1, E2, E3, E4) are selected by input selectors SEL1, SEL2, SEL3, SEL4 comprising two-input multiplexers as input selection means, and the output is selected from each of the two-input exclusive OR gates XOR1 to XOR4. Connected to the second input. Also,
Two-input exclusive OR gates XOR2 to XOR2 to other than the two-input exclusive OR gate XOR1 located before the first-stage register S1
Outputs of the preceding registers S2 to S4 are connected to the first input of XOR4.

On the other hand, an output of a feedback information selector SEL0 as feedback information selecting means is connected to a first input of a two-input exclusive OR gate XOR1 connected to an input of the first stage register S1. The feedback information selector SEL0 selects and outputs one of the output of the register S4 at the last stage and the output of the two-input exclusive OR gate (feedback information generating means) XOR0 according to the test control signal 12.

The input selectors SEL1 to SEL4 are also controlled by the test control signal 12 output from the control circuit 10. When the test control signal 12 is 0, the input selectors SEL1 to SEL4
L4 selects the read data 31 (I1, I2, I3, I4), and the feedback information selector SEL0 selects the feedback information. When the test control signal 12 is 1, the input selectors SEL1 to SEL4 output the expected signatures 21 (E1, E2, E3, E4).
And the feedback information selector SEL0 selects the output of the register S4 at the last stage.

The feedback information selectors SEL0 and SEL4
Input selectors SEL1 to SEL4 allow the parallel input LFS
The two-input exclusive-OR gates XOR1 to XOR4 of the parallel input LFSR1 are used to store the compression signature obtained by compression by R1 and the expected signature of the expected signature storage register 2.
The information collection means 18 is provided to XOR4 ( an operation circuit originally provided for compressing parallel data ).

The diagnostic register 7 receives the output 11 of each of the two-input exclusive-OR gates XOR1 to XOR4, the test control signal 12, and the clock 13, and makes the test control signal 12 write-enable at the end of the memory test. The result is stored, and the content is output to the output 71.

The correctness judgment circuit 8 also receives the outputs 11 of the two-input exclusive OR gates XOR1 to XOR4, and judges the correctness of the memory at the end of the memory test and outputs a memory correctness judgment result 81.

FIG. 3 is a timing chart for explaining the comparison between the compression signature and the expected signature by the parallel input LFSR1 and the determination of correctness in the embodiment of the present invention.

The test circuit of the semiconductor integrated circuit configured as described above will be described below with reference to FIGS.
The operation will be described. In the following description, for the sake of simplicity, the configuration of a memory (not shown) to be tested has a word number of 3
Assume that there are two words, each word being four bits.

In this embodiment, basically, the generation of the compression value and
The comparison between the obtained compression value (sought signature) and the expected compression value (expected signature) is performed by using the same parallel input LFSR1.
Is significantly different from the conventional method.

Hereinafter, the creation of a compression value in the test circuit and the comparison between the obtained compression value and the expected compression value will be described.
Here, for simplicity, it is assumed that data has already been written to the memory.

The following table shows the contents of the registers S1 to S4 in each information compression cycle in the predetermined initial value (1010) of the parallel input LFSR1 and the data read from the memory. In the values of the registers S1 to S4, the alphanumeric characters shown in parentheses are in hexadecimal notation. The contents 0011 (3 in hexadecimal notation) of the registers S1 to S4 in the 32nd cycle, which is the last cycle of information compression, indicate the signature to be obtained in this input sequence.

[0067]

[Table 1] In the table, the input data (read data from the memory) and the contents of the registers S1 to S4 are written in the order of I1, I2, I3, I4 / S1, S2, S3, S4 from the left. .

First, in the test start cycle, the first memory read address 61 is given, and reading of data from the memory is started. The read data 1111 (F in hexadecimal notation) is stored in the read data register 3 and output to the parallel input LFSR1. In parallel with this, an initial value (1010: A in hexadecimal notation in this example) is set in the parallel input LFSR1.

Subsequently, in the first cycle of compression, the test control signal 12 is 0, and the input selector outputs the read data 31 (I1, I2, I3, I4) to the feedback information selector SE.
L0 has selected feedback information. The test control signal 12 is always 0 during the compression operation. In this case, the read data 1111 is selected by the input selectors SEL to SEL4 and compressed by the parallel input LFSR1. The compressed value is 0010 (2 in hexadecimal notation). Also in this cycle, a new memory read address 61 is given, and data is read from the memory. The read data 0111 (7 in hexadecimal notation) is stored in the read data register 3 and output to the parallel input LFSR1.

Similarly, in the second cycle of compression, the read data 0111 is selected by the input selectors SEL to SEL4 and compressed by the parallel input LFSR1. In this case, the compressed value is 1110 (E in hexadecimal notation). Also,
Also in this cycle, a new memory read address 61 is given, and data is continuously read from the memory. The read data 1011 (B in hexadecimal notation) is stored in the read data register 3 and output to the parallel input LFSR1.

From the first cycle to the thirty-second cycle of compression, the same operation is performed except that the applied memory read address is different. If all the data read from the memory is correct, the signature to be obtained is obtained in the 32nd cycle of compression, and becomes 0011 (3 in hexadecimal notation).

When the compression cycle (up to 32 cycles) is completed, the 33rd cycle becomes the determination cycle. The test control signal 12 is the last cycle (last compression cycle)
And becomes 1 in synchronization with the inverted clock.
The input selectors SEL1 to SEL4 are expected signatures 21 (E1, E2, E
3, E4), and the feedback information selector SEL0 selects the output of the last-stage register S4. That is, in the judgment cycle, all the two-input exclusive OR gates XOR1 to XO
The first input of R4 is the output of the previous register (the last register S4 in the first register S1),
Is input with an expected signature 21 (E1, E2, E3, E4). In each of the two-input exclusive-OR gates XOR1 to XOR4, the value stored in each stage of the registers S1 to S4 and the expected signature are input. Expected signature 21 of storage register 2 (E1, E
2, E3, E4).

However, the register S of the n-th stage (n = 1 to 4)
The expected signature En and the output of the register Sn-1 of the preceding stage (however, the last stage when n = 1) are input to the two-input exclusive OR gate XORn connected to the input of n, so that the expected signature is obtained. As can be seen from the above table, the storage register 2 stores data obtained by circulating the expected signature 0011 (3 in hexadecimal notation) one bit to the right (or three bits to the left). In this embodiment, the stored data is 1
001 (9 in hexadecimal notation).

Therefore, each of the two-input exclusive OR gates
XOR1 to XOR4 output 0 if the corresponding bits of the compressed signature match the corresponding bits of the expected signature, and output 1 if they do not match, and store the comparison result in a register at the subsequent stage. The comparison result is input to the diagnostic register 7 and the correctness / incorrectness judgment circuit 8 as the output 11 of the two-input exclusive OR gates XOR1 to XOR4.

The diagnostic register 7 uses the test control signal 12 as a write enable signal, and outputs the outputs 1 of the two-input exclusive OR gates XOR1 to XOR4 in this comparison / determination cycle.
1 is stored as the determination result and output to the output 71. If all the values of the outputs 11 of the two-input exclusive OR gate are 0 in the comparison judgment cycle, the correctness judgment circuit 8 outputs 1 assuming that the memory is normal.
If there is an output of a two-input exclusive OR gate having the value of
The memory outputs 0 because it is not normal. This correct / incorrect judgment circuit 8 can be realized by a four-input NOR gate to which the output 11 of the two-input exclusive OR gate is input as shown in FIG. However, as shown in Table 1, in the nineteenth cycle of the compression, as can be seen from the output 11 of the two-input exclusive OR gate, that is, the values of the registers in each stage are all 0, Is valid only in the comparison determination cycle.

Therefore, conventionally, since the obtained compression values were compared using the ALU, complicated control by a microprogram was required. However, in this embodiment,
A parallel input LF that performs data compression by only simple control of providing a test control signal in the comparison / determination cycle
Since it is possible to compare the compressed signature with the expected signature by using SR1, it is not necessary to separately provide a comparing means for performing the comparison, and the on-chip circuit can be provided with only a small amount of hardware (feedback information SEL0 and input selectors SEL1 to SEL4). It is possible to realize a memory test circuit that can be easily implemented.

In this embodiment, the output 31 of the read data register 3 is input to the parallel input LFSR1 to compress the data. However, if a control signal and some hardware are added to the parallel input LFSR1, Since the parallel input LFSR1 can be used as a read data register during normal operation and as a parallel input LFSR during a memory test, hardware can be reduced in this case.

The expected signature storage register 2 needs to store data obtained by circulating the expected signature one bit to the right (or circulating three bits to the left). A similar effect can be obtained by adopting a rotator-like configuration in which the input selectors SEL1 to SEL4 circulate the expected signature output from the expected signature storage memory 2 rightward by one bit (or circulate leftward by three bits) without performing the above operation. Having.

Further, in this embodiment, the parallel input LFSR1
Is 1010 (A in hexadecimal notation), but is not necessarily limited to this value and can take any value. In this case, a correct test can be performed by storing the expected signature corresponding to the initial value.

In addition, in this embodiment, the parallel input LFSR
1 was connected to the memory, and the test was performed. The output of the internal function block was connected to the parallel input LFSR1, and the same input sequence as that for which the expected compression value was obtained was given. Then, by comparing the obtained compression value with the expected compression value, a test of the internal function block can be similarly performed.

(Second Embodiment) Next, a second embodiment, specifically, a test circuit of a plurality of semiconductor integrated circuits connected to a common data bus will be described with reference to FIG.

FIG. 4 is an overall configuration diagram of a test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention. 1 is different from FIG. 1 in that a data bus 14 is provided, and the input selector shown in FIG.
Two-input exclusive-OR gate XO directly without going through SEL1 to SEL4
A data bus 14 is connected to second inputs of R1 to XOR4, and a first memory 9a and a second memory 9b, which are semiconductor integrated circuits to be tested, are connected to the data bus 14.
And the expected signature storage register 2 are connected to each other, and the contents stored in the memories 9a, 9b and the expected signature storage register 2 are stored in the data bus 1 respectively.
Output buffers 9d, 9e, and 2c for outputting the test control signal 12 and data output from the output buffers 9d, 9e, and 2c to the data bus 14 are provided to an external input. That is, the control for designating any one of the output buffers is performed based on the specified memory designation signal. Note that the expected signature in the expected signature storage register 2 is stored in advance,
It is separately input from the outside via the data bus 14.

That is, in this embodiment, the input selecting means
Instead of the input selectors SEL1 to SEL4 of FIG.
a, 9b and a control circuit 10 for controlling the output buffers 9d, 9e, 2c built in the expected signature storage register 2.
It consists of. All the components of the circuit shown in FIG. 4 are arranged on the same substrate.

Next, a description will be given of data compression and comparison with expected signatures and determination of correctness in this embodiment.

For simplicity, it is assumed that the memories 9a and 9b are connected to the same data bus, have the same structure, and have the same memory capacity as a data array of a two-way set associative cache memory. The data written in the memories 9a and 9b are the same,
An expected signature when this data is read in a certain reading order is stored in the expected signature storage register 2.

First, the parallel input LFSR 1a is initialized (initial value setting), and then reading of the first memory 9a and compression of read data are performed. In the compression cycle of the first memory 9a, an output enable signal to the data bus 14 is output from the control circuit 10 to the first memory 9a, and read data of the first memory 9a is output to the data bus 14. . Parallel input LFSR1a
Inputs data on the data bus 14 and compresses the data. The order of reading from the first memory 9a is the same as when the expected signature is obtained, and the compression cycle is continued until reading of all the words is completed.

When the compression cycle of the first memory 9a is completed, a signature required for the parallel input LFSR1a is obtained.

Next, the operation proceeds to the comparison / determination cycle of the first memory 9a. The test control signal 12 becomes 1 in the second half of the previous cycle (last compression cycle) in synchronization with the inverted clock, and the feedback information selector SEL0 selects the output of the register S4 at the last stage. The control circuit 10
Outputs an output enable signal to the data bus 14 to the expected signature storage register 2, and outputs the expected signature to the data bus 14.

The data on the data bus 14 is input to each of the two-input exclusive OR gates XOR1 to XO of the parallel input LFSR1a.
It is provided to a second input of R4. In each of the two-input exclusive OR gates XOR1 to XOR4, an exclusive OR operation (comparison) between the value stored in each stage of the registers S1 to S4 and the expected signature 21 of the expected signature storage memory 2 is performed. And the comparison result is output from each of the two-input exclusive OR gates XOR1 to XOR1 to
The signal is output to the output 11 of the XOR 4 and is input to the diagnostic register 7 and the correct / incorrect judgment circuit 8.

The diagnostic register 7 outputs the output 11 of the two-input exclusive OR gate XOR1 to XOR4 in the comparison / determination cycle to the first
Is stored in the field assigned to the determination result in the memory 9a, and is output to the output 71.

If the outputs 11 of all the two-input exclusive-OR gates XOR1 to XOR4 are 0 in the judgment cycle, the correct / incorrect judgment circuit 8 determines that the first memory 9a is normal and outputs 1. If there is at least one output having a value of 1, the first memory 9a outputs 0 as not normal.

Next, reading of the second memory 9b and compression of the read data are performed. However, the first memory 9
As in the case of a, it is necessary to first initialize the parallel input LFSR1a. Subsequently, reading of the second memory 9b and compression of the read data are performed. The difference from the compression cycle of the first memory 9a is that an output enable signal to the data bus 14 is output from the control circuit 10 to the second memory 9b, and the read data of the second memory 9b is sent to the data bus 14. Are output only, and the reading order specified by the address 62 is the same as that of the first memory 9.
Same as a. If the memories 9a and 9b are normal, the data to be read is the same.

The parallel input LFSR1a is connected to the data bus 14
Input the above data and compress it. The compression cycle is continued until all the words have been read.

When the compression cycle for the second memory 9b is completed, a signature required for the parallel input LFSR1a is obtained. Here, since the data written in the first memory 9a and the data written in the second memory 9b are the same and the reading order is the same, if the correct data is read, the same signature is used in the memory 9a and the memory 9b. Is obtained.

Next, the operation proceeds to the comparison / determination cycle of the second memory 9b. As in the case of the first memory 9a, the test control signal 12 becomes 1 in synchronization with the inverted clock in the latter half of the previous cycle (last compression cycle), and the expected signature output from the expected signature storage register 2 21 is input to the data bus 14 and input to the parallel input LFSR1a, so that the expected signature 21 is compared with the compression signature.

The diagnostic register 7 outputs the output 11 of the two-input exclusive OR gate XOR1 to XOR4 in the comparison / determination cycle to the second
In the field assigned to the correctness judgment result of the memory 9b, and outputs the content to the output 71.

The correct / incorrect judgment circuit 8 includes a first memory 9
As in the case of a, if the outputs 11 of all the two-input exclusive OR gates XOR1 to XOR4 are 0 in the determination cycle, the second memory 9b outputs 1 as normal and
If at least one output has a value of 0, the second memory 9b
Outputs 0 as not normal.

As described above, each of the memories 9a and 9b
By executing both the cycles of data compression and comparison determination for the first memory 9a and the second memory 9b connected to the common data bus 14, a test can be performed.

Although the memories 9a and 9b have the same structure and the same memory capacity, they may have different capacities or different data may be written.
Further, two or more memories may be connected to the data bus 14. In these cases, the signatures obtained by compression for each memory are different.Therefore, the expected signatures corresponding to the respective memories are obtained, or the signatures are obtained by reading all the memories, and this and the expected signatures are obtained. By comparing, memories of various configurations connected to the data bus can be tested. When the expected signature storage register 2 stores a plurality of expected signatures, it is necessary to input an address (not shown) output from the control circuit 10 to the storage register 2.

(Third Embodiment) FIG. 5 shows a test circuit for a semiconductor integrated circuit according to a third embodiment of the present invention. In this embodiment, two data buses are provided, and one or a plurality of semiconductor integrated circuits, specifically, an arithmetic unit (internal functional block) or a memory are connected to each data bus. Hereinafter, the configuration of the test circuit of FIG. 5 will be described. still,
Portions having the same configuration as the test circuit of FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. Only different portions will be described.

In FIG. 5, 14a and 14b are data buses, respectively. The first input of each of the two-input exclusive OR gates XOR1 to XOR4 of the parallel input LFSR1c is connected to one data bus 14a, and the second input is connected to the other data bus 14
b. In addition, each output side of the three registers S1 to S3 except the register S4 of the last stage of the parallel input LFSR1c and the output side of the feedback information selector SEL0 are:
Output buffers 1d, 1e, 1f, 1g, 1h, 1
i, 1j, 1k, the two data buses 14
a, 14b. The one data bus 14a
Are connected to a first memory 9a, which is a memory under test, an arithmetic unit (internal functional block) 17 such as a multiplier or an adder, which is a semiconductor integrated circuit to be tested, and an expected signature storage register 2a. . Similarly, a second memory 9b, which is a semiconductor integrated circuit under test, and an expected signature storage register 2b are connected to the other data bus 14b. Each expected signature storage register 2a, 2b has an output buffer 2e, 2d. The control circuit 10 controls each of the output buffers 1d to 1k, 2d, 2e, 9d, and 9e to allow only one data to be output to the data buses 14a and 14b, and outputs the test control signal 12. Further, the control circuit 10 controls the expected signature storage register 2a connected to the one data bus 14b, and stores two expected signatures to be stored in the storage register 2a, namely, the expected signature for the memory 9a and the expected signature for the arithmetic unit 17. The expected signature is stored in a predetermined storage location, and the expected signature storage register 2b connected to the other data bus 14b is controlled to store the expected signature for the memory 9a to be stored in the storage register 2b in a predetermined storage location. Store in place. All the components that make up the test circuit of FIG. 5 are arranged on the same substrate.

With the above configuration, in the test circuit of FIG. 5, for example, when the test of the first memory 9a is performed,
Each bit of the 4-bit data read from the first memory 9a is converted into a two-input exclusive OR gate XOR1 to XOR4 of the parallel input LFSR1c via one data bus 14a.
Of the three registers S1 to S3 except the last register S4 and the output of the feedback information selector SEL0, that is, the parallel input LFSR1
By inputting the internal information of c to the second input of the next two-input exclusive OR gates XOR1 to XOR4 via the other data bus 14b, the data can be compressed.

FIG. 6 shows a parallel input LFSR in this embodiment.
Comparison of the compressed signature with 1c and the expected signature,
And a timing chart for explaining the determination of correctness.
Hereinafter, a test of the memory by the test circuit of FIG. 5 will be described with reference to FIGS. For simplicity of explanation,
It is assumed that the first and second memories 9a and 9b have the same configuration and the same memory capacity, and that the written data is the same. The control signals output from the control circuit 10 to the memories 9a and 9b, the expected signature storage registers 2a and 2b, and the parallel input LFSR1c in the test start cycle, the compression cycle, and the comparison determination cycle are as shown in the following table.

[0104]

[Table 2] First, the parallel input LFSR1c is initialized, that is, an initial value is set. Subsequently, in the compression cycle of the data read from the first memory 9a, one data bus 14a
Is output from the control circuit 10 to the output buffer 9e of the first memory 9a, so that the data read from the first memory 9a is output to the data bus 14a. Further, since the output enable signal to the other data bus 14b is output from the control circuit 10 to the four output buffers 1d to 1g of the parallel input LFSR1c, the internal information of the parallel input LFSR1c, that is, the registers S1 to S3
Each output of the feedback information selector SEL0 is output to the other data bus 14b. Since the test control signal 12 is 0 in the test start cycle and the compression cycle, in the parallel input LFSR1c, the feedback information selector SEL0 selects the output of the two-input exclusive OR gate XOR0 as feedback information. The output of the two-input exclusive OR gate XOR0 is input to the first bit of 14b, and the outputs of the registers S1, S2, and S3 are input to the second, third, and fourth bits, respectively.

In each of the two-input exclusive-OR gates XOR1 to XOR4 of the parallel input LFSR1c, the data of the data bus 14a, that is, the data Ib1 to Ib4 read from the first memory 9a are input to the first input, respectively. The data of the data bus 14b, that is, the internal information of the parallel input LFSR1c is input to two inputs, and these exclusive OR gates XOR1 to XOR4 perform these exclusive OR operations. Each operation result is stored in the registers S1 to S4 in synchronization with the clock 13. As described above, the first memory 9 using the parallel input LFSR1c
The data read from a is compressed.

The order of reading data from the first memory 9a is the same as the order of reading data when obtaining the expected signature. The compression cycle is continued until all data is read from the first memory 9a, and when the reading and compression of the last data are completed, the compression signature to be obtained is obtained in the parallel input LFSR1c.

Next, in the cycle for comparing the compression signature of the first memory 9a with the expected signature, the test control signal 12 becomes 1 in the second half of the last compression cycle in synchronization with the inverted clock. The information selector SEL0 selects the output of the register S4 at the last stage, so that the parallel input LFSR1c outputs the outputs of the registers S1 to S4 at each stage, that is, the obtained compression signature to the other data bus 14b. One data bus 1
An output enable signal to the expected signature storage register 2a is output from the control circuit 10 to the expected signature storage register 2a.
The expected signature stored in is output.

In each of the two-input exclusive OR gates XOR1 to XOR4 of the parallel input LFSR1c, the data of the data bus 14a, that is, the expected signature is input to the first input, and
The data of the data bus 14b, that is, the compression signature is input to the input, and these exclusive OR gates XOR1 to XOR4 perform these exclusive OR operations. After each operation result is output to the output 11 of each of the exclusive OR gates XOR1 to XOR4, it is input to the diagnosis register 7 and the right / wrong judgment circuit 8.

The diagnostic register 7 stores the respective outputs 11 of the two-input exclusive-OR gates XOR1 to XOR4 in the comparison / determination cycle in a field of the first memory 9a allocated as a storage location of the determination result. At the same time, the judgment result is output to the outside. In addition, the correct / incorrect judgment circuit 8 includes two-input exclusive OR gates XOR1 to XO in the comparison judgment cycle.
If each output 11 of R4 is 0, the first memory 9a
Outputs a value “1” meaning normal, and if any one of the outputs 11 has a value of 1, the first memory 9 a
Outputs a value of "0" meaning that it is not normal.

Thereafter, the data 1a1 to Ia4 are read from the second memory 9b, the read data is compressed, and the compression signature is compared with the expected signature. Since these operations are the same as those of the test for the first memory 9a, the description is omitted.

In the above description of the present embodiment, it is assumed that the two memories 9a and 9b have the same configuration and the same memory capacity. However, they may have different capacities, and different data may be stored. It may be written. Data bus 1
A plurality of memories may be connected to 4a and 14b, respectively. When different data is written in each memory, the expected signature storage register 2 corresponding to each memory is written.
a and 2b store different expected signatures. When each of the expected signature storage registers 2a and 2b has a plurality of expected signatures, it is necessary to generate an address signal designating the expected signature from the control circuit 10 and input this signal to the expected signature storage registers 2a and 2b. is there. When only one expected signature storage register is provided, data is sequentially read from a plurality of memories provided, a compression signature of a series of output sequences is obtained, and the obtained compression signature is compared with the expected signature.

Next, the features of this embodiment will be described. In the present embodiment, for example, when testing the first memory 9a, as shown in FIG.
“1001,” “1001,” “1111,” “001”
0 ”... Of the parallel input LFSR 1 c (that is, data that differs in each cycle) is sequentially transmitted to the other data bus 1.
4b, the respective data are sequentially written to the second memory 9b connected to the other data bus 14b (at the time of testing the second memory 9b, the internal information of the parallel input LFSR1c is , One data bus 1
The data is sequentially written to the first memory 9a via the memory 4a and input to the arithmetic unit 17 as an arithmetic operand. Therefore, prior to testing the second memory 9b,
There is no need to connect a data generating means for writing data to the memory 9b of the data bus 14a. In this embodiment, the first memory 9a and the second memory 9b have the same configuration and the same capacity.
It is possible to write the data to the second memory 9b concurrently with the compression of the data read from a.

Further, the first signal using the parallel input LFSR1c
In addition to the test of the second memories 9a and 9b, if the two memories 9a and 9b have the same capacity and the same data is written in the addresses corresponding to each other, the data is stored in the first memory 9a. The input data and the data stored in the second memory 9b are respectively input to the two-input exclusive OR gate of the parallel input LFSR1c via the data buses 14a and 14b.
XOR1 to XOR4 are input to this 2-input exclusive OR gate
At XOR1 to XOR4, the input data are compared. As a result of this comparison, if both data match, 2
Since the outputs 11 of the input exclusive OR gates XOR1 to XOR4 are all 0, the correctness judgment circuit 8 outputs a value "1" indicating that both memories 9a and 9b are normal. On the other hand, if the two data do not match, any one of the outputs 11 of the two-input exclusive-OR gates XOR1 to XOR4 is 1, so that the correctness judgment circuit 8 determines whether one of the two memories 9a and 9b or A value “0” indicating that both are abnormal is output. Therefore, whether the memories 9a and 9b are normal or abnormal is determined based on the value of the output of the correctness determination circuit 8. Therefore, by reading the data of both memories 9a and 9b one by one at the same time and comparing these read data by the two-input exclusive OR gates XOR1 to XOR4 of the parallel input LFSR1c, the two memories 9a and 9b are read. Can be tested.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described. The present embodiment has a configuration in which a little hardware is added to the parallel input LFSR and the comparison / determination result is output outside the chip. FIG. 7 is an overall view of a test circuit of a semiconductor integrated circuit according to the fourth embodiment.

The difference between the second embodiment and FIG. 4 is that the feedback information selector (feedback information generation means) SEL0 is a three-input selector so that the parallel input LFSR 1b is connected to the scan path in the chip. In addition to the output of the register S4 and the output of the two-input exclusive OR gate (feedback information generating means) XOR0, the scan-in signal 15 is input, and the output of the register S4 at the last stage is output to the scan path as the scan-out signal 16. The connection and the respective registers S1 to S1 of the parallel input LFSR1b
S4 is provided with a zero output circuit 9c as zero output means for giving 0 as parallel data, and an output buffer 9f is arranged in the zero output circuit 9c to control the data output from the zero output circuit 9c to the data bus 14 by the control circuit 10. This is a configuration in which control is performed by

Therefore, in the present embodiment, the zero output circuit 9c is connected to the data bus 14 during the scan operation.
Is output and the value of 0 is input to the two-input exclusive OR gate XO.
Given to the second inputs of R1 to XOR4,
Since the values of 1 to S4 themselves shift right by one bit in accordance with the clock, the comparison result of the parallel input LFSR1b is output as a scan-out signal. Therefore, the comparison result can be observed outside the chip.

In addition, not only in the scan-out of the comparison result but also in the scan operation, the signal provided as the scan-in signal is selected by the three-input selector SEL0 and is sequentially stored in the parallel input LFSR1b in accordance with the clock. The initial value (seed) at the time of data compression is used as a scan-in signal, and this scan-in signal is scanned in at the beginning of the test of the semiconductor integrated circuit. Here, if the capacities of the plurality of memories to be tested are different from each other, or the written data is different from each other even if the capacities are the same, an initial value for obtaining the same compression signature is obtained in advance. This initial value is scanned in for each memory test. Therefore, self-diagnosis of all memories is possible only by having one expected signature.

As described above, in the present embodiment, the functions of compression of the output sequence, comparison of the compression value with the expected value, and the function as the scan (shift) register can be realized by using the same parallel input LFSR. .

In the above description, the signal 11 output to the diagnostic register 7 and the correct / incorrect judgment circuit 8 is the output of the two-input exclusive OR gate XOR1, XOR2, XOR3, XOR4. By performing a shift operation in the comparison determination cycle, the output of the two-input exclusive OR gate, which is the comparison result, is stored in the register of each stage, and the output of these registers is stored in the diagnosis register 7 as the correctness determination result The correct / incorrect judgment circuit 8 determines that all values of the output 11 of the register of each stage are 0.
If so, the memory is determined to be normal and 1 is output. If at least one has a value of 1, the memory is determined to be abnormal and 0 is output.
Is output, the correctness can be correctly determined.

The present invention is not limited to the above embodiments. That is, in a memory test, if data is fixed and the reading order is always the same as in ROM and PLA, the expected signature is uniquely determined. Even in the RAM, the data to be written and the reading order for the test are determined. If they are always the same, they are uniquely determined in the same manner. Therefore, even in the case of a programmable ROM, PLA, or the like, a test can be performed by this test circuit by rewriting the expected signature at the time of programming. Also, the parallel input LFS
R is arranged on the same chip as the memory under test, but is not limited to this.

[0121]

As described above, according to the test circuit and the test method for a semiconductor integrated circuit of the present invention, the compression signature obtained by the repetition of the compression is compared with the expected signature. The comparison means
As an operation circuit originally provided in the test circuit for compressing parallel data, the data can be obtained by using, for example, a parallel input LFSR for compressing an output sequence of data from a semiconductor integrated circuit. Since the compression signature was compared with the expected signature, ALU was used as a comparison means as in the past.
Compared to using, the test time is not extended,
The normality of the semiconductor integrated circuit (memory or internal function block) can be determined with a small amount of hardware.

In addition, since simple control that does not require control by a microprogram for testing a semiconductor integrated circuit is possible, these circuits can be mounted on a chip with a small area, and an automatic test for a built-in chip can be performed. Has an effect that it can be configured relatively easily.

Further, for comparison with the expected signature, A
Since it is not necessary to use an LU, when testing one memory, there is no need to connect the parallel input LFSR to the data bus, and the test circuit can be flexibly arranged on the chip, and the internal functions not connected to the data bus can be used. There is an advantage that the block can be easily tested.

In particular, according to the test circuit of the semiconductor integrated circuit of the present invention, the two data buses connected to the two data buses.
By examining the output of the input exclusive OR gate,
18. A more flexible automatic test is possible because not only data compression and comparison on one data bus but also data comparison between two data buses can be performed using the same parallel input LFSR. According to the test circuit of the semiconductor integrated circuit of the described invention, even when observing the correctness of the output series of the semiconductor integrated circuit outside the chip, the information to be scanned out is not the obtained signature but the determination result. A large number of expected signatures can be managed for each type of semiconductor integrated circuit, and it is not necessary to make a comparison using the same, and even a user who does not know the expected signature can easily perform a correct / incorrect test of the semiconductor integrated circuit. .

Furthermore, according to the semiconductor integrated circuit test method of the present invention, the internal information of the parallel input LFSR can be input to the semiconductor integrated circuit as test data while the semiconductor integrated circuit is being tested. Therefore, the test data generating means can be eliminated, and the cycle of storing the test data in the semiconductor integrated circuit can be eliminated.

In addition, according to the semiconductor integrated circuit test method of the present invention, the parallel input linear feedback shift register is controlled so that the expected compression values of the plurality of semiconductor integrated circuits are the same. An initial value to be input is obtained in advance for each semiconductor integrated circuit, and each initial value is scanned into the parallel input linear feedback shift register at the start of the test, so that the normality of a plurality of semiconductor integrated circuits is tested. Also, only one expected compression value is required, and a flexible automatic test can be performed with a small area.

[Brief description of the drawings]

FIG. 1 is an overall schematic configuration diagram of a test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a specific test circuit of a semiconductor integrated circuit using a parallel input LFSR in the first embodiment.

FIG. 3 is a timing chart for explaining a comparison between data compression and an expected signature in the first embodiment.

FIG. 4 is a specific configuration diagram of a test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 5 is a specific configuration diagram of a test circuit of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 is a timing chart for explaining a comparison between data compression and an expected signature in the third embodiment.

FIG. 7 is a specific configuration diagram of a test circuit of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

[Explanation of symbols]

1, 1a, 1b, 1c Parallel input linear feedback shift register (compact test circuit) 1d, 1d to 1k, 2c, 9d, 9e Output buffer S1 to S4 Register XOR1 to XOR4 Two-input exclusive OR gate (arithmetic circuit) XOR0 Feedback information generation means SEL0 Feedback information selection means 2, 2a, 2b Expected signature storage register (expected compressed value storage means) 7 Diagnostic register 8 Correct / incorrect judgment circuit SEL1-SEL4 2-input multiplexer (input selection means) 9a, 9b Memory (semiconductor integrated circuit) Circuit) 10 control circuit (control means) 14a one data bus 14b the other data bus 17 arithmetic unit (internal functional block)
(Semiconductor integrated circuit) 18 Information collecting means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/277 G01R 31/28-31/30 G11C 29/00

Claims (24)

(57) [Claims] 1. A test circuit for a semiconductor integrated circuit to which a plurality of parallel data are sequentially inputted from a semiconductor integrated circuit and which uses a compact test circuit for compressing the inputted plurality of parallel data, wherein an expected compression value is stored. An expected compression value storage means, originally provided in a test circuit, for compressing the parallel data;
An arithmetic circuit, and an information collecting means for giving the compressed value obtained by the compression by the compact test circuit and the expected compressed value of the expected compressed value storage means to the arithmetic circuit, the obtained compressed value and the expected value. A test circuit for a semiconductor integrated circuit, wherein a comparison means for comparing a compression value is also used by the arithmetic circuit originally provided. 2. The test circuit for a semiconductor integrated circuit according to claim 1, wherein said compact test circuit comprises a parallel input linear feedback shift register. 3. The parallel-input linear feedback shift register includes a plurality of registers, a plurality of two-input exclusive OR gates arranged in front of each of the registers, an output of a last-stage register and an intermediate stage. Feedback information generating means for generating feedback information from the output of the register. The output of the two-input exclusive OR gate at the preceding stage is input to each of the registers, and the feedback information generating means is located at the preceding stage of the first register. The first input of each of the two-input exclusive-OR gates except the input exclusive-OR gate is supplied with the output of the preceding register, and the two-input exclusive-OR gate located before the first-stage register is provided. The output of the feedback information selecting means is given to a first input of the parallel input linear feedback system. A plurality of two-input exclusive OR gates provided in the parallel register, and the information collecting means controls one of an output of the feedback information generating means of the parallel input linear feedback shift register and an output of the last register. A feedback information selecting means for selecting by a signal, and controlling one of parallel data and an expected compression value of an expected compression value storage means as data to be supplied to a second input of each register of the parallel input linear feedback shift register. 3. The test circuit for a semiconductor integrated circuit according to claim 2, comprising input selection means for selecting by a signal. 4. The semiconductor integrated circuit to be tested is a memory.
A test circuit for a semiconductor integrated circuit as described in the above. 5. The test circuit according to claim 1, wherein the semiconductor integrated circuit to be tested is an internal function block. 6. The test circuit for a semiconductor integrated circuit according to claim 3, wherein said input selection means is constituted by a two-input multiplexer. 7. A data bus, wherein each of the two-input exclusive-OR gates of a parallel input linear feedback shift register is directly connected to the data bus, and the semiconductor integrated circuit and expected compressed value storage means are provided. Are connected via an output buffer, respectively, and the input selection means is configured to output any one of the semiconductor integrated circuit and the expected compressed value storage means to the data bus. 4. The test circuit for a semiconductor integrated circuit according to claim 3, further comprising a control circuit for controlling each of the output buffers. 8. The test circuit according to claim 7, wherein a plurality of semiconductor integrated circuits are connected to the data bus. 9. An input selector selects parallel data from a semiconductor integrated circuit in a compression cycle for compressing parallel data from the semiconductor integrated circuit in accordance with a control signal, and compares the obtained compressed value with an expected compressed value. 8. The test circuit for a semiconductor integrated circuit according to claim 3, wherein an expected compression value of the expected compression value storage means is selected at the time of the determination. 10. The semiconductor integrated circuit according to claim 3, wherein the expected compression value storage means stores the expected compression value by rotating only one bit in advance in the shift direction of the parallel input linear feedback shift register. Test circuit. 11. A parallel input linear feedback shift register comprising one data bus, comprising: an output buffer for connecting an output of each register and an output of feedback information selecting means to the data bus, respectively; A first input of an OR gate is directly connected to the data bus, and is connected to a first input of each two-input exclusive OR gate except for a two-input exclusive OR gate located in front of the first stage register. Are each provided with the output of the preceding stage register via the output buffer and the data bus, and the first input of the two-input exclusive OR gate located before the first stage register is provided with the feedback information selecting means. 4. The semiconductor integrated circuit according to claim 3, wherein an output of said semiconductor integrated circuit is provided through said output buffer and said data bus. Test circuit. 12. The parallel input linear feedback shift register further comprising another data bus, the parallel input linear feedback shift register further comprising another output buffer for connecting an output of each register and an output of the feedback information selecting means to the other data bus, respectively. , The second input of each two-input exclusive OR gate is directly connected to the data bus, and each of the two input exclusive OR gates except the two-input exclusive OR gate located before the first register
The second input of the input exclusive OR gate is supplied with the output of the preceding register through the other output buffer and the other data bus, respectively. 12. The semiconductor integrated circuit according to claim 11, wherein an output of said feedback information selecting means is given to a second input of the logical OR gate via said another output buffer and said another data bus. Circuit test circuit. 13. A semiconductor integrated circuit and an expected compression value storage means are connected to the data bus and the other data bus, respectively, wherein each of the semiconductor integrated circuit and the expected compression value storage means has an output buffer built therein. The input selection means uses one of the two data buses for compression of the parallel input linear feedback shift register while providing the other data bus with the semiconductor integrated circuit connected to the other data bus and the expected compression value. A control circuit for controlling each output buffer included in the semiconductor integrated circuit and the expected compressed value storage means, and each output buffer included in the parallel input linear feedback shift register so as to output data from any of the storage means; 13. The test circuit for a semiconductor integrated circuit according to claim 12, comprising: 14. A data bus and another data bus are each connected to a semiconductor integrated circuit, said semiconductor integrated circuit has an output buffer built-in, and input selection means is connected to one of the data buses. Output data from the semiconductor integrated circuit connected to the data bus, output data from the semiconductor integrated circuit connected to the other data bus to the other data bus, and output data to the two data buses. Control for controlling an output buffer incorporated in the semiconductor integrated circuit and each output buffer incorporated in the parallel input linear feedback shift register so that competitors are compared by each two-input exclusive OR gate of the parallel input linear feedback shift register. 13. The test circuit for a semiconductor integrated circuit according to claim 12, comprising a circuit. 15. An output of each two-input exclusive OR gate of the parallel input linear feedback shift register,
8. The test circuit for a semiconductor integrated circuit according to claim 3, further comprising a right / wrong determining means for determining whether the semiconductor integrated circuit is correct or not based on the value of each input and outputting a result of the determination. 16. An output of each two-input exclusive OR gate of the parallel input linear feedback shift register,
8. The test circuit for a semiconductor integrated circuit according to claim 3, further comprising a diagnostic register for storing the input content and outputting the input content. 17. The feedback information selection means receives scan-in information, and the feedback information selection means selects the scan-in information during a scan operation. An output is connected to a scan path as scan-out information, and each register of the parallel input linear feedback shift register is provided with zero output means for giving zero as a parallel data at the time of a scan operation. 8. The test circuit for a semiconductor integrated circuit according to claim 7, wherein outputs of all registers of the register are configured to be observed. 18. A true / false judgment for inputting a comparison result of both data at each two-input exclusive OR gate of a parallel input linear feedback shift register, determining whether the two data match or not, and outputting the determination result. 15. The test circuit for a semiconductor integrated circuit according to claim 14, further comprising means. 19. At the same time as sequentially reading data from the semiconductor integrated circuit according to the same address sequence as when the expected compression value obtained in advance is generated, each read data is sequentially transferred to each of the parallel input linear feedback shift registers in parallel. By repeatedly inputting and shifting, the compression of the parallel data is repeated in sequence, and the output of each register at the time of compressing the last parallel data is obtained as a compressed value of the parallel data. The output of the last-stage register is given to the first input of the two-input exclusive-OR gate located at the preceding stage, and the first input of the two-input exclusive-OR gate located at the preceding stage of each register except the first-stage register is provided. Of the parallel input linear feedback shift register.
The expected compression value is input to the second input of the input exclusive OR gate, and each of the two input exclusive OR gates performs a comparison operation between corresponding bits of the parallel data compression value and the expected compression value,
A test method for a semiconductor integrated circuit, wherein the normality of the semiconductor integrated circuit is tested based on a result of the comparison operation. 20. One of the plurality of semiconductor integrated circuits is connected to one data bus via an output buffer, and data is sequentially read from the connected semiconductor integrated circuits via the data bus. After performing compression of each read data, calculation of a compression value, and comparison between the obtained compression value and an expected compression value, another one of the plurality of semiconductor integrated circuits is output via an output buffer. Connected to one data bus, sequentially reads data from the connected semiconductor integrated circuit via the data bus, compresses the read data, calculates a compression value, and compares the obtained compression value with the expected compression value. 20. The method for testing a semiconductor integrated circuit according to claim 19, wherein repeating the comparison is performed. 21. When repeatedly compressing data from a semiconductor integrated circuit by a parallel input linear feedback shift register, each time the data is compressed, a register other than the last stage register of the parallel input linear feedback shift register is used. 20. The test of a semiconductor integrated circuit according to claim 19, wherein the intermediate compression information including the output and feedback information of the semiconductor integrated circuit is input or stored as test data of the semiconductor integrated circuit connected to the data bus via the data bus. Method. 22. The method according to claim 19, wherein an initial value is scanned in the parallel input linear feedback shift register before starting the test. 23. The semiconductor integrated circuit under test is a plurality of memories, each of which has different capacity, written data or written data, and is scanned into a parallel input linear feedback shift register. 23. The apparatus according to claim 22, wherein the initial value is a predetermined initial value obtained in advance so that each expected compression value obtained by reading data from each of the memories has the same value.
The test method of the semiconductor integrated circuit described in the above. 24. The semiconductor integrated circuit under test is a plurality of internal function blocks, each of which has a different function or input sequence, and is scanned into a parallel input linear feedback shift register. 23. The semiconductor integrated circuit according to claim 22, wherein the initial value is a predetermined initial value obtained in advance so that each expected compression value obtained from the output of each internal function block for each of the input sequences has the same value. How to test the circuit.