JP3178217B2 - Direct conversion receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct conversion receiver for digital radio communication.

[0002]

2. Description of the Related Art Recently, frequency shift keying (FSK: Frequency Shift Key) on a radio frequency carrier.
For example, as a receiver of a digital modulation signal such as frequency-shifting keying, a direct conversion receiver is being studied as a configuration suitable for integration into an integrated circuit.

[0003] For example, a configuration described in Japanese Patent Application Laid-Open No. 55-14701 is known. Hereinafter, a conventional FSK data demodulator will be briefly described with reference to FIG.

In FIG. 6, an FSK received signal received by an antenna 30 is amplified by a signal amplifier 31 and supplied to a mixer 32 and at the same time is supplied to a mixer 33. The signal of the local oscillator 34 is supplied to the mixer 33 through the mixer 32 and the 90-degree phase shifter 35, and down-converts the input signal by mixing with the signal of the receiver input terminal 30, and passes only the baseband signal. The I signal 38 and the Q signal 3 which pass through the low-pass filters 36 and 37, are in a quadrature phase with each other, and whose phase delay relationship is inverted by the frequency shift of the FSK signal.
Get 9. The I signal 38 and the Q signal 39 pass through amplitude limiting amplifiers 40 and 41, respectively, to obtain digital signals 42 and 43. Then, digital signals 42 and 43 are input to the D input terminal and the clock input terminal of the D flip-flop 44, and data is demodulated using the output signal 45 of the D flip-flop 44.

Next, after the output signal 45 is shaped by a low-pass filter 46, the symbol period is detected by a clock synchronizing circuit 47, and the symbol judgment circuit 48 judges the sign based on the sample at the center of the symbol in the symbol period. , A final demodulation result 49 is obtained.

[0006]

When a frequency difference occurs between the local oscillator and the transmission carrier signal, the frequency difference directly affects the frequency of the IQ baseband signal, and is accompanied by a change in the sign of the received symbol. , The frequency of the baseband signal changes. In general, since a direct conversion receiver can be easily integrated, a digital demodulation method as described in the related art is often used. In such a digital demodulation method, a baseband signal is binarized and demodulated. Perform At this time, the transmission of the IQ baseband signal is performed only at the zero crossing point due to the binarization, and since the phase information of the IQ baseband signal has been lost, the code change detection of the transmission symbol in demodulation is performed. Often causes delay. Furthermore, when performing high-speed communication, since the modulation index tends to be low, the influence of the above-described delay on the demodulation result increases, and in particular, the amount of allowable frequency deviation with respect to the local oscillator of the receiver decreases. There was a problem that.

Further, when a circuit which easily generates noise during operation of a CPU or the like operates intermittently in synchronization with a symbol period, the CPU often operates so as to operate at the time of symbol judgment by the symbol judgment means. However, there is a problem that the reception sensitivity is deteriorated due to the leakage of the operation noise to the demodulation circuit.

The present invention has been made to solve the above-mentioned problems.
By controlling the operation timing of PU, narrow band,
It is an object of the present invention to obtain a high-sensitivity direct conversion receiver compatible with high-speed digital modulation.

[0009]

In order to achieve the above-mentioned object, a first technical solution of the present invention is that a change in the frequency of the IQ baseband signal is caused by a frequency difference between a received FSK carrier and a local oscillator. If it occurs, the phase of the clock synchronization circuit is controlled in accordance with the degree of the frequency shift detected by the frequency change, the position of the determination point in the symbol determination unit in the symbol is changed, and the determination delay amount in the demodulation unit is changed. Is performed to improve the receiving sensitivity.

[0010] The second technical solution of the present invention is as follows.
When a circuit, such as a CPU, which is expected to generate noise due to the operation operates in synchronization with the data determination, the operation timing is controlled so as to operate when the influence on the symbol determination is small.

[0011]

According to the present invention, the code (symbol) judging means of the demodulator is provided with the code judging point, which is conventionally provided at the center of the symbol, behind the center.
Even if the code change point in the demodulation result moves behind the symbol due to the influence of the delay described above, accurate code determination is possible, and the reception sensitivity is improved when there is a frequency shift between the transmission carrier and the local oscillator. Can be planned.

Further, by setting the operation timing of the CPU or the like after the symbol judgment point, the influence of the operation noise is reduced and high-sensitivity reception is enabled.

Further, the present invention is to improve the receiving sensitivity by adding to the configuration of the direct conversion demodulation means.
Since both the demodulation means and the above configuration can be realized by digital signal processing, it is easy to integrate the entire demodulator into an integrated circuit, and it is possible to simultaneously reduce the size and power consumption of the receiver.

[0014]

【Example】

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram of a main part of a demodulation circuit applied to a direct conversion receiver according to a first embodiment of the present invention. In this embodiment, since the direct conversion receiver is configured, the I signal 38 and the Q signal obtained by the direct conversion described in the related art are used.
Demodulation is performed using the signal 39.

In FIG. 1, a signal amplifier 31, a mixer 32, a mixer 33, a local oscillator 34, a 90-degree phase shifter 35, and low-pass filters 36 and 37 are equivalent to those in FIG.

In FIG. 1, reference numeral 1 designates an input of the I signal 38 and the Q signal 39, and the signals 38 and 39 are inverted in phase relationship due to a sign change of a transmission signal. This is a demodulation means for detecting a change in transmission data by reversing the phase relationship. The demodulation means 1
More specifically, the amplitude limiting amplifiers 40 and 4 shown in FIG.
1 and a D flip-flop 44. Alternatively, the I signal 38 and the Q signal 39 are phase-shifted by 90 degrees by a
, And the I signal 38 and the Q signal 39 are mixed by a mixer, and the Q signal 39 and the I signal 38 are mixed by a mixer, and the sum of both mixing outputs is obtained by an arithmetic unit. Such a configuration can also be realized.

Reference numeral 2 denotes an output signal of the demodulation means 1, 3 denotes a low-pass filter for shaping the waveform of the output signal 2 of the demodulation means 1, 4 denotes frequency detection means for detecting the frequencies of the I signal 38 and the Q signal 39, 5 is an output signal of the frequency detecting means 4; 6 is a clock synchronizing means for outputting a clock signal 7 which estimates the timing of the center of the symbol by detecting a symbol change point from a code change in the output signal of the low-pass filter 3; Is a signal delay means for adding an amount of delay corresponding to the signal 5 to the clock signal 7, and 9 is a symbol for making a symbol determination from the output signal of the low-pass filter 3 using the timing of the output signal of the signal delay means 8. The determination means 10 is the final demodulation result obtained by the symbol determination means 9.

The operation of the above configuration will be described below. First, the I signal 38 and the Q signal 39 always maintain a phase difference of 90 degrees, but their phase relationship is inverted with a change in the sign of the transmission signal. The demodulation means 1 detects the phase relationship between the I signal 38 and the Q signal 39,
The sign of the transmission signal is determined. The determined demodulation result 2 is passed through a low-pass filter 3 to perform waveform shaping, and is supplied to a clock synchronization unit 6 and a symbol determination unit 9. Here, if there is a frequency difference between the carrier of the received FSK signal and the local oscillator 34, the above-mentioned I
The frequency of the baseband signal as the signal 38 and the Q signal 39 changes.

FIG. 2A shows the case where there is no frequency difference between the carrier of the received FSK signal and the local oscillator, and FIG. 2B shows the case where there is a frequency difference. ) And demodulation results (c). (D) is the frequency relationship between the received FSK signal and the output signal of the local oscillator 34.

The carrier frequency of the received FSK signal is FRF, and the oscillation frequency of the local oscillator is FLO.
The frequency shift is FD. In the case of FIG.
The frequency of the baseband signal shown in (b) becomes FD regardless of the sign change of the transmission signal shown in (b). Here, generally, the amount of delay in code detection in the demodulation means 1 is inversely proportional to FD. In this case, since the frequency of the I signal between codes is the same, the amount of delay in code detection is always substantially constant, so that the duty ratio in the demodulation result shown in demodulation result (c) is about 1/2.

FIG. 2B shows the relationship when there is a frequency difference between the received FSK signal carrier and the local oscillator. In this case, as shown in FIG.
Since there is a frequency difference therebetween, the frequency of the baseband signal shown in (b) changes to FD1 and FD2 with the sign change of the transmission signal shown in (a).

The amount of delay in code determination in the demodulation means 1 is almost inversely proportional to the frequency of the baseband signal.
As the frequency of the baseband signal changes, the amount of delay in code determination between symbols also changes. Accordingly, as shown in FIGS. 2B and 3C, when the frequency of the baseband signal is as low as FD1, the delay increases, and in extreme cases, it may reach the center of the symbol. In such a case, the symbol determination means 8
If the sign determination at the center of the symbol is performed as in the related art, it is expected that the sign determination result will have a large error.

Here, the demodulation error can be reduced by shifting the code decision point from the symbol center to the rear according to the delay amount instead of always performing the code decision at the symbol center. In the configuration of FIG. 1, the clock synchronization means 6 detects a symbol change point from a code change in the output signal of the low-pass filter 3, and estimates the timing of the center of the symbol. Then, the frequency change of the IQ baseband signals 38 and 39 is
And outputs the output signal 5 of the frequency detecting means 4 to the signal delaying means 8. Then, the signal delay unit 8 supplies the symbol determination unit 9 with a delayed signal corresponding to the output signal 5 with respect to the clock signal 7 indicating the symbol center position estimated by the clock synchronization unit 6, The code determination point of the code determination means 9 is moved to the rear of the symbol according to the degree of change in the frequency of the IQ baseband signal. That is, the symbol determination of the symbol is performed by the symbol determination point moved backward by the expected determination delay amount of the IQ baseband signals 38 and 39 according to the frequency difference between the received FSK carrier signal and the local oscillator, A final demodulation result 10 is obtained.

In the configuration described above, the frequency detecting means 4 detects the frequency difference between the received FSK carrier signal and the local oscillator, and the symbol determining means 8 shifts the symbol determination point according to the frequency difference. But,
The symbol determination point is simply a fixed amount regardless of the frequency difference,
By moving it backward, it is possible to improve the sensitivity when the frequency difference occurs. In that case, the frequency detecting means 4 and the signal delaying means 8 can be omitted.

FIG. 3 shows the result of the characteristic improvement by computer simulation assuming a demodulator having a configuration in which the frequency detection means 4 and the signal delay means 8 in FIG. 1 are omitted. In FIG. 3, the horizontal axis indicates the symbol determination position in the symbol determination means 9 assuming that one symbol is 100%, and the vertical axis indicates the BER (bit error rate) when the symbol determination based on the position is performed. BER is a bit ratio of error data in demodulated data to the total number of transmission data. Here, the frequency difference between the received FSK carrier signal and the local oscillator is changed from 0 to 3 kHz. In particular, when the frequency difference is 3 kHz, the BER becomes about 0.04 when the symbol determination position is set at the center of the symbol.
However, when the BER was set at a position of 3/4 or 75% of one symbol length, the BER was about 0.004, and a reduction in the error rate was confirmed. Since the reduction of the error rate directly leads to the improvement of the receiving sensitivity, the effect of improving the receiving sensitivity by the configuration of the present invention has been confirmed.

(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a circuit diagram of a main part of a demodulation circuit applied to a direct conversion receiver according to a second embodiment of the present invention. This embodiment is also shown in FIG.
Similarly to the above, since the configuration of the direct conversion receiver is used, demodulation is performed using the I signal 38 and the Q signal 39 obtained by the direct conversion described in the related art. Therefore, in FIG. 4, the signal amplifier 31, the mixer 32, the mixer 33, the local oscillator 34, the 90-degree phase shifter 35, and the low-pass filters 36 and 37 are equivalent to the configuration of FIG.
In FIG. 4, reference numeral 1 denotes a demodulation unit, 2 denotes an output signal of the demodulation unit 1, and 3 denotes a low-pass filter for shaping the waveform of the output signal 2 of the demodulation unit 1. The above configuration is the same as in FIG. It is.

On the other hand, 6 is a clock synchronizing means for outputting a clock signal 7 which estimates the timing of the center of the symbol by detecting a symbol change point from a code change in the output signal of the low-pass filter 3, and 9 is a low-pass filter. Symbol determination means for performing symbol determination from the output signal of the signal generator 3 using the timing of the clock signal 7; 11, an arithmetic processing means such as a CPU; and 10, a final demodulation result obtained by the symbol determination means 9.

The operation of the above configuration will be described below. The operation up to obtaining the output signal of the low-pass filter 3 in the second embodiment is the same as that in the first embodiment, and the subsequent operation will be described.

The clock synchronization means 6 includes the low-pass filter 3
, A symbol change point is detected from the code change in the output signal, and a clock signal 7 in which the timing at the center of the symbol is estimated is supplied to the symbol determination means 9. The output signal of the low-pass filter 3 is subjected to symbol determination at the center of the symbol by the symbol determination means 9 at the timing of the clock signal 7 to obtain a final demodulation result 10.

Here, when adopting a configuration in which an operation by arithmetic processing is added to the demodulation operation, the arithmetic processing means 11 may operate intermittently in synchronization with the symbol period. At this time, when the arithmetic processing means 11 is constituted by a digital circuit, the generation of noise due to the operation and the deterioration of the receiving sensitivity due to leakage to the demodulation unit often cause problems.

In this embodiment, the arithmetic processing means 11 is operated synchronously by the clock signal 7 supplied from the clock synchronizing means 6, and the operation start timing is after the symbol judgment point in the symbol judgment means 9. Things. Thus, the operation of the arithmetic processing means 11 can be performed at a timing with little influence on the symbol determination by the symbol determining means 9, and the deterioration of the receiving sensitivity due to the leakage of the operation noise of the arithmetic processing means 11 is minimized. It is assumed that.

FIG. 5 shows the result of the characteristic improvement by computer simulation assuming the demodulator having the configuration shown in FIG. In FIG. 5, the horizontal axis indicates the operation start position of the arithmetic processing unit 11 for each symbol, where one symbol is 100%, and the vertical axis is the BER at that time. In the embodiment shown in FIG. 5, since the symbol determination is set at the center of the symbol, if there is a noise generation factor before the symbol determination point, the influence of the noise is increased, and the sensitivity is degraded. I understand that. Further, by setting the operation start point of the arithmetic processing means 11 after the symbol determination point, the influence of the leaked noise is reduced.

Therefore, when it is necessary to operate circuits such as the arithmetic processing means 11 in which noise is expected to occur in synchronization with the symbol period, the operation of the arithmetic processing means 11 and the like is controlled by the clock signal 7. By performing the start, the arithmetic processing means 11 can be operated after the symbol judgment by the symbol judgment means 8, and
As described above, the reception sensitivity can be improved by a relatively simple method.

In each embodiment, the case where the modulation format of the received signal is FSK has been described.
It is obvious that the demodulation according to the present invention can be applied to a receiver using another modulation scheme by using a demodulator corresponding to another modulation scheme.

Here, in each embodiment, the case where the receiving system is the direct conversion receiving system has been described. However, if the carrier signal is an intermediate frequency signal, the demodulation of the present invention can be applied as a heterodyne demodulating system. Is clear.

[0036]

As described above, according to the present invention, even if a frequency difference occurs between the carrier of the received FSK signal and the local oscillator of the receiver, which is a major problem in direct conversion reception, the present invention is more effective. Since accurate symbol determination is possible, a demodulator that supports narrower bandwidth and higher speed FSK can be realized.

According to the present invention, in the case of a receiver incorporating arithmetic processing means such as a CPU, it is possible to reduce the influence of noise generated by the arithmetic processing means, thereby enabling more sensitive demodulation. Becomes

Further, since the components can also be realized by digital circuit elements, integration into a circuit is possible, miniaturization and cost reduction are possible, and the industrial effect is great.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a main part of a demodulation circuit applied to a direct conversion receiver according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing a demodulation operation in the embodiment.

FIG. 3 is a characteristic diagram showing an effect of improving demodulation sensitivity according to the embodiment.

FIG. 4 is a circuit diagram of a main part of a demodulation circuit applied to a direct conversion receiver according to a second embodiment of the present invention.

FIG. 5 is a characteristic diagram showing an effect of improving demodulation sensitivity according to the embodiment.

FIG. 6 is a circuit diagram showing a main part of a demodulation circuit to which an FSK demodulation method according to a conventional receiver configuration is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Demodulation means 3 Low-pass filter 4 Frequency detection means 6 Clock synchronization means 8 Signal delay means 9 Code determination means 32, 33 Mixer 34 Local oscillator 35 90-degree phase shifter 36, 37 Low-pass filter

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yasushi Tanaka 4-3-1 Tsunashima, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture Inside Matsushita Communication Industrial Co., Ltd. (56) References JP-A-3-139941 (JP, A) JP-A-6-6397 (JP, A) JP-A-3-62753 (JP, A) JP-A-4-335733 (JP, A) JP-A-64-58043 (JP, A) JP-A-5-250058 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/14

Claims (2)

(57) [Claims] 1. A demodulation means for detecting a phase relationship between each other because a phase relationship is inverted by a code change of an IQ baseband signal due to direct conversion reception, and detecting a change in transmission data by inverting the phase relationship. Clock synchronization means for detecting a symbol change point from the code change of the demodulation detection signal and outputting a clock signal in which the timing of the symbol center is estimated; and a frequency for receiving the IQ baseband signal and detecting a frequency change of the input signal Detection means, signal output means of the frequency detection means as a control signal, signal delay means for delaying the clock signal by time according to the control signal, at the timing of the output signal of the signal delay means, the demodulation detection signal Sign determination means for performing code determination, wherein the frequency detection means detects a change in frequency of the IQ baseband signal. The local oscillator detects a frequency shift with respect to the received FSK carrier frequency of the receiver local oscillator and supplies the control signal as the control signal to the signal delay means. The signal delay means divides the clock signal by 1 / according to the frequency shift.
A delay of two symbol lengths or less is supplied to the code judging means, and the code judging means makes a code judgment of the demodulation detection signal in synchronization with an output signal of the signal delaying means, whereby the frequency detecting means A direct conversion receiver that changes a delay amount of a code determination point from a symbol center estimation point by the clock signal in accordance with the frequency shift of the local oscillator detected in the above. 2. Demodulation means for detecting a phase relationship between each other because a phase relationship is inverted by a sign change of an IQ baseband signal due to direct conversion reception, and detecting a change in transmission data by inverting the phase relationship. Code determination means for determining the sign of a demodulation detection signal which is an output signal from the demodulation means; and detecting a symbol change point from a code change of the demodulation detection signal and estimating a symbol center timing. Clock synchronizing means for supplying to the means, and arithmetic processing means operating synchronously with the demodulation detection signal, wherein the arithmetic processing means uses the timing of the clock signal to determine the sign judgment point in the sign judging means. By operating intermittently later, it operates at a timing when the effect of leakage of operation noise to the demodulation unit on demodulation results is small. A direct conversion receiver that determines a code of the demodulation detection signal at a timing using the clock signal, outputs the result as a demodulation code determination result, and performs demodulation using the demodulation code determination result. .