JP3176016B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to a single power supply having a booster circuit for generating a high voltage required at the time of writing / erasing. The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art For example, a NAND type EEPROM is known as one of EEPROMs which can be programmed / erased by a single power supply (for example, Vcc = 5V). this is,
A plurality of memory cells are connected in series in such a manner that their sources and drains are shared by adjacent ones, and this is connected to a bit line as a unit. A memory cell is usually an FET-MO having a charge storage layer and a control gate stored therein.
It has an S structure. The memory cell array is integrally formed in a p-type well formed in a p-type substrate or an n-type substrate.

In an EEPROM, a voltage higher than a power supply voltage is applied to a memory cell during normal writing / erasing, and data is stored by controlling a charge amount of a charge storage layer by a tunnel current or the like.

The data write / erase operation of such a NAND type EEPROM is as follows. Data writing is performed sequentially from the memory cell located farthest from the bit line. A high voltage Vpp (approximately 20 V) is applied to the control gate of the selected memory cell, and an intermediate potential VppM (approximately 10 V) is applied to the control gate and the selection gate of the memory cell on the bit line side. , Or OV or an intermediate potential according to data.

When 0 V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, “1”. When an intermediate potential is applied to the bit line, electron injection does not occur, so that the threshold does not change and remains negative. This state is "0".

Data erasure is performed on all memory cells in a NAND cell at the same time. That is, all control gates and select gates are set to 0 V, the bit lines and source lines are set in a floating state, and a high voltage of 20 V is applied to the p-type well and the n-type substrate.
Is applied. As a result, in all the memory cells, electrons of the floating gate are emitted to the p-type well, and the threshold value shifts in the negative direction.

As can be understood from the above description, in general, a single power supply operation EEPROM needs to generate a voltage higher than the power supply voltage inside. For this reason, this high voltage is conventionally generated using a booster circuit. The current supply capability of a booster circuit generally decreases with a drop in power supply voltage. Further, the booster circuit is driven by a ring oscillator, and the oscillation frequency of the ring oscillator also decreases as the power supply voltage drops. For this reason, a booster circuit designed to operate at the lowest power supply voltage value has an excessive current supply capability at the maximum power supply voltage value, and wastes power supply power.

In order to solve the above problem, the present inventors have proposed an oscillation circuit in which the oscillation frequency increases with a decrease in the power supply voltage, and a drive frequency dependent boost drive capability, which boosts the power supply voltage by driving the oscillation circuit. EEPR having a booster circuit for generating a necessary voltage at the time of writing / erasing of a memory body
OM has already been proposed (JP-A-5-325578). This makes it possible to obtain a boosted potential that does not depend on fluctuations in the power supply voltage, and eliminate waste of power supply power caused by fluctuations in the power supply voltage during writing / erasing.

However, even with this type of device,
The following problems could not be avoided. That is, it is difficult to strictly control the conductance and threshold value of the transistor when manufacturing the oscillation circuit, and it is inevitable that some variation occurs. The oscillation frequency changes due to this variation. When the temperature changes, the conductance and the threshold also change, so that the oscillation frequency fluctuates due to the temperature change. Such a frequency fluctuation leads to waste of power supply power.

[0010]

As described above, conventionally, in an EEPROM having a booster circuit, power supply power is wasted due to a change in current supply capability of the booster circuit caused by a change in power supply voltage during writing / erasing. There was a problem. Further, in order to solve this, Japanese Patent Laid-Open Publication No.
Even if the configuration as disclosed in Japanese Patent No. 25578 is adopted, there is a problem that power supply power is wasted due to fluctuations in the oscillation frequency due to manufacturing variations and temperature fluctuations.

The present invention has been made in consideration of the above circumstances, and has as its object to increase the boosting capability not depending not only on fluctuations in the power supply voltage but also on manufacturing variations and temperature fluctuations. An object of the present invention is to provide a nonvolatile semiconductor memory device in which a power supply power is not wasted at the time of writing / erasing by mounting a booster circuit having the above.

[0012]

In order to solve the above problems, the present invention employs the following configuration. That is, the present invention provides a memory main body having a non-volatile memory function, an oscillation circuit whose oscillation frequency changes in accordance with the magnitude of a power supply voltage, a drive frequency dependency in boosting capability, and power supply by driving the oscillation circuit. A non-volatile semiconductor memory device, comprising: a booster circuit that boosts a voltage to generate a voltage required for writing / erasing data in the memory body, wherein the oscillation circuit includes a constant current source that generates a constant current; A capacitor whose one end is connected to the constant current source by inversion of an input signal;
A reference voltage source that generates a reference voltage, and an amplification circuit that amplifies and outputs a difference between a voltage at one end of the capacitive element and the reference voltage, and a delay circuit that includes:
At one end of the capacitive element until the input signal is inverted.
The difference between the power supply voltage and the reference voltage increases as the power supply voltage increases.
It is characterized by increasing to .

Here, preferred embodiments of the present invention include the following. (1) The memory body is a NAND type EEPROM in which a plurality of nonvolatile memory cells having an FET-MOS structure are connected in series. (2) The oscillation circuit is connected to a first constant current source for generating a constant current, a first capacitive element having one end connected to the first constant current source due to inversion of the input signal, and until the input signal is inverted. Amplifying and outputting the difference between the reference voltage and the voltage at one end of the first capacitive element such that the difference between the voltage at one end of the first capacitive element increases as the power supply voltage increases. A first delay circuit, a second constant current source for generating a constant current, a second capacitive element having one end connected to the second constant current source by inverting an input signal, and a reference voltage and a second voltage. A second delay circuit comprising a second amplifying circuit for amplifying and outputting the difference between the voltage at one end of the capacitive element and an output of the sequential logic of the output of the first amplifying circuit and the output of the second amplifying circuit And a sequential logic circuit for providing the output as an input to the first and second delay circuits. thing. (3) The constant current source includes a first MOS transistor having a gate and a drain connected to each other, a resistance element connected in series with the first MOS transistor, and a reference voltage for outputting a gate voltage of the first MOS transistor. A second MOS transistor whose output is input to the gate, whose source is connected to the source of the first MOS transistor, and whose drain is selectively connected to one end of the capacitor together with the first power supply voltage terminal; To configure.

[0014]

According to the present invention, the current supply capability of the booster circuit tends to decrease as the power supply voltage drops, but the oscillation frequency of the oscillating circuit for driving the same increases with the power supply voltage drop. Is negated. As a result, a booster circuit having a current supply capability independent of the power supply voltage is realized, and the power supply power is not wasted due to the fluctuation of the power supply voltage at the time of writing / erasing.

In addition, according to the present invention, the oscillation circuit is provided with a constant current source so that variations in the conductance and threshold value of the transistor do not affect the oscillation frequency. Can be prevented beforehand, thereby making it possible to more reliably eliminate waste of power supply power.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a NAND type E according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a nonvolatile semiconductor memory device using an EPROM.

A bit line control circuit 2 for writing and reading data to and from a memory cell array 1 as a memory means is provided. The bit line control circuit 2 is connected to a data input / output buffer 6 and receives an output of a column coder 3 for receiving an address signal from an address buffer 4 as an input. A row decoder 5 is provided for the memory cell array 1 to control a control gate and a selection gate, and a substrate for controlling the potential of a p-type substrate (or a p-type well) on which the memory cell array 1 is formed. A potential control circuit 7 is provided.

The memory main unit 10 is constituted by a circuit or the like which performs each function of the memory cell array 1 or the substrate potential control circuit 7 described above.
Is configured. The booster circuit 8 receives a drive signal from an oscillator 9 as an oscillation circuit and applies a high voltage boosted from a power supply voltage to a bit line control circuit 2, a row decoder 5, a substrate potential control circuit when writing / erasing the memory cell array 1. 7

FIGS. 2A and 2B show the memory cell array 1.
3A is a plan view of one NAND cell portion and FIG. 3B is an equivalent circuit diagram. FIGS.
It is A 'and BB' sectional drawing. In a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12,
A memory cell array 1 including a plurality of NAND cells is formed. In this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell.

Each of the memory cells has a floating gate 14 (14 ₁ , 14 ₁₎ on a substrate 11 via a tunnel insulating film 13.
_2, ..., 14 ₈₎ are formed, the gate insulating film 1 on the
5, the control gate 16 (16 ₁ , 16 ₂ ,..., 16
₈ ) is formed and configured. The memory cells are connected in series so that adjacent ones of the n-type diffusion layers 19, which are the source / drain of these memory cells, are shared.

The drain side of the NAND cell, each of the source side, the floating gate of the memory cell, the select gate is formed simultaneously with the control gate 14 _9, 16 ₉ and 14 _10, 1
6 ₁₀ are provided. CVD on the substrate on which the elements are formed
It is covered with an oxide film 17, on which a bit line 18 is provided. The bit line 18 is in contact with the drain diffusion layer 19 at one end of the NAND cell. The control gates 16 of the NAND cells arranged in the row direction are commonly arranged as control gate lines CG1, CG2,..., CG8.
These control gate lines become word lines. Select gate 1
4 _9, 16 ₉ and 14 _10, 16 ₁₀ are also respectively arranged in a row direction successively selected gate SG1, SG2.

FIG. 4 shows an equivalent circuit of the memory cell array 1 in which such NAND cells are arranged in a matrix. FIG. 5 shows a first specific configuration of the booster circuit 8 in FIG. FIG. 6 shows drive signals VP1, VP2 of the booster circuit 8.
, VP3, and VP4.

The voltage is raised by a D-type n-channel MO.
Using S transistors QD1 to QD4 as capacitors,
Type n-channel MOS transistors Qn1 to Qn4, Qn1
7 is used as a transfer gate. D-type n-channel MOS transistors QD5 to QD5 as capacitors are used to boost the gate voltages of transfer gates Qn1 to Qn4 to prevent a voltage drop due to a threshold voltage.
QD8 and E-type n-channel MOS as transfer gate
Transistors Qn5 to Qn8 are provided.

Further, the E-type n-channel MOS transistors Qn13, Qn14, Qn15 and the D-type n-channel MOS transistors QD9, QD10 boost the gate voltage of the transfer gate Qn17, and no voltage drop due to the threshold voltage occurs as described above. It is provided for the purpose. The E type channel MOS transistor Qn16 is provided for equalizing the gate electrode of Qn14 and the output voltage Vpp. These MOS transistors Qn13, Qn14, Qn15,
The portion consisting of QD9 and QD10 operates as a dummy boosting stage. In the present embodiment, four-stage boosting is performed, but the number of stages may be adjusted as needed.

When VP1 is "L" and the power supply voltage Vcc
, The capacitors QD1 and QD3 are charged. When VP1 is "H", the charged charges of the capacitors QD1 and QD3 are transferred to the capacitors QD6 and QD8 through the transfer gates Qn6 and Qn8, respectively, and charged, and the gate voltages of the transfer gates Qn2 and Qn4 are boosted. In this state, VP2 becomes "L",
When VP4 becomes "H", the charge of the capacitors QD1 and QD3 is transferred to the capacitors QD2 and QD4 through the transfer gates Qn2 and Qn4, respectively, and charged.

Such an operation is repeated to generate a boosted voltage Vout obtained by boosting the power supply voltage Vcc to a predetermined value.
Although the boosting capability of the booster circuit 8 tends to decrease as the power supply voltage Vcc drops, the drive signals VP1, VP2, VP3
, VP4, the higher the frequency, the greater the tendency.

FIG. 7 shows a second specific configuration of the booster circuit 8 in FIG. FIG. 8 shows the drive signals V1,
The output signal of the oscillator 9 which is V2 is shown. The voltage is increased by the D-type n-channel MOS transistor QD5.
~ QD8 as a capacitor, E-type n-channel M
This is performed by using the OS transistors Qn18 to Qn21 as transfer gates. When V1 changes from "H" to "L" and V2 changes from "L" to "H" at the same time, the E-type n-channel MOS transistors Qn18 and Qn20 turn on and Q
Since n19 and Qn21 are turned off, the charges of the capacitors QD5 and QD7 are transferred to the capacitors QD5 and QD8, respectively.

When the drive signals V1 and V2 have "H.L" reversed, the on / off states of the transfer gates Qn18 to Qn21 are also reversed, so that the charges of the capacitors QD6 and QD8 are transferred to the capacitor QD7 and the output Vout, respectively. You. Such a state is alternately repeated, and the power supply voltage is boosted. The boosting capability of the booster circuit 8 tends to decrease as the power supply voltage drops, but this tendency is canceled by the increase in the frequency of the drive signals V1 and V2.

FIG. 9 shows a ring oscillator which is one of the conventional oscillation circuits. When the input signal Vin is "L", no oscillation occurs, and the output signal VRNG is fixed at "H". Then, when the input signal Vin becomes “H”, oscillation starts.

FIG. 10 shows a first specific configuration of the oscillator 9 in FIG. The capacitor C1 is an n-channel M
One end is selectively connected to the power supply voltage Vcc and the drain of the n-channel MOS transistor Qn34 according to the voltage level of the common gate of the OS transistor Qn36 and the p-channel MOS transistor Qp9. Similarly, one end of the capacitor C2 is selectively connected to the power supply voltage Vcc and the drain of the n-channel MOS transistor Qn35 according to the voltage level of the common gate of the n-channel MOS transistor Qn37 and the p-channel MOS transistor Qp10.

N channel MOS transistors Qn27, Qn2
8 and p-channel MOS transistors Qp1, Qp2, Qp3
Are the voltage Vref at the gate and drain of the n-channel MOS transistor Qn33 and the voltage Vca at one end of the capacitor C1.
A first amplifier circuit is configured to compare p1 with each other, amplify the difference therebetween, and output the amplified signal. Similarly, the n-channel MOS transistors Qn29 and Qn30 and the p-channel MOS transistors Qp4, Qp5 and Qp6 compare the voltage Vref with the voltage Vcap2 at one end of the capacitor C2, amplify the difference therebetween and output the result. Is composed. NOR gate G2
, G3 constitute a sequential logic circuit for outputting the sequential logic of the outputs of these two amplifier circuits.

N channel MOS transistors Qn36 and p
The voltage level of the common gate of channel MOS transistor Qp9 and the voltage level of the common gate of n-channel MOS transistor Qn37 and p-channel MOS transistor Qp10 alternately change to "H
In the standby state, the input signal Vin is "H" and the n-channel MOS transistor Q
n26, Qn32, Qn100 and Qn101 are on, and p-channel MOS transistors Qp1 and Qp4 are off. Therefore, Vref
, Vcap2 and Vosc1 are “L”, and Vcap1 and Vosc2 are “H”.
It has become.

When the input signal Vin changes from "H" to "L", oscillation starts as follows. n-channel MOS
Since the transistor Qn30 is off, the drain voltage becomes "H". At this time, Vosc1 and Vosc2 are inverted, and the n-channel MOS transistor Qn36 and the p-channel MOS transistor Qp10 are turned on. Vcap2 is p
It rises rapidly by the channel MOS transistor Qp10, and the sequential logic circuit is reset. Vcap1, which has been set to Vcc, decreases linearly with time due to a constant current flowing through the n-channel MOS transistor Qn34. Then, when Vcap1 becomes smaller than Vref, the output of the amplifier circuit is inverted.
osc1 and Vosc2 are respectively inverted. Such a state is repeated, and the outputs Vosc1 and Vosc2 of the oscillator (oscillation circuit) oscillate.

Hereinafter, it will be described that the oscillation frequency f of the oscillator decreases as Vcc increases. The constant voltage Vd independent of the power supply voltage is output to the source of the n-channel MOS transistor Qn31 whose constant voltage Vst is input to the gate. Vref is the resistance value R of the resistance element R1.
And the conductance g1 of the n-channel MOS transistor Qn33, and does not depend on Vcc.
For simplicity, n-channel MOS transistors Qn34 and Qn34
Suppose that the conductance of n35 is equal to g2, and the capacitance of capacitors C1 and C2 is equal to C. n-channel MO
Assuming that currents flowing through the S transistors Qn33 and Qn34 (Qn35) are Iref and Icap, respectively, Iref = (Vd−Vref) / R (1) Icap = Iref × (g2 / g1) (2) is established. Since the oscillation period T is equal to twice the time required for Vcap1 (2) to change from Vcc to Vref as described above, T = 2 × C × (Vcc−Vref) / Icap = 2 × R × C × (g2 / G1) × (Vcc−Vref) / (Vd−Vref) (3) Thus, the oscillation frequency f = 1 / T becomes (Vcc-V
ref).

Here, in the equation (3), the conductances g1 and g2 of the MOS transistor are inserted in the form of (g2 / g1). Although the conductance of the MOS transistor varies somewhat depending on the conditions at the time of manufacturing, the variation of each transistor in the same chip is in the same direction. Therefore, even if the conductances g1 and g2 vary somewhat during manufacture, the ratio (g2 / g1) is constant. on the other hand,
Although the threshold value Vt of the transistor changes depending on the temperature, the term of the threshold value Vt does not exist in the equation (3). Therefore, it can be seen that the oscillation frequency does not depend on manufacturing variations or changes in temperature.

In the conventional device, the equation of the oscillation frequency is expressed by M
The conductance of the OS transistor is inserted alone,
Further, since the threshold Vt was inserted, the oscillation frequency fluctuated due to manufacturing variations and changes in temperature.

FIG. 11 shows a second specific configuration of the oscillator 9 in FIG. Capacitor C3 is an n-channel MO
One end is selectively connected to the power supply voltage Vss equal to the ground level and the drain of the p-channel MOS transistor Qp13 according to the voltage level of the common gate of the S transistor Qn38 and the p-channel MOS transistor Qp16. Similarly, the capacitor C4 is an n-channel MOS transistor Q
One end is selectively connected to the power supply voltage Vss and the drain of the p-channel MOS transistor Qp14 according to the voltage level of the common gate of the n39 and the p-channel MOS transistor Qp17.

N channel MOS transistors Qn40, Qn4
1, Qn42 and p-channel MOS transistors Qp19, Qp20,
Qp21 forms a first amplifier circuit that compares the voltage Vref at the gate and drain of the p-channel MOS transistor Qp12 with the voltage Vcap1 at one end of the capacitor C3, amplifies the difference therebetween, and outputs the result. Similarly, n-channel MO
S transistors Qn44, Qn45, Qn46 and p-channel MOS
The transistors Qp22, Qp23, and Qp24 constitute a second amplifier circuit that compares the voltage Vref with the voltage Vcap2 at one end of the capacitor C4, amplifies the difference therebetween, and outputs the result. The NAND gates G4 and G5 form a sequential logic circuit that outputs the sequential logic of the outputs of these two amplifier circuits.

N channel MOS transistors Qn38 and p
The voltage level of the common gate of the channel MOS transistor Qp16 and the voltage level of the common gate of the n-channel MOS transistor Qn39 and the p-channel MOS transistor Qp17 alternately change to “H.
L ".

At the time of standby, the input signal Vin is "H".
And an n-channel MOS transistor Qn43,
The p-channel MOS transistors Qp11, Qp18, Qp25 are on, the n-channel MOS transistors Qn42, Qn46, and the p-channel MOS transistors Qp19, Qp20 are off. Therefore, Vref, Vcap2, Vosc1 are “H”, Vcap
1, Vosc2 is "L".

When the input signal Vin changes from "H" to "L", oscillation starts as follows. p-channel MOS
Since the transistor Qp24 is off, the drain voltage becomes "H". At this time, Vosc1 and Vosc2 are inverted, and the n-channel MOS transistor Qn39 and the p-channel MOS transistor Qp16 are turned on. Vcap2 is n
Channel MOS transistor Qn39 causes a rapid drop, and the sequential logic circuit is reset. Vcap1, which has been set to Vss, decreases linearly with time due to a constant current flowing through the p-channel MOS transistor Qn13. When Vcap1 becomes larger than Vref, the output of the amplifier circuit is inverted.
osc1 and Vosc2 are inverted respectively. Such a state is repeated, and the outputs Vosc1 and Vsc of the oscillator (oscillation circuit) are output.
osc2 oscillates.

Hereinafter, it will be described that the oscillation frequency f of the oscillator decreases as Vcc increases. A constant voltage Vd independent of the power supply voltage is output to the drain of the p-channel MOS transistor Qp15 to which a constant voltage Vst is input to the gate. Vref is determined by the resistance value R of the resistance element R2, the conductance g1 of the p-channel MOS transistor Qp12, and the conductance g2 of Qp15, and increases as Vcc increases. For simplicity, it is assumed that the conductance of p-channel MOS transistors Qp13 and Qp14 is equal to g2, and the capacitance of capacitors C3 and C4 is equal to C. p channel MOS transistor Qp1
2 and the currents flowing through Qp13 (Qp14) are Iref and Ica, respectively.
Assuming that p, Iref = Vd / R (4) Icap = Iref × (g2 / g1) (5) Since the oscillation period T is equal to twice the time required for Vcap1 (2) to change from Vcc to Vref as described above, T = 2 × C × Vref / Icap = 2 × R × C × (g2 / g1) × Vref / Vd (6) Thus, it can be seen that the oscillation frequency f = 1 / T is inversely proportional to Vref which increases as Vcc increases.

Also in this case, g1 and g2 are inserted in the form of (g2 / g1) in the equation (6), and there is no term of the threshold value Vt. Therefore, it can be seen that the oscillation frequency does not depend on manufacturing variations or changes in temperature, as in the circuit of FIG.

FIG. 12 shows the configuration of FIG. 6 for driving the booster circuit of FIG.
Circuit for outputting the signals VP1 to VP4 of FIG. Since a constant voltage independent of the power supply voltage is output to the drain of p-channel MOS transistor Qp29 whose constant voltage Vst is input to the gate, an inverter composed of n-channel MOS transistor Qn51 and p-channel MOS transistor Qp30 Does not depend on Vcc.

FIG. 13 shows a first constant voltage generating circuit.
The output Vout is equal to n-channel MOS transistors Qn48 and Qn48.
It is equal to the difference between the threshold voltages of I1. FIG. 14 shows a first block diagram of a booster circuit driven by an output of an oscillator whose oscillation frequency increases as the power supply voltage decreases. Reference numeral 51 denotes the constant voltage generation circuit of FIG. 13, 52 denotes the oscillation circuit of FIG. 10 or 11, and 53 denotes the booster circuit of FIG. With this configuration, the Vcc dependency of the boosting capability is reduced.

FIG. 15 shows a second block diagram of the second constant voltage generating circuit and the booster circuit driven by the output of the oscillator whose oscillation frequency increases as the power supply voltage decreases. When the input signal Von changes from "L" to "H", the oscillator starts operating, and a booster circuit 54 for generating a constant voltage,
At the time of writing / erasing, driving of the booster circuit 53 for charging the load capacitance to be set to a high voltage is started. Since the p-channel MOS transistor Qp36 is on until the delay time Td elapses, the drain voltage Vm is equal to Vcc, and the oscillation frequency of the oscillator 52 decreases as the power supply voltage decreases.

However, since the load capacity of the booster circuit 53 for generating a constant voltage is small, the output voltage is immediately set to the breakdown voltage Vz of the Zener diode ZD1. Thereafter, when the delay time Td elapses, the p-channel MOS
The transistor Qp36 is turned off, and the drain voltage Vm becomes a value obtained by dividing the breakdown voltage Vz by resistance. This value does not depend on Vcc, and the oscillation frequency of the oscillator 53 increases as the power supply voltage decreases. Thus, the dependency of the boosting capacity of the boosting circuit for charging the load capacitance to be set to a high voltage at the time of writing / erasing on the power supply voltage can be reduced.

FIG. 16 shows a third block diagram of a third constant voltage generating circuit and a booster circuit driven by the output of an oscillator whose oscillation frequency increases as the power supply voltage decreases. The constant voltage generating circuit includes a ring oscillator 55 (FIG. 9) having a large Vcc dependency, a constant voltage generating boosting circuit 54 driven by the output signal RNG, a Zener diode ZD2, and a resistance divider of the breakdown voltage Vz. R5 and R6. Until the delay time Td elapses, the constant voltage is applied to the oscillator 52 and the booster circuit 58
Although input to the signal generation circuit 57 (FIG. 12) for driving (FIG. 5), the circuit operation does not start. After the elapse of the delay time Td, these circuits start operating, and the booster circuit 58 that drives the load capacitance to be set to a high voltage at the time of writing / erasing is driven. Thus, the power supply voltage dependency of the boosting capability of the booster circuit can be reduced.

FIG. 21 shows a delay circuit constituting oscillator 9 in FIG. FIG. 22 shows the respective voltage waveforms.
Until the input signal Vin is inverted, the voltage Vcap at one end of the capacitor 103 is connected to the first power supply voltage terminal 110. When the input signal Vin is inverted, Vcap is changed by the constant current source 102 at a constant rate with respect to time. The amplifier circuit 101 compares Vcap with the reference voltage Vref and amplifies the difference therebetween. Therefore, the amplification circuit 101
Inverts the output when Vcap and Vref become equal.

The first power supply voltage terminal 110 is connected to the power supply voltage Vcc.
, V1 is equal to Vcc, V2 is equal to Vref, and the slope of Vcap is negative. Here, Vref is made to decrease with an increase in Vcc or to be invariant with Vcc. If the capacitance of the capacitor 103 is written as C and the constant current is written as Iconst, the delay time Td from when the input is inverted to when the output is inverted is, in principle, Td = C × (Vcc−Vref) / Iconst, and Vcc The delay time increases with the increase of.

The first power supply voltage terminal 110 is connected to the power supply voltage Vss
When = 0 V, V1 is equal to Vss, V2 is equal to Vref, and the slope of Vcap is positive. Here, Vref is set to increase as Vcc increases. If the capacitance of the capacitor 103 is written as C and the constant current is written as Iconst, the delay time Td from when the input is inverted to when the output is inverted is Td
Is, in principle, Td = C × Vref / Iconst, and the delay time increases as Vcc increases.

FIG. 17 shows a third oscillator in this embodiment, and FIG. 18 shows each voltage waveform. The outputs of the two delay circuits 1000 are input to the sequential logic circuit 105, and the outputs are input to the respective delay circuits 1000. V
Vcap1, which has been set to cc, decreases linearly with time due to the constant current. When Vcap1 becomes smaller than Vref, the output of the amplifier circuit is inverted. As a result, Vout1 and Vout2 are inverted by the sequential logic circuit. Then, Vcap1 is rapidly charged to Vcc, and Vcap2, which has been kept at Vcc, decreases linearly with time by the constant current. When Vcap2 becomes smaller than Vref, the output of the amplifier circuit is inverted. As a result, Vout1 and Vout2 are inverted by the sequential logic circuit.

Such a state is repeated, and the outputs Vout1 and Vout2 of the oscillator (oscillation circuit) oscillate. Vca
While the amplitudes of p1 and Vcap2 increase with an increase in Vcc, the drive current is constant, so that the oscillation frequency of the oscillator decreases with an increase in Vcc.

FIG. 19 shows a fourth oscillator in this embodiment, and FIG. 20 shows each voltage waveform. The constant voltage Vref in FIG. 20 increases with an increase in Vcc. Two delay circuits 1
000 is input to the sequential logic circuit 105, and its output is input to each delay circuit 1000. Vcap1, which has been grounded, rises linearly with time due to the constant current. When Vcap1 becomes larger than Vref, the output of the amplifier circuit is inverted. As a result, Vout1 and Vout2 are inverted by the sequential logic circuit. Then, Vcap1 is rapidly discharged to the ground level, and Vcap2, which has been grounded, rises linearly with time by a constant current. When Vcap1 becomes larger than Vref, the output of the amplifier circuit is inverted. As a result, Vout1 and Vout2 are inverted by the sequential logic circuit.

Such a state is repeated, and the outputs Vout1 and Vout2 of the oscillator (oscillation circuit) oscillate. Vca
While the amplitudes of p1 and Vcap2 increase with an increase in Vcc, the drive current is constant, so that the oscillation frequency of the oscillator decreases with an increase in Vcc.

The present invention is not limited to the embodiment described above. The configuration of the memory cell array is not limited to the NAND type, but is a NOR type (AND type including a cell unit in which a plurality of memory cells are connected in parallel and select gates connected to both ends of the unit). The present invention can also be applied to a DINOR type having a select gate connected to one end. Further, the memory cell is not limited to the FET-MOS structure having a two-layer gate, but can be applied to a memory cell requiring a boosted potential at the time of writing / erasing. In addition, various modifications can be made without departing from the scope of the present invention.

[0057]

As described above in detail, according to the present invention, a non-volatile circuit including an oscillation circuit whose oscillation frequency changes according to the magnitude of a power supply voltage, and a booster circuit which boosts the power supply voltage by driving the oscillation circuit In addition to realizing a booster circuit with current supply capability independent of power supply voltage in a volatile semiconductor memory device, it also prevents variations in transistor conductance and threshold voltage, as well as fluctuations in oscillation frequency due to temperature changes. A booster circuit having a boosting capability that does not depend on variations and temperature fluctuations can be realized, and waste of power supply power at the time of writing / erasing can be reliably eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a plan view and an equivalent circuit diagram showing a configuration of a NAND cell in the embodiment.

FIG. 3 is a sectional view taken along line AA ′ and line BB ′ in FIG.

FIG. 4 is an equivalent circuit diagram of a memory cell array in the embodiment.

FIG. 5 is a circuit diagram showing a first configuration example of a booster circuit in the embodiment.

FIG. 6 is a timing chart showing drive signals of the booster circuit of FIG. 5;

FIG. 7 is a circuit diagram showing a second configuration example of the booster circuit in the embodiment.

FIG. 8 is a timing chart showing drive signals of the booster circuit of FIG. 7;

FIG. 9 is a circuit diagram showing a ring oscillator which is one of conventional oscillation circuits.

FIG. 10 is a circuit diagram showing a first configuration example of an oscillator in the embodiment.

FIG. 11 is a circuit diagram showing a second configuration example of the oscillator in the embodiment.

12 is a circuit diagram illustrating a configuration of a circuit that outputs a signal for driving the booster circuit in FIG. 5;

FIG. 13 is a circuit diagram showing a configuration of a first constant voltage generation circuit in the embodiment.

FIG. 14 is a block diagram of a booster circuit using a first constant voltage generation circuit.

FIG. 15 is a block diagram of a booster circuit using a second constant voltage generation circuit.

FIG. 16 is a block diagram of a booster circuit using a third constant voltage generation circuit.

FIG. 17 is a circuit diagram showing a third configuration example of the oscillator in the embodiment.

FIG. 18 is a diagram showing voltage waveforms at main nodes of the oscillator shown in FIG. 17;

FIG. 19 is a circuit diagram showing a fourth configuration example of the oscillator in the embodiment.

FIG. 20 is a diagram showing voltage waveforms at main nodes of the oscillator shown in FIG. 19;

FIG. 21 is a diagram showing a delay circuit forming the oscillator according to the embodiment.

FIG. 22 is a diagram illustrating voltage waveforms at main nodes of the delay circuit of FIG. 21;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Bit line control circuit 3 ... Column decoder 4 ... Address buffer 5 ... Row decoder 6 ... Data input / output buffer 7 ... Substrate potential control circuit 8 ... Boost circuit 9 ... Oscillator 10 ... Memory body 11 ... P type silicon Substrate or p-type well 12 element isolation oxide film 13 tunnel insulating film 14 floating gate 15 gate insulating film 16 control gate 17 interlayer insulating film 18 bit line 19 n-type diffusion layer 51 constant voltage generating circuit 52 oscillation circuit 53, 54, 58 booster circuit 55 ring oscillator 57 signal generator 100 switch 101 amplifier circuit 102 constant current source 103 capacitor 104 reference voltage source 105 sequential logic circuit 110 power supply voltage Terminal 1000: delay circuit

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 3/00-3/22

Claims (5)

(57) [Claims] A memory body having a non-volatile memory function; an oscillation circuit whose oscillation frequency changes in accordance with the magnitude of a power supply voltage; a drive frequency dependency in boosting capability; A non-volatile semiconductor storage device, comprising: a booster circuit that boosts a voltage to generate a required voltage at the time of writing / erasing of the memory main body, wherein the oscillation circuit generates a constant current; A capacitance element having one end connected to the constant current source by inverting an input signal; a reference voltage source for generating a reference voltage; and an amplifier for amplifying and outputting a difference between a voltage at one end of the capacitance element and the reference voltage. And a delay circuit including: a delay circuit, until the input signal is inverted in the delay circuit.
The difference between the voltage at one end of the capacitive element and the reference voltage is the power supply voltage.
A nonvolatile semiconductor memory device which increases with an increase in pressure . Wherein said oscillation circuit includes a first constant current source for generating a constant current, a first capacitor one end by the inverse of the input signal is connected to a first constant current source, the reference voltage A first amplifier circuit for amplifying and outputting the difference between the reference voltage from the source and the voltage at one end of the first capacitor, and a first capacitor until the input signal is inverted.
The difference between the voltage at one end of the
A first delay circuit that increases with an increase, a second constant current source that generates a constant current, a second capacitance element having one end connected to the second constant current source by inverting an input signal, A second amplifier circuit for amplifying and outputting the difference between the reference voltage and the voltage at one end of the second capacitor, and one end of the second capacitor until the input signal is inverted.
The difference between the reference voltage and the reference voltage increases as the power supply voltage increases.
A second delay circuit that increases, a sequential logic circuit that outputs a sequential logic of an output of the first amplifier circuit and an output of the second amplifier circuit, and provides the output as an input of the first and second delay circuits; The nonvolatile semiconductor memory device according to claim 1, comprising: 3. The constant current source includes: a first MOS transistor having a gate and a drain connected to each other; a resistance element connected in series with the first MOS transistor;
The output of the reference voltage source that outputs the gate voltage of the S transistor is input to the gate, the source is connected to the source of the first MOS transistor, and the drain is selectively connected to one end of the capacitive element together with the first power supply voltage terminal. 3. The nonvolatile semiconductor memory device according to claim 1, further comprising: a second MOS transistor connected to the second MOS transistor. 4. The method according to claim 1 , wherein the capacitance of the capacitive element is maintained until the input signal is inverted.
The voltage is a power supply voltage, and the reference voltage is a constant voltage
The nonvolatile memory according to any one of claims 1 to 3, wherein
Semiconductor memory device. 5. The method according to claim 1 , further comprising the step of:
The voltage is a ground voltage, and the reference voltage is a constant voltage
The nonvolatile memory according to any one of claims 1 to 3, wherein
Semiconductor memory device.