JP3175138B2 - Bus interface device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus interface device suitable for a common transmission line bus having a transmission speed of about 31.25 kbps widely used in process control and the like, and in particular, to a multi-station arrangement on a bus. And easy improvement of the interface to the existing bus.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing the configuration of a conventional current transmission type bus interface device. In the figure, a pair of signal lines L1 and L2 are a common transmission path bus for transmitting a current signal. A plurality of communication stations ST are arranged on the bus for transmitting and receiving signals on the bus, and include a transmitting unit TX and a receiving unit RX. The transmitting unit TX receives a serial 1-bit signal from a communication frame generating unit separately provided inside the communication station ST, and outputs a current signal corresponding to the serial 1-bit signal. Level is 1
The polarity of the current signal to be transmitted is the same for both the H level, the L level and the neutral level, such as mA and the neutral level at the time of non-transmission is 10 mA. Here, the characteristic impedance Z _AC with respect to the frequency of the communication carrier of the signal lines L1 and L2 is 1
Assuming that the characteristic impedance Z _DC for a power supply close to 00Ω and _DC is 50Ω, the voltage corresponding to this current signal of 10 ± 9 mA is 0.5 ± 0.45V.

According to such a current transmission type, there is an advantage that a bus condition can be favorably maintained. For example, even if a failure occurs in a certain communication station ST and H-level current continues to flow to the bus, it is equivalent to a temporary change in the neutral level for the entire bus. On the other hand, if a failure occurs in a certain communication station ST of the voltage transmission type and the H-level voltage continues to flow to the bus, the entire bus is recognized as the H-level voltage. Cannot be performed. Therefore, according to the current transmission type, it is possible to perform a remote search for a faulty station by using a bus usage of a call / no response.

On the other hand, as a drawback of the current transmission type, the number of stations that can be arranged on the bus is limited by the current transmission capability of each communication station. Therefore, the current transmission capability of each communication station is limited according to the intended number of stations. That is what needs to be strengthened. For example, when ten communication stations having a neutral level of 10 mA are arranged on a bus, superposition of neutral level currents occurs on the bus. now,
If the DC characteristic impedance Z _DC is 50Ω, the neutral level current I _{0 of} each communication station is 10 mA, and the number n of stations arranged on the bus is 10, the neutral level current on the bus represented by the following equation is obtained. And the DC voltage of 5 V is resident on the bus. Z _DC (50Ω) × I ₀ (10 mA) × n (10 units) = 5 V _DC (1) Therefore, there arises a problem that each communication station needs to be capable of overcoming the resident voltage and supplying current.

FIG. 10 is a diagram for explaining the relationship between the general structure of a common transmission path bus and a bus interface device. A pair of signal lines L1 and L2 is a common transmission line bus of a type called a twisted pair, and each signal line L1, L2
And two sets of a terminating resistor RT and a ground capacitor C0. Then, one end of the ground capacitor C
0 is grounded, and the grounding capacitor C0 at the other end is not grounded. Here, the constant of the element used for the termination is, for example, 50Ω for RT and 10 μF for C0. The bus power supply PS1 is a circuit for supplying a current to the bus, and the DC coupling means ZDC has a characteristic impedance Z _{AC with} respect to the frequency of the communication carrier as a power supply as large as possible so as not to affect the inherent characteristic impedance of the bus. When supplying, a resident DC voltage Z _{DC represented} by equation (1)
It has a DC impedance Z _DC as small as possible to reduce xI ₀ xn, and for example, an inductance of about 20 mH is used.

The communication station ST has a transmission function TX for outputting a 1-bit pulse train signal to the bus, and is provided with an office power supply PS2 for operation. For such a common transmission path bus, the voltage of the bus power supply PS1 is 20V, 10V.
It is selected to be a constant voltage such as V or 0V. The transmitting / receiving station ST connected to such a bus is of a current type,
The current is transmitted at the voltage of the bus power supply PS1.

[0007]

Therefore, it is important to lower the bus resident voltage Z _DC xI ₀ xn, which increases in proportion to the connected transmitting station. First, it is conceivable to reduce the current I ₀ at the neutral level of each communication station. But,
The pulse signal transmits a signal by [neutral level current] ± [H, L level pulse current], and the H, L level pulse current I ₀ ± α needs to be the same sign as I _0. is there. The peak current α of the pulse current cannot be made extremely small in order to ensure resistance to noise, and there is a certain limit since I ₀ cannot be smaller than α.

Next, it is conceivable to reduce the _DC characteristic impedance Z _DC , but it is impossible to reduce the DC resistance of the bus to zero because the DC resistance is severe. Therefore, the number n of stations arranged on the bus is unavoidably limited, but there is a problem that it is not suitable for a large-scale instrumentation system. The present invention has been made to solve the above problems, and has a bus interface capable of disposing a large number of stations on a bus and transmitting a 1-bit signal to the bus independently of a DC bias current flowing through the bus. It is intended to provide a device.

[0009]

According to the present invention for achieving the above object, a 1-bit signal is serially connected to a pair of signal lines L1 and L2, and the 1-bit signal is set to a high level, a low level and a neutral level. A positive side voltage output PS2 + or a negative side voltage output PS2- of a station power supply PS2 having a positive / negative voltage output for supplying power for operation to the bus interface device for transmitting data with three levels of current values. At least one of which inputs a signal line connection portion 60 connected to one of the signal lines L2 and a signal voltage TXIN commanded from the outside, and the negative input portion TXIN- is connected to the negative voltage output terminal. Connected to
Positive side of the input unit TXIN + signal input unit 40 connected to the input capacitor Cin, the potential of the intermediate connection point CP of the signal transmitting unit inputs via the feedback resistor R _FB, is inputted through the input capacitor Adder circuit 50 for adding to signal voltage
And first to fourth voltage dividing resistors connected in series for dividing the positive and negative voltage outputs of the station power supply, and the first voltage dividing resistor R
The connection point of the third voltage dividing resistor R5 is connected to the control terminal of the first current source, and the connection point of the second voltage dividing resistor and the third voltage dividing resistor R6 is connected to the output terminal of the adding circuit. The connection point of the third voltage dividing resistor and the fourth voltage dividing resistor R4 is connected to the current setting unit 30 connected to the control terminal of the second current source and the current transmitted by the control voltage input to the control terminal. First and second current sources Q1 and Q2 that increase and decrease differentially;
And a signal transmitting unit 70 for connecting an intermediate connection point of the variable current source and one of the signal lines L1 via an output capacitor Cout.

[0010]

The signal line connecting portion connects the pair of signal lines L1 and L2 and the bus interface device to determine a reference potential,
Enables current delivery. The signal input unit has an input capacitor to allow a difference between the potential of the office power supply and the signal voltage TXIN. The first and second variable current sources Q1 and Q2 receive the current from one of them, and the excess current flows through the pair of signal lines L1 and L2 connected to the bus via the output capacitor Cout. A feedback loop composed of an adder circuit, a current setting unit, first and second current sources, and a signal sending unit provides a signal voltage for externally instructing a potential at an intermediate connection point between the first and second variable current sources. By making it coincide with TXIN, the operating point is maintained at a constant value regardless of whether or not the surplus current flowing through the bus goes.

[0011]

FIG. 1 is a circuit diagram of a bus interface device according to an embodiment of the present invention, which is configured so that an operating voltage inside a transmitting station TX and an operating voltage of a bus can be set independently. In the figure, a first current source 10 flows a current _IQ1 through a resistor R1 connected to an emitter terminal of a PNP transistor Q1, and a control voltage _VQ1 is applied to a base terminal. The second current source 20 is an NPN transistor Q
The current I _Q2 flows through the resistor R2 connected to the emitter terminal of the second transistor _2, and a control voltage V _Q2 is applied to the base terminal.

The current value setting section 30 is provided between the output terminal of the buffer U1 and the first and second current sources. The resistors R3, R5, R6, and R4 are connected in series in this order. The positive side voltage output PS2 + and the negative side voltage output PS2- of the office power supply are connected to both ends of this resistance circuit. The connection point between the resistors R3 and R5 is connected to the base terminal of the transistor Q1, and generates a control voltage _VQ1 . Resistance R6
The node between R4 and R4 is connected to the base terminal of transistor _Q2 and generates control voltage _VQ2 . Resistance R5 and R
6 is connected to the output terminal of the buffer U1, and simultaneously controls the control voltage V _Q1 and the control voltage V _Q2 by the output voltage V _U1 of the buffer U1, thereby controlling the first and second current sources Q
1, Q2 is differentially increased / decreased.

The signal input unit 40 inputs a 1-bit signal TXIN via an input capacitor Cin in consideration of a DC voltage difference between the transmitting station TX and an external device. Here, the brass side of the 1-bit signal TXIN is connected to the plus terminal of the buffer U1 via the input capacitor Cin, and the minus side is connected to the negative voltage output PS2- of the office power supply. Adder circuit 50 adds the 1-bit signal TXIN inputted through the input capacitor Cin, and a potential Vcp of the intermediate connection point CP which is fed back through the feedback resistor R _FB, the current value setting via the buffer U1 Sent to the unit 30. Further, the input capacitor Cin and the feedback resistor R _FB also function as a time constant circuit, and the influence is reduced even if noise flows in from the signal lines L1 and L2.

The signal line connecting section 60 is a station power supply PS having positive and negative voltage outputs for supplying power for operation to the transmitting station TX.
The second positive side voltage output PS2 + is connected to the signal line L2 to enable current transmission to the signal lines L1 and L2. Further, the negative voltage output PS2- is connected to the signal line L1 and the bias resistor R.
Via _L1 connected so as to ensure a constant load current to the bus power source PS1 in the bias resistor R _L1 flowing a constant load current.

The signal transmitting section 70 includes transistors Q1 and Q
2 collector terminals via diodes D1 and D2.
And a common connection point of the diodes D1 and D2.
Is the output capacitor C_L1Connected to the signal line L1 through
I have. Here, diodes D1 and D2 are transistors
Q1 and Q2 become low collector voltage due to high collector voltage etc.
Impedance and cannot maintain the variable current value.
In order not to affect the signal line L1 even if the state is changed,
Provided for protection. The output capacitor C _L1Is
Even if there is a potential difference between the line L1 and the transmitting station TX.
Inserted so that you can continue.

The operation of the thus constructed apparatus will now be described.
I will tell. FIG. 2 shows the addition circuit 50 and the current setting unit 3 of FIG.
0, first and second current sources Q1 and Q2, and signal transmission unit
The circuit composed of 70 as a feedback loop
It is a figure explaining what operates. Now in buffer U1
The output voltage increases by ΔV and V_U1+ ΔV
You. Then, the control voltage at the connection point between the resistors R3 and R5
V_Q1Is V_Q1+ ΔV_Q1To increase. Then Transis
The current I flowing through the resistor R1 due to the effective operation of the _Q1To
I_Q1-ΔI_Q1To reduce. This decrease ΔI_Q1Is for the station
The positive voltage output PS2 + of the power supply PS2 is set to Vcc,
The voltage drop between the emitter and the base in the transistor Q1 is Δ
V_EBIs represented by the following relational expression. {Vcc- (V_U1+ ΔV)} · {R3 / (R3 + R5)} = (I_Q1-ΔI_Q1) · R1 + ΔV_EB (1)

Similarly, the control voltage V _{Q2 at} the connection point between the resistors R6 and R4 increases to V _Q2 + ΔV _Q2 . Then, the transistor Q2 operates effectively, and the current I _Q2 flowing through the resistor R2 is increased to I _Q2 + ΔI _Q2 . This increase ΔI _Q2
Sets the negative voltage output PS2- of the office power supply PS2 to 0 V (G
ND), and the voltage drop between the emitter and the base in the transistor Q2 is represented by ΔV _EB, which is represented by the following relational expression. (V _U1 + ΔV) · {R4 / (R6 + R4)} = (I _Q2 −ΔI _Q2 ) · R2 + ΔV _EB (2)

Then, the sink current of the second current source Q2 increases, and the supply current of the first current source Q1 decreases. Therefore, the difference ΔI _Q2 + ΔI _Q1 is generated via the output capacitor C _L1 through the signal lines L1, L2 or It is supplied from the office power supply PS. Then, a potential difference ΔV _CL1 is generated in the output capacitor C _L1 and an unbalanced current ΔI _CL1 flows. Therefore, the potential Vcp at the intermediate connection point CP drops to Vcp-ΔVcp. Then, the reduced voltage value ΔVcp is fed back to the addition circuit 50 via the feedback resistor R _FB , and lowers the output voltage V _U1 + ΔV of the buffer U1.

Next, the gain of the negative feedback will be described. Now, assuming that the potential Vcp of the intermediate connection point CP is an upper limit of 4 V and a lower limit of 1 V, and is an intermediate state of 2.5 V in an equilibrium state,
It will operate at 2.5 ± 1.5V. Where the feedback resistor R _FB
If There the 100 k.OMEGA, current corresponding to the ± 1.5V becomes ± 15 .mu.A as a current value flowing through the feedback resistor R _FB. Then, this ± 15 μA is sent to the current setting unit 30 via the addition circuit 50, and the first and second current sources Q1, Q2
A non-equilibrium current of about ± 9 mA. Then, the output voltage of the buffer U1 is compared with the voltage value of the neutral level by ±
When the voltage fluctuates by about 1 mV, the first and second current sources Q1, Q
The resistance values R1 to R6 are set so as to generate a non-equilibrium current of about ± 9 mA in R2 (for example, R1 = R2 = 50Ω, R
3 = R4 = 1 kΩ, R5 = R6 = 1.1 kΩ) and ± 1 m
When V is amplified to ± 1.5 V, the feedback gain becomes 1
500 times. Therefore, the potential Vcp of the intermediate connection point CP is also 1
It will be controlled with an accuracy of about mV.

Next, the effect of the 1-bit signal TXIN on the negative feedback loop will be described. In the adder circuit 50, the potential Vcp of the intermediate connection point CP and the 1-bit signal TXIN
Is determined depending on the impedance ratio between the feedback resistor R _FB and the input capacitor Cin. As described above, the feedback resistance R _FB is 100 kΩ, the input capacitor Cin is about 0.5 kΩ when the 1-bit signal TXIN is 30 kBps with the input capacitor Cin being 0.01 μF.
The contribution of the bit signal TXIN is reduced to about 1/200. Therefore, the 1-bit signal TXIN does not substantially affect the negative feedback loop.

FIG. 3 is an explanatory diagram of signals handled by the apparatus of FIG. There are three types of 1-bit signal TXIN: +3.0 V (high level), +2.5 V (neutral level), and +2.0 V (low level). Then, in a steady state, the output signal of the operational amplifier U1 becomes the same as the one-bit signal TXIN, the control voltage V _{Q1 at} the connection point between the resistors R3 and R5 becomes 0.95 / 1.19 / 1.43V, respectively, and the connection voltage at the connection point between the resistors R6 and R4. The control voltages V _Q2 are 1.43 / 1.19 / 0.95V, respectively. Therefore, the first current source, respectively the current I _Q1 flowing through the Q1 5.9 / 10.6 / 15.2mA, the second current source current flowing in Q2 I _Q2 respectively 15.2 / 10.6 / 5.9mA. Therefore, the output current Iout that flows through the signal line L1 is because it is I _Q1 -I _Q2, a 9.3 / 0 / -9.3mA.

FIG. 4 is a waveform diagram of a current sent from the transmitting station TX to the bus of FIG. 10, showing an example in which a DC voltage of 10 V is applied between the signal lines L1 and L2. In the figure, (A) shows the output potential V _U1 of the buffer _U1 , (B)
Is the current I _BUS flowing through the bus, and (C) is the signal lines L1 and L2.
The potential V _{L1, L2} between (D) is the potential V at the intermediate connection point CP.
_CP . The output potential V _U1 of the buffer U1 is initially 50 μ
The S level is 2.5 V, which represents a neutral level, and then 15 V
High level 3V and low level 2V are repeated at a cycle of about μS. Correspondingly, the current I flowing through the bus I
_BUS is 0 mA representing a neutral level for about 50 μS at the beginning, but thereafter becomes high level 10 m at a cycle of about 15 μS.
A and low level -10 mA are repeated. Then, the signal line L1, the potential between L2 V _{L1, L2} about the original 50μS is a 10V representing the neutral level, and then repeats the high level 10.5V and a low level 9.5V with a period of approximately 15 [mu] S. The potential V _CP at the intermediate connection point CP represents the same movements as the output potential V _U1 approximately buffer U1.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention. Compared to the device of FIG. 1, the coupling capacitors C1 and C2 are connected in parallel to the resistors R5 and R6 of the current setting unit 30, respectively. Also provided for suppressing voltage limiter V _LM feedback voltage from the feedback resistor R _FB in summing circuit 50. Here, connecting the diodes D3, D4 as the voltage limiter V _LM in reverse polarity, and connected in parallel the input capacitor Cin and substantially limits the maximum value of the feedback voltage to 0.6V.

The features of the device configured as described above will be described. Compared with the device shown in FIG. 1, the power consumption during normal operation is reduced and the initial current when connected to the bus is suppressed. is there. FIG. 6 is an explanatory diagram of signals handled by the device of FIG. +3.0 V for 1-bit signal TXIN
(High level), + 2.5V (neutral level) and + 2.0V
(Low level). Then, in a steady state, the output signal of the operational amplifier U1 becomes the same as the one-bit signal TXIN, and the control voltage V at the connection point between the resistors R3 and R5.
_Q1 is 0.5 / 1.0 / 1.5V, respectively, and the control voltage V _{Q2 at} the connection point of the resistors R6 and R4 is 1.5 / 1.0 / 0.5V, respectively.
Becomes Therefore, current I _Q1 flowing through the first current source Q1 respectively 0.0 / 3.7 / 9.0 mA, the second current source current flowing in Q2 I _Q2 respectively 9.0 / 3.7 / 0.0mA. Therefore,
Since the output current Iout flowing through the signal line L1 is I _Q1 −I _Q2, it is 9.0 / 0 / −9.0 mA. Compared to the values in FIG. 4, the current I _Q1 flowing through the first current source _Q1 and the second current source Q
It can be understood that the currents _IQ2 flowing through ₂ are small and the power consumption is reduced.

The circuit constants of the current setting section 30 and the first and second current sources Q1 and Q2 are selected as follows. R1 = R2 = 100Ω, R3 = R4 = 1kΩ, R5 =
R6 = 1.5 kΩ, C1 = C2 = 1 μF. That is, due to the coupling capacitors C1 and C2, the resistance values R1 and R2 inside the current source required to make the unbalanced currents I _Q1 -I _Q2 of the first and second current sources 9 mA are doubled, and the current consumption is increased. Is reduced.

FIG. 7 is a waveform diagram showing a transient response when the device of FIG. 5 is connected to a bus to which a DC voltage of 10 V is applied.
At the time of connection, 1 ms has elapsed. First, in the initial state of not being connected to the bus, the output potential V _U1 buffer U1 is 2.5V is neutral level, current I _BUS flowing through the bus is naturally 0 mA. Further, the potential V between the signal lines L1 and L2
_{L1 and L2} are −5 V corresponding to the potential of the station power supply PS2, and the potential V _CP at the intermediate connection point CP is equal to the output potential V _U1 of the buffer U1.

Due to the connection at time T0, the signal lines L1, L
The potentials V _{L1 and L2} between the two rise from -5V to 10V which is equal to the DC applied voltage of the bus, and accompanying this, the intermediate connection point CP
It rises to 16V from the potential V _CP also 2.5V in. Then
3.0V output voltage V _U1 voltage imbalance in response to the buffer U1 in 1-bit signal TXIN corresponds to the high level
, The current I _Q1 supplied from the first current source Q1 is reduced, and the current I _Q2 drawn by the second current source _Q2 is increased, so that an unbalanced current flows and is connected to the signal lines L1 and L2. The delivery of the current to the bus appears as a current I _BUS , where a current of around −5 mA flows for approximately 4 ms. Current I
_The output capacitor CL1 is charged by _BUS , and the potential V _CP at the intermediate connection point _CP also drops from 10V to around 4V.

When the potential V _CP at the intermediate connection point CP reaches 4 V at time T1, the output potential V
_U1 gradually decreases from 3.0V to 2.5V. Correspondingly, the current I _BUS is also gradually reduced from 5 mA to 0 mA, and the output capacitor CL1 is further charged. And at time T2
In the equilibrium state of the neutral level without output potential V _U1 buffers U1 overshoots reaches the 2.5V.

FIG. 8 is a comparison diagram with the response waveform of FIG.
The circuit of the adder circuit 50, to connect the diodes D3, D4 in the opposite polarity, is obtained by adding an input capacitor Cin and substantially voltage limiter V _LM connected in parallel. The response waveform is similar to that of FIG. 7, but the current I _BUS flows for about −15 mA for about 1.5 ms from the time T0 to T1.
Further, the time required from the potential V _CP even 10V at the intermediate connection points CP for lowering to 4V vicinity, 4 of 1.5mS and 7
It fluctuates more rapidly than mS. And at time T2
Indicates that the output potential V _U1 of the buffer U1 reaches 2.5 V,
Overshoot occurs and reaches 2.5V again at time T3. Therefore, the response to the connection becomes oscillatory. In the device shown in FIG. 5, since the capacitors C1 and C2 are added to the current setting unit 30, the response is not oscillating and the settling is performed smoothly. Incidentally, by adding the voltage limiter V _LM, as compared with the case of connecting the device of FIG. 1 to the bus, the smooth transient response.

[0030]

As described above, according to the present invention,
A bus interface device for setting a neutral level current, which could not be reduced below a certain value to zero, and flowing currents of opposite polarities in accordance with H and L levels, by providing first and second current sources, a current setting unit, and a signal There is an effect that the structure can be realized with a simple structure using the input unit. Further, since the current output is output to the signal lines L1 and L2 via the output capacitor C _L1 , it is possible to easily transmit a pulse train current signal to the bus even when various DC voltages are resident on the bus. Further, the addition circuit 50, the current setting unit 30, the first and second current sources Q
1, Q2 and constitute a feedback circuit from the signal transmitting section 70, and the 1-bit input signal TXIN are galvanically isolated by an input capacitor Cin, the signal lines L1, L2 are galvanically isolated by the output capacitor C _L1 Therefore, there is an effect that the output current is stabilized autonomously in the transmitting station TX.

According to the second embodiment shown in FIG. 5, the addition of the coupling capacitors C1 and C2 has the effect of reducing current consumption. The provision of the voltage limiter also has the effect of improving the transient response characteristics when connecting the bus interface device to the bus.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating that a circuit including an adding circuit 50, a current setting unit 30, first and second current sources Q1 and Q2, and a signal transmitting unit 70 of FIG. 1 operates as a feedback loop. .

FIG. 3 is an explanatory diagram of signals handled by the device of FIG. 1;

FIG. 4 is a waveform diagram of a current transmitted from the transmitting station TX to the bus of FIG.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of signals handled by the device of FIG. 5;

FIG. 7 is a waveform diagram showing a transient response when the device of FIG. 5 is connected to a bus to which a DC voltage of 10 V is applied.

FIG. 8 is a comparison diagram with the response waveform of FIG. 7; a voltage limiter V in which diodes D3 and D4 are connected to the addition circuit 50 of the circuit of FIG. 1 with opposite polarities and connected substantially in parallel with an input capacitor Cin; _LM is added.

FIG. 9 is a configuration block diagram of a conventional current transmission type bus interface device.

FIG. 10 is an explanatory diagram of a relationship between a general structure of a common transmission path bus and a bus interface device.

[Explanation of symbols]

 Reference Signs List 10 first current source 20 second current source 30 current value setting unit 40 signal input unit 50 addition circuit 60 signal line connection unit 70 signal transmission unit

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-59-43648 (JP, A) JP-A-4-120930 (JP, A) JP-A 8-125672 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04L 12/28 H04L 25/00

Claims (3)

(57) [Claims] 1. A bus interface device for transmitting a serial 1-bit signal to a pair of signal lines (L1, L2) using three levels of current values of the 1-bit signal: high level, low level and neutral level. The positive voltage output (PS2 +) or the negative voltage output (PS2-) of the office power supply (PS2) having positive and negative voltage outputs for supplying power for operation to the bus interface device.
And a signal line connection part (60) connected to one of the signal lines (L2), and a signal voltage (TXIN) commanded from the outside, and a negative input part (TXIN -) Is a signal input unit (40) connected to the negative voltage output, and a positive input unit (TXIN +) is connected to an input capacitor (Cin).
And the potential at the intermediate connection point (CP) of the signal transmission unit is set to a feedback resistance (R
_FB ), and an addition circuit (50) for adding the signal voltage input through the input capacitor to the signal voltage input thereto, and first to fourth series-connected fourth to fourth voltage dividers for dividing the positive and negative voltage outputs of the office power supply. And a first voltage dividing resistor (R
The connection point between 3) and the second voltage-dividing resistor (R5) is connected to the control terminal of the first current source, and the connection point between the second voltage-dividing resistor and the third voltage-dividing resistor (R6) is connected to this addition circuit. And a connection point between the third voltage dividing resistor and the fourth voltage dividing resistor (R4) is connected to the control terminal of the second current source.
0) and the first and second current sources (Q1, Q2) in which the current to be sent out by the control voltage input to the control terminal increases and decreases differentially.
And the signal transmission unit (70) for connecting an intermediate connection point between the first and second variable current sources and one of the signal lines (L1) via an output capacitor (Cout). A bus interface device. 2. A coupling capacitor (C1, C2) connected in parallel to a second voltage dividing resistor and a third voltage dividing resistor of the current setting unit.
2. The bus interface device according to claim 1, wherein the bus interface device is mounted. 3. A feedback voltage limit circuit (V) which suppresses a signal voltage fed back to said addition circuit via a feedback resistor to a certain voltage or less, or reduces the signal voltage proportionally.
2. The bus interface device according to claim 1, further comprising an LM).