JP3174907B2 - Charge signal equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge signal equalizing device used as a component for an arithmetic unit or a signal processing device using a charge transfer element such as a CCD.

[0002]

2. Description of the Related Art A charge mode operation device that directly performs an operation by a CCD or the like by directly using a charge signal has a low power consumption and is easy to implement an integrated circuit. Despite research on processing, multi-valued logic circuits, fuzzy inference devices, and the like, there are currently no remarkable examples of applied products.

The main cause of this is that the circuit area for realizing the precision required to achieve the purpose is large, and there is no merit in introducing the digital signal processing as compared with digital signal processing especially in applications requiring high precision. .

Another disadvantage of the charge mode operation device is that since the input charge signal packets are directly processed such as addition and division, the fanout of signal processing is extremely restricted. As seen in the examples, it is difficult to construct a free arithmetic device, for example, it requires a signal duplication operation that causes the device to be complicated and large.

[0005] Furthermore, there is also a method in which a charge signal is divided into a plurality of parts by a dynamic splitter by a CCD and processed. Yes (Reference 3)
reference).

Document 1 = Progress in Computer-aided VLS
I design; Vol.3 pp.73-74; Ablex Publishing, Norwoo
d, NJ, USA, 1989 Reference 2 = AMChiang, "A CCD Programmable Signal Pr
ocessor "IEEE journal of Solid-state Circuits, Vo
l.25, No.6 pp.1510-1517 Literature 3 = SSBencuya et.al., "Dynamic Packet Split
ting in ChargeDomain Devices ", IEEE Vol.EDL-3, No.
9, September 1982

As a method for solving these problems, US Pat. No. 5,539,404 proposes a technique for dividing a charge signal packet into two equal parts with high accuracy using a small device. Use for multiplication, AD conversion, and the like has been proposed.

The specific contents are described in IEICE, Vol. E79-
A, No. 2, Feb. 1996, pp217-223
Please refer to.

This technique is an epoch-making method for realizing a great improvement in output accuracy in an operation manner by utilizing a charge dividing device whose division accuracy has been extremely reduced due to miniaturization. Since the number of fan-outs is limited to two, the above-mentioned need for increasing the number of fan-outs has not been sufficiently solved.

[0010]

The present invention extends the basic concept of the above-mentioned U.S. Pat. No. 5,539,404 and uses a high-precision equalizing device which can handle an arbitrary number of divisions by using a charge transfer element. It is intended to propose a configuration method.

[0011]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above situation, and its main invention is to receive one input charge signal and divide it into N signals. A first charge signal splitting device, and N · N output corresponding to N ′ inputs sequentially input to the charge signal splitting device.
A charge signal homogenizer (N, N ') comprising a charge signal adder for adding N' charge signal packets in a charge domain according to a previously planned combination to form N "output charge signals. Is a natural number of 2 or more, and N ″ is a natural number of 3 or more).

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings. Generally, the operation of dividing the charge signal Q into N ′ charge signals qi is expressed mathematically by converting the scalar quantity Q into an N′-dimensional vector (q1, q
2,..., QN ′).

[0013]

(Equation 1)

Here, ei indicates a division error for each output in the case of N ′ equalization, and their sum is Σei = 0 from the law of conservation of electric charge.

The process of receiving N ′ charge signals, dividing them into N charges by the same dividing device, and selectively accumulating the results to form N ″ outputs is performed in the same manner. In other words,

[0016]

(Equation 2) Becomes

Here, as the simplest example, N = N '
= N ", the above matrix Y
Is a square matrix, but since qi are all divided by the same dividing device, the error component eij included in each element is ekj of another k rows (j = 1, 2,...)
N).

Here, the output error of the N dividing device is represented by E1, E
By setting the combination of addition operations as 2,..., EN, for example, the following formulas can be arranged.

[0019]

(Equation 3)

Assuming N = N ′, the output of equation (1) is expressed by equation (3)
Is an operation of multiplying the column vector X by the matrix Y, and more specifically, the operation of applying N to the matrix Y
The inner product of each of the row vectors and the column vector X is calculated to form a new column vector X ′. (X ′) = (Y) · (X) (4)

This inner product operation is synonymous with the operation for obtaining the cross-correlation of two sequences (ei) (E [i + k]) having N elements, but | ei | <1, | E [ Since i + k] | <1 is guaranteed by its definition, the maximum value of their cross-correlation is always smaller than the maximum value of each series, and the following relationship is established. max (| ei |, | Ei |)> max (| Σei · E
[i + k] |) where k = 0, 1,..., N−1, and [i + k] = (i + k−1) mod (N) +1

This result means that the original maximum error of X ′ is always smaller than the original maximum error of X according to equation (4). If equation (4) is considered as a recurrence equation, By repeating the same processing, the error range theoretically converges to zero.

For this reason, the processing of equation (4) is an operation of reducing the original non-uniformity of X to X ′, and will be hereinafter referred to as “uniform processing”.

FIG. 1 shows an example in which a uniforming processing apparatus for executing the processing of the above-mentioned equation (3) is constituted by using a CCD. In FIG. 1, a charge signal splitting device SPL constituted by a CCD dynamic splitter sequentially receives seven input charge signals and further splits each charge into seven. The output charge signal of the SPL is sequentially accumulated in a total of 49 gates hatched by the CCD shift register SR, and when the 49 inputs are completed, S1−S1
The sum is added in the charge region at each of the 13 summing nodes shown in FIG. Eventually, the following seven signals become uniform output signals. S1 + S8; S2 + S9; S3 + S10; S4 + S1
1, S5 + S12; S6 + S13; S7

FIG. 2 shows a case where the portion of the adder in the example shown in FIG. 1 is replaced with a circular shift register using a CCD.
This is a pipeline processing format. In this example, S
The seven outputs of the PL are sequentially added in parallel to a shift register SR1 driven in synchronization with the SPL, and the data is supplied to a seven-stage circular shift register SR2 arranged at the right end and driven in synchronization with the SPL similarly to SR1. Is added. As a result, finally, the same seven outputs as in the example shown in FIG. 1 are formed on the circular shift register.

In the example of FIG. 3, the adder shown in FIG.
This figure shows a format in which a system is arranged to realize faster processing. In this format, the output destination of the SPL is switched to SR1 and SR1 'for every seven inputs, thereby reducing the loss time generated due to the addition of data and realizing almost twice the processing speed.

FIG. 4 shows an example in which the charge signal dividing device is arranged inside the cyclic shift register and the addition operation is performed directly on the cyclic shift register. This operation is
Although essentially the same as the example shown in FIG. 2, this configuration does not require the shift register SR1 and is suitable for implementing a device corresponding to a relatively large division number N with a simpler structure. In this case, the N output charges are directly output from each stage of the cyclic shift register.

FIG. 5 shows an example in which the charge signal equalizing device shown in FIG. 2 is multi-staged.

FIG. 6 shows a configuration in which a feedback circuit F for the output charge signal is provided in the configuration shown in FIG. 2 and the charge signal dividing device is repeatedly used to perform the equalization process stepwise. In FIG. 6, the output charge signal formed on the cyclic shift register SR2 is sequentially supplied as an input to the charge signal splitting device SPL through the feedback circuit F, and the processing of Expression (4) is repeatedly executed.

FIG. 7 shows an example of a charge signal equalizing apparatus similar to FIG. 1 in which six inputs are sequentially supplied to a 10-divided SPL to execute processing. In this device, 60 charge signal packets are aligned on the SR corresponding to a set of inputs, but 6
In order to combine the same number of 0 packets into N number of output packets, the following case is considered. N ″ = 1, 2, 3, 4, 5, 6, 10, 12, 15, 3
0,60. Of these, the case of N ″ = 1, 60 does not match the purpose of the device, and is excluded from consideration. If the method of grouping 60 packets is selected, nine types of division numbers can be selected by the same device. You can see that there is.

FIG. 7 shows an example of the arrangement of packets to be added in the case of N ″ = 5 by hatching. In this case, the selection of N, N ′, and N ″ causes a difference in the efficiency of the equalization processing. However, uniformity is achieved.

FIG. 8 shows the result of Monte Carlo simulation for confirming the effect of reducing the error based on equation (4) when the charge signal equalizing apparatus shown in FIG. 1 is used.

In FIG. 8, the horizontal axis represents each element | ei of X and Y.
|, The ratio of the maximum value of the original absolute value of X ′ when the maximum value of | Ei | is 100%, and the vertical axis represents the combinations of 4000 randomly selected (ei) and (Ei). The corresponding cumulative frequency distribution of occurrence frequency is shown.

In this simulation, N is set to 7, and as parameters, the maximum values of the elements constituting (ei) and (Ei) are selected and shown as 25%, 50%, and 100%. 50% corresponds to the maximum value of | ei |, | Ei | being 0.5, and within this range, ei, E
It was assumed that the value of i was determined with equal probability.

As can be seen from FIG. 8, the maximum value is 100%, that is, the partial signal value formed by division is 0- (2/7).
Even in an extreme case where the dispersion is performed within the range, the maximum error can be reduced to less than half by one equalizing process in most cases. The effect of reducing the error is that the individual division accuracy is 50% and 25%. It is clearly shown that there is a tendency to increase significantly by improving the percentage.

In the simulation shown in FIG. 8, ei and Ei are independent sequences. However, when the same charge signal dividing device is used in a multiplexed manner, Ei = ei.
Since the autocorrelation becomes a problem, the effect of the equalization processing is small, but as shown in FIG. 9, the error can be reliably reduced as described above.

[0037]

[Table 1]

Table 1 shows that N = 5 according to the configuration shown in FIG.
8 shows an example of a process in which eight stages of the charge signal equalizing devices are connected in series, and errors are reduced stepwise by multi-stage processing. In Table 1, the symbol p indicates the number of repetitions of the equalization processing, and the numerical value shown in the column of p = 0 indicates the value of five input charge packets. Is improved up to about eight digits.

[0039]

[Table 2]

Table 2 shows an example in which the same charge signal equalizing device is used eight times in the device shown in FIG. 6 to perform the equalizing process. It can be seen that the processing is more effective in reducing errors.

[0041]

As is apparent from the above description, according to the present invention, it is possible to realize an operation of dividing a signal corresponding to an arbitrary division number N into N equal parts with small power consumption by using a small-sized integrated circuit. it can.

For this reason, it is possible to perform a highly accurate N-division operation on N including a prime number other than 2 which has been conventionally difficult to realize.

Also, since the accuracy of division can be adjusted over a wide range depending on the operation mode of the apparatus, even if the same apparatus is used, a flexible operation which cannot be expected with the conventional technology can be performed.

[Brief description of the drawings]

FIG. 1 shows a charge signal equalizing apparatus according to an embodiment of the present invention,
FIG. 4 is a configuration diagram configured using D.

FIG. 2 shows a charge signal equalizing apparatus according to another embodiment of the present invention.
FIG. 2 is a configuration diagram in which a portion of the adder in FIG. 1 is replaced with a cyclic shift register using a CCD and configured as a pipeline processing format.

FIG. 3 is a configuration diagram of a charge signal equalizing apparatus according to still another embodiment of the present invention, in which two systems of the adder of FIG. 2 are arranged to realize higher-speed processing.

FIG. 4 is a configuration diagram in which a charge signal dividing device used in the configuration of the present invention is arranged inside a cyclic shift register and configured to directly execute an addition operation on the cyclic shift register.

FIG. 5 is a configuration diagram in which the charge signal equalizing device shown in FIG. 2 is configured in multiple stages.

FIG. 6 shows a configuration in which a feedback circuit F for an output charge signal is provided in the configuration of the charge signal equalization device shown in FIG. 2, and the charge signal division device is repeatedly used to perform the equalization process stepwise. FIG.

FIG. 7 is a configuration diagram of a charge signal equalizing device similar to FIG. 1 for sequentially performing processing by sequentially supplying six inputs to a 10-divided SPL.

8 is a graph showing the result of Monte Carlo simulation for confirming the effect of reducing errors when the charge signal equalizing apparatus shown in FIG. 1 is used in multiple stages.

9 is a graph showing Monte Carlo simulation results for confirming the effect of reducing errors when the charge signal dividing device shown in FIG. 1 is repeatedly used by a feedback circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-53-129945 (JP, A) JP-A-54-152850 (JP, A) Patent 2599679 (JP, B2) JP-B-56-37640 (JP, A) B2) Japanese Patent Publication No. 1-129945 (JP, B2) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06G 7/14 G06G 7/16

Claims (7)

(57) [Claims] 1. An input charge signal is received, and is
A first charge signal dividing device that divides the charge signal dividing device into N 個 N ′ number of charge signal packets sequentially output to the charge signal dividing device; A charge signal addition device for adding N 'output charge signals in the charge region according to the combination to form N "output charge signals. However, N and N' are natural numbers of 2 or more, and N". Is a natural number of 3 or more. 2. The charge signal equalizing device according to claim 1, wherein N = N ″. 3. The charge signal equalizer according to claim 1, wherein two or more charge signal equalizers are connected in series, and an output of the preceding charge signal equalizer is sequentially supplied as an input to a subsequent charge signal equalizer.
Or the charge signal equalizing device according to 2. 4. An output signal of the charge signal equalizing device,
The charge signal equalizing device according to any one of claims 1 to 3, further comprising a charge transfer circuit that sequentially feeds back as an input to the charge signal equalizing device, wherein one charge signal equalizing device is repeatedly used. 5. The charge signal equalizing device according to claim 1, wherein a circular shift register having at least one charge addition gate is used as said charge signal addition device. 6. The charge signal equalizing device according to claim 1, wherein the number of output charge signals is adjusted by changing a combination of addition operations performed by the charge signal addition device. 7. A second charge signal splitting device for splitting an input charge signal into N ′ signals; and N ′ of the second charge signal splitting device.
7. A charge signal equalizing device comprising: the charge signal equalizing device according to claim 1;