JP3171242B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a DRAM (Dynamic Random Access Memory).
Access Memory).

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for semiconductor memory devices to be reduced in cost and increased in capacity. In order to satisfy these requirements, it is most effective to increase the capacity per device size (chip size). Therefore, the cell size of the semiconductor memory device tends to be further reduced. Hereinafter, a DRAM which is one of the semiconductor memory devices will be considered.

[0003] A DRAM includes a combination of one transistor and one capacitor. The required capacitance of the capacitor is calculated based on the capacitance of the bit line connected to the transistor. This required capacitor capacity does not change much as the cell size is reduced.

Since the capacitance of a capacitor is inversely proportional to the thickness of a capacitance film, the smaller the film thickness, the greater the capacitance. Since the thickness of the capacitor film is determined based on the leak current of the capacitor film, it cannot be reduced to a certain level or less.

The capacitance of a capacitor is proportional to the area (capacitor surface area) of a portion where a capacitor lower electrode and a capacitor upper electrode of a capacitor oppose each other via a capacitance film. Therefore, it is more difficult to secure the surface area of the capacitor as the cell size becomes smaller. Generally, a capacitor has a three-dimensional structure in order to increase the surface area of the capacitor. As the three-dimensional structure of the capacitor, for example, a capacitor having a very thick capacitor lower electrode (simple thick film stack capacitor), a capacitor having a cylindrical capacitor lower electrode (cylinder stack capacitor), and the like can be considered. ing. Hereinafter, these manufacturing methods will be described.

First, a method of manufacturing a conventional simple type thick film stacked capacitor will be described. As shown in FIG. 5A, an element isolation oxide film 2, a diffusion layer region 3, a gate electrode 4,
A capacitor contact hole 6 is formed on the semiconductor substrate 1 having the bit lines 5 by using a photoresist pattern 7 formed by photolithography as a mask. After removing the photoresist pattern 7, as shown in FIG. 5 (b), after forming a phosphorus-doped polysilicon film of, for example, 0.9 μm, the photoresist pattern 8 formed using the photolithography technique is used as a mask. Then, the capacitor lower electrode 9 is formed. After removing the photoresist pattern 8, as shown in FIG.
For example, a silicon nitride film having a thickness of about 7 nm
0, and a phosphorus-doped polysilicon film is formed to a thickness of 0.1.
A film of about 15 μm is formed to form the capacitor upper electrode 11. As a result, a capacitor for holding electric charges is formed.

Next, a method of manufacturing a conventional cylinder type stack capacitor will be described. As shown in FIG. 6A, the isolation oxide film 2, the diffusion layer region 3, the gate electrode 4,
And a capacitor contact hole 6 using a photoresist pattern 7 formed on the semiconductor substrate 1 having the bit lines 5 by photolithography as a mask.
The hole is opened. After removing the photoresist pattern 7, FIG.
As shown in (b), after forming a phosphorus-doped polysilicon film having a thickness of about 0.15 μm and a PSG film having a thickness of about 0.8 μm, a photoresist pattern 8 formed using a photolithography technique is used as a mask. A core oxide film 12 and a capacitor lower electrode 9 are formed. After removing the photoresist pattern 8, as shown in FIG.
After a phosphorous-doped polysilicon film is formed on the entire surface to a thickness of about 0.07 μm, the entire surface is etched back to form a sidewall electrode 13. Next, as shown in FIG. 6D, the core oxide film 12 is removed. Then, as shown in FIG. 6E, for example, a silicon nitride film of about 7 nm
Is formed, and for example, a phosphorus-doped polysilicon film is formed to a thickness of about 0.15 μm to form the capacitor upper electrode 11. As a result, a capacitor for holding electric charges is formed.

[0008]

Referring to FIG. 7 [0008], in a simple thick-film stacked capacitor, the capacitor bottom electrode 9 is provided with a sharp portion P _9. When a voltage is applied between the capacitor upper electrode 11 and the capacitor lower electrode 9, an electric field (arrow E) concentrates on the portion P ₉ , and the capacitance film 10 is formed between the capacitor upper electrode 11 and the capacitor lower electrode 9.
Leakage current flows through the device. This leak current is a major factor that degrades the charge retention characteristics of the capacitor.

[0009] With reference to FIG. 8, in the cylinder type capacitor, there is an acute part P ₁₃ to the side wall electrodes 13.
When a voltage is applied between the capacitor upper electrode 11 and the side wall electrode 13, an electric field (arrow E) concentrates on the portion P ₁₃ , and a leakage current flows between the capacitor upper electrode 11 and the side wall electrode 13 via the capacitance film 10. Flows. Then, the leakage current degrades the charge retention characteristics of the capacitor.

[0010] To solve this problem, Japanese Patent Laid-Open No. 4-328859 discloses a method in which a sharp portion formed during a DRAM manufacturing process is rounded off by isotropic etching. According to this method, since the sharp portion is eliminated, the electric field is not locally concentrated.

[0011] However, in the isotropic etching, not only sharp corners are rounded, but also the height of the stack is considerably shortened.

In recent years, as the cell size has been reduced, the area at the top of the stack has been reduced. For this reason, when securing a large surface area for the above-described purpose, it is more reasonable to secure a wider side surface than an upper surface. For example, in the case of a simple thick film stack capacitor having a bottom size of 0.25 μm × 0.75 μm and a height of 0.90 μm, the area of the top surface is 0.188 μm ² , while the surface area of the side surface is 1.88 μm ² . It is about 8 μm ² . When 0.1 μm is etched in the height direction by isotropic etching so as to round an acute portion, the surface area of the entire stack is reduced by about 0.2 μm ² . This decreasing area is larger than the area of the upper surface. In the case of the cylinder type stack, since it has an inner wall surface in addition to the outer wall surface, the surface area is significantly reduced when isotropic etching is performed. In addition, the rounding of the sharp corners also reduces the surface area.

As described above, according to the isotropic etching, although the electric field can be prevented from being locally concentrated on the lower electrode of the capacitor, the problem that the surface area of the lower electrode of the capacitor is reduced is secondarily caused.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which an electric field is not locally concentrated on a capacitor lower electrode and the surface area of a stack capacitor lower electrode is large.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of rationally manufacturing the above semiconductor device.

[0016]

According to the present invention, there is provided a semiconductor device having a capacitor having first and second electrodes opposed to each other via a capacitance film, wherein the first electrode has a cylindrical shape. An additional capacitor film that is at least thicker than the capacitor film between the upper surface including the edge of the first electrode and the capacitor film to reduce electric field concentration on the edge of the electrode. Is obtained.

According to the present invention, the additional capacitance film has a thickness such that the electric field applied to the laminated film with the capacitance film is 0.75 times or less the electric field applied to the single capacitance film. The semiconductor device is obtained.

[0018]

According to the present invention, the first electrode includes:
The semiconductor device having the side surface having a larger surface area than the upper surface is obtained.

According to the present invention, there is further provided the semiconductor device, wherein the additional capacitance film includes any one of silicon oxide, silicon nitride, and tantalum oxide.

[0021]

[0022]

According to the present invention, a step of forming a first conductive film on a semiconductor substrate in which a diffusion layer region, a gate electrode, a bit line, and a connection hole are formed; Forming a stop film, forming a buffer film on the etch stop film, patterning the buffer film, and forming a first insulating film on a semiconductor substrate having the patterned buffer film Removing the exposed etch stop film while leaving the exposed side as a sidewall insulating film only on the side of the buffer film patterned by etching back the first insulating film; Forming a first electrode by etching a part of the buffer film, the etch stop film, and the first conductive film using a film as a mask; Forming a second insulating film as a capacitance film on the semiconductor substrate on which the first electrode is formed, and forming a second conductive film as a second electrode on the capacitance film. And a method for manufacturing a semiconductor device characterized by having the following. In the method for manufacturing a semiconductor device, the first conductive film may be formed such that the surface area of the side surface of the first electrode is larger than the surface area of the upper surface.

[0024]

In the semiconductor device according to the present invention, since the upper surface near the acute portion of the capacitor lower electrode is covered with an insulating film thicker than the capacitor film, the electric field concentration at the acute portion is reduced.

Further, according to the present invention, since the electric field concentration is reduced, the capacitance film can be further thinned.

Further, according to the present invention, since the isotropic etching for rounding the sharp portion is not performed after the formation of the capacitor lower electrode, the surface area of the capacitor lower electrode is not greatly reduced.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described below with reference to the drawings.

[First Embodiment] Referring to FIG. 1, a DRAM which is a semiconductor device according to a first embodiment of the present invention includes an element isolation oxide film 2, a diffusion layer region 3, a gate electrode 4, and a bit line 5. A capacitor lower electrode 9 electrically connected to the diffusion layer region 3 is provided on the semiconductor substrate 1 having
The buffer insulating film 14 is provided on the upper surface of the lower electrode 9. Further, the capacitance film 10 and the capacitor upper electrode 11
have.

With reference to FIGS. 2A to 2C, a method of manufacturing a simple type thick film stacked capacitor will be described.

First, as shown in FIG. 2A, a photoresist pattern 7 formed by photolithography on a semiconductor substrate 1 having a diffusion layer region 3, a gate electrode 4 and a bit line 5 is masked. A connection hole 6 reaching the diffusion layer region 3 is opened. The connection hole 6 is, for example, 0.22 μm at the top and 0.15 μm at the bottom.
It has a diameter of the order of m. After removing the photoresist pattern 7, as shown in FIG.
After a phosphorus-doped polysilicon film 19 having a thickness of about m and a silicon oxide film having a thickness of, for example, about 0.1 μm are formed, buffer insulation is performed at intervals of, for example, about 0.2 μm using a photoresist pattern 8 formed by photolithography as a mask. The film 14 is formed. After removing the photoresist pattern 8, as shown in FIG. 2C, the phosphorus-doped polysilicon film 19 is etched using the buffer insulating film 14 as a mask to form the capacitor lower electrode 9. Then, for example, a silicon nitride film of about 8 nm
By forming a phosphorus-doped polysilicon film of about 0.15 μm as the capacitor upper electrode 11, the capacitor structure shown in FIG. 1 can be obtained.

In this embodiment, the phosphorus-doped polysilicon film 19 is patterned after the removal of the photoresist pattern 8. However, the phosphorus-doped polysilicon film is continuously formed after the silicon oxide film is patterned without removing the photoresist film. 19 patterning may be performed.

In this embodiment, the buffer insulating film 1
4 is a silicon oxide film, but there is no problem if a film having a higher dielectric constant than the silicon oxide film, for example, a silicon nitride film or a tantalum oxide film is used to increase the accumulated charge capacity. Similarly, the capacitance film 10 is a silicon nitride film, but there is no particular problem even if a tantalum oxide film or the like is used.

[Second Embodiment] Referring to FIG. 3, a DRAM which is a semiconductor device according to a second embodiment of the present invention includes an element isolation oxide film 2, a diffusion layer region 3, a gate electrode 4, and a bit line 5. A capacitor lower electrode 9 electrically connected to the diffusion layer region 3 is provided on the semiconductor substrate 1 having
On the protruding portion of the capacitor lower electrode 9, a side wall insulating film 17 is provided. Further, it has a capacitance film 10 and a capacitor upper electrode 11.

Referring to FIGS. 4 (a) to 4 (f), a method for manufacturing a cylinder type stacked capacitor will be described.

First, as shown in FIG. 4A, a photoresist pattern 7 formed by photolithography on a semiconductor substrate 1 having a diffusion layer region 3, a gate electrode 4, and a bit line 5 is masked. For example, the upper part reaching the diffusion layer region 3 is, for example, 0.22 μm,
A connection hole 6 of about 0.15 μm is formed at the bottom.

Next, as shown in FIG. 4B, a phosphorus-doped polysilicon film 19 of, for example, about 0.9 μm is formed on the entire surface.
After forming a silicon oxide film 15 of, for example, about 0.02 μm and an amorphous silicon film of, for example, about 0.3 μm, the buffer silicon film 16 is patterned using the photoresist pattern 8 formed by using the photolithography technique as a mask. .

After the photoresist pattern 8 is removed, for example, a silicon oxide film (not shown) is formed on the entire surface to a thickness of about 0.07 μm, and then the entire surface is etched back to perform patterning as shown in FIG. The structure is such that the side wall insulating film 17 remains only on the side wall of the formed amorphous silicon film (buffer silicon film 16). The silicon oxide film 15 exposed at this time is removed when the entire surface of the silicon oxide film (not shown) is etched back.

Then, as shown in FIG. 4D, the phosphorus-doped polysilicon film 19 and the buffer silicon film 16 are etched using the side wall insulating film 17 and the silicon oxide film 15 as a mask. At this time, as an etching gas,
Etching is performed using a mixed gas of chlorine and hydrogen bromide.

Next, as shown in FIG. 4E, when the silicon oxide film 15 under the buffer silicon film 16 is exposed, the etching gas is switched to carbon tetrachloride, and the silicon oxide film 15 is etched. Do.

Next, as shown in FIG. 4F, when the exposed silicon oxide film 15 is completely removed, the etching gas is switched again to a mixed gas of chlorine and hydrogen bromide.
The phosphorus-doped polysilicon film 19 is etched to obtain the shape of the capacitor lower electrode 9 as shown in FIG. Then, for example, a silicon nitride film of about 8 nm
By forming a phosphorus-doped polysilicon film of about 0.15 μm as the capacitor upper electrode 11, the capacitor structure shown in FIG. 3 can be obtained.

In this embodiment, the side wall insulating film 17 is a silicon oxide film, but a film having a higher dielectric constant than the silicon oxide film, for example, a silicon nitride film or a tantalum oxide film is used to increase the accumulated charge capacity. There is no problem.
Similarly, the capacitance film 10 is a silicon nitride film, but there is no particular problem even if a tantalum oxide film or the like is used.

[0042]

Since the semiconductor device according to the present invention has an additional capacitance film between the surface including the edge of the first electrode and the capacitance film, the electric field is locally concentrated on the lower electrode. And the surface area of the lower electrode of the stack capacitor is large.

That is, since the electric field concentration at the acute angle portion of the electrode is reduced, the leak current through the capacitor film is reduced, and the withstand voltage of the capacitor film is improved.

Further, since the electric field concentration is reduced, the capacity film can be further thinned, so that an increase in the accumulated charge capacity is expected.

Further, according to the present invention, since the isotropic etching for rounding the sharp portion is not performed after the formation of the capacitor lower electrode, the surface area of the capacitor lower electrode does not greatly decrease, and therefore, the amount of accumulated electric charge greatly decreases. Can be avoided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;

FIGS. 2A to 2C are views for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention;

FIGS. 4A to 4F are diagrams for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention; FIGS.

FIGS. 5A to 5C are views for explaining a conventional method for manufacturing a semiconductor device having a simple thick film stacked capacitor.

FIGS. 6A to 6E are views for explaining a method for manufacturing a semiconductor device having a conventional cylinder-type stacked capacitor.

FIG. 7 is a diagram showing electric field concentration occurring at a capacitor lower electrode of a conventional semiconductor device having a simple thick film stack capacitor.

FIG. 8 is a diagram showing electric field concentration occurring at a capacitor lower electrode of a conventional semiconductor device having a cylindrical stack capacitor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation oxide film 3 Diffusion layer area 4 Gate electrode 5 Bit line 6 Capacitor contact hole 7, 8 Photoresist pattern 9 Capacitor lower electrode 10 Capacitance film 11 Capacitor upper electrode 12 Core oxide film 13 Side wall electrode 14 Buffer insulation Film 15 silicon oxide film 16 buffer silicon film 17 sidewall insulating film 19 phosphorus-doped polysilicon film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (6)

(57) [Claims] 1. A first and a second facing each other via a capacitance film.
And a capacitor comprising: a first electrode, wherein the first electrode comprises:
In the semiconductor device exhibiting cylinder shape, the electrode between the upper surface and the capacitor film including the edge of the first electrode
At least the capacitance film for reducing electric field concentration on the edge of
A semiconductor device having an additional capacitance film thicker than a film thickness . 2. The electric field applied to the laminated film with the capacitor film is 0.7% of the electric field applied to the single film of the capacitor film.
2. The semiconductor device according to claim 1, having a film thickness that is five times or less. 3. The semiconductor device according to claim 1, wherein the first electrode has a side surface having a larger surface area than an upper surface. 4. The semiconductor device according to claim 1, wherein said additional capacitance film includes one of silicon oxide, silicon nitride, and tantalum oxide. 5. A step of forming a first conductive film on a semiconductor substrate on which a diffusion layer region, a gate electrode, a bit line, and a connection hole are formed, and forming an etch stop film on the first conductive film. Performing, forming a buffer film on the etch stop film, patterning the buffer film, forming a first insulating film on a semiconductor substrate having the patterned buffer film, Removing the exposed etch stop film while leaving as a sidewall insulating film only on the side of the buffer film patterned by etching back the first insulating film; and using the sidewall insulating film as a mask. Forming a first electrode by etching a portion of the buffer film, the etch stop film, and a part of the first conductive film, Forming a second insulating film as a capacitance film on the semiconductor substrate on which the first electrode is formed, and forming a second conductive film as the second electrode on the capacitance film. Semiconductor device manufacturing method. 6. The method according to claim 5, wherein the first conductive film is formed such that a surface area of a side surface of the first electrode is larger than a surface area of the upper surface.