JP3171041B2 - Diversity receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diversity receiver used for transmitting digital data such as a car telephone.

[0002]

2. Description of the Related Art First, the technical background of the present invention will be described.

A transmission path having intersymbol interference (hereinafter referred to as ISI) will be described. When a transmission information sequence {In} is transmitted to the transmission line, the transmission information sequence receives ISI and additive white Gaussian noise (hereinafter, AWGN) wn on the transmission line, and a reception signal rn on the reception side. Becomes Here, the suffix n represents time. This r
n can be expressed by equation (1).

[0004]

(Equation 1)

Here, L is the transmission line memory length, c i, n is the i-th tap coefficient at time n that constitutes the transmission line characteristics, and if no ISI exists, L = 0 and c
Expressed as n. FIG. 11 shows a model (L = 2) of a transmission line having ISI. In is input to a delay element such as a shift register, multiplied by a tap coefficient, and added. Here, components other than c0, n are ISI components. Here, when coding is introduced, In is a coded sequence.

[0006] "Maxmum-likelihoo" by GD Forney, Jr.
d sequence estimation of digitalsequence in the pr
esence of intersymbol interference ”(IEEE Trans.
Information Theory, vol.IT-18, pp.363-378, May 197
The description of the maximum likelihood sequence estimation using the Viterbi algorithm shown in 2) will be given sequentially.

The state and trellis diagram will be described.
The state indicates a state. The received signal rn includes In-1 and In-2 having coefficients of c1, n and c2, n. That is, in order to estimate the current transmission sequence, it is necessary to consider the past transmission sequence. This combination of the past transmission sequences corresponds to a state, and if the delay circuit has one symbol period (L = 1), there are two types of state "0" and state "1". As shown in FIG. If the period is (L = 2), four types of state “00”, state “01”, state “10” and state “11” are prepared. As described above, the state is expressed by a combination of transmission sequences, and the memory length of the Viterbi algorithm is represented by V
(Usually V = L, but in the present invention, V
Is an arbitrary value. That is, L = 0 when V> 0), and the states xn and xn− at time n and time n−1.
1 can be expressed by equations (2) and (3), respectively.

[0008]

(Equation 2)

That is, among the two states, V-1 transmission sequences from In-1 to In-V + 1 have the same value. By utilizing this property, the trellis diagram of FIG. 12 can be created. As described above, when the alphabet size (the number of points that the signal can take) is U and the signal takes binary values of 0 and 1 (U =
2), the number M of states is M = U ^v = 2 ² = 4. That is, in this example, In is set to 0, 1 and V is set to 2, so that xn forms four states of 00, 10, 01, and 11 to form a trellis. Also, the line segment xn in the trellis diagram
/ Xn-1 is called a branch. This branch is uniquely from In to In-
Determine the V transmission sequence. Therefore, when V is set to L, the estimated value (replica) of rn represented by the equation (1) can be uniquely estimated.

Next, the branch metric will be described. The branch metric is the error power of the received signal and the replica of the received signal reproduced in each state. This error power is related to the state occurrence probability. Estimated value In-i of transmission sequence from In to In-V determined by branch xn / xn-1
[Xn / xn-1] (0 ≦ i ≦ L) to rn replica hn
[Xn / xn-1] can be created as follows.

[0011]

(Equation 3)

Here, the estimated value of ci, n is gi, n.
The difference en [xn / xn-1] between the actual received signal rn and the replica hn [xn / xn-1] determined by the branch xn / xn-1 expresses a certainty, and this en [xn / xn-1] 2
The squared power is called a branch metric En [xn / xn-1] and can be expressed as follows.

[0013]

(Equation 4)

That is, the branch metric En [xn / xn-1] can be uniquely determined from the branch xn / xn-1.

Next, the path metric will be described. The path metric is the sum of all branch metrics corresponding to states on the surviving sequence path.
That is, the sum of the branch metrics En [xn / xn-1] uniquely determined by the branches xn / xn-1 for all the branches is called a path metric, and the path metric Fn [xn / xn- at time n]. 1] can be expressed as follows.

[0016]

(Equation 5)

The path metric Fn [xn / xn-1] is
It can be calculated by sequential processing as shown in equation (6). That is, when the current time is n, the “probability of the current received signal” is the branch metric En [xn / xn−
1], the “probability calculated and stored for the surviving sequence connected to the past state” is the path metric F
n-1 [xn-1 / xn-2] and "the likelihood calculated for the surviving sequence connected to the current state" correspond to the path metric Fn [xn / xn-1].

Next, the ACS processing will be described. ACS
Is an abbreviation for Add-Compare-Select.
The addition processing is an operation of adding a branch metric to the path metric shown in the above equation (6). The comparison process is an operation of comparing U metrics because a path metric having an alphabet size U (U = 2 when the transmission signal is 0 or 1) is created for each state. For the entire maximum likelihood sequence estimation, S (= M × U) path metrics are created because there are U branches in M states. The selection processing is an operation of selecting a path metric having the smallest path metric for each state from the result of the comparison processing in each state, and selecting a sequence corresponding to the selected path metric as a surviving path.

For example, FIG. 12 shows an example of a trellis lattice. Two branches are input to this trellis lattice. First, the addition processing of the equation (6) is performed on these two branches. Next, a smaller branch is selected by comparing the two path metrics. This is comparison selection, a path connected to the selected branch is called a surviving path, and a path not selected is rejected.

The above is the description of the maximum likelihood sequence estimation using the Viterbi algorithm. A detailed description of the operation based on the block diagram will be described later. Thus, GD Forney
The maximum likelihood sequence estimation indicated by (1) operates as follows when a received signal at a symbol rate is input. Based on the estimated transmission path characteristics, the received signal is input, and the `` probability '' for each `` state '' which is a combination of transmission sequences that may occur and the `` surviving sequence '' connected to the past `` state '' On the other hand, the Viterbi which performs ACS processing for all states based on the “probability” already calculated and stored, as a “surviving sequence”, of a sequence most likely to occur for each current “state”. After inputting all input signal sequences using the algorithm, the only remaining "surviving sequence"
(Maximum likelihood sequence) is determined as the transmitted signal sequence.

Next, estimation of transmission path characteristics will be described.
Estimation of transmission path characteristics is an operation of modeling an actual transmission path as shown in FIG. 11 and estimating tap coefficients of an estimated transmission path model as shown in FIG. First, a method of estimating transmission path characteristics from a known sequence called a training sequence will be described. When there is a sufficiently random training sequence of length K, the estimated value gi of the tap coefficient ci can be calculated as equation (7).

[0022]

(Equation 6)

Here, * indicates a complex number conjugate. However,
If the training sequence is not sufficiently random, it is necessary to solve a deterministic normal equation (approximate Winer-Hopf equation). When the tap coefficient ci, n changes with time, it is necessary to use an adaptive algorithm such as an LMS (Least Mean Square) algorithm or an RLS (Recursive Least Squares) algorithm.

Hereinafter, the LMS algorithm will be described. An LMS algorithm is one of the algorithms for sequentially calculating an approximate solution of the Wiener solution. This adjusts the tap coefficient so that the square error value of the received signal and its replica is minimized, and can be expressed as follows.

[0025]

(Equation 7)

Here, in particular, δ is a step size, In
Is called a reference input. Here, by setting L = 0, it is possible to correspond to a transmission line without ISI. The LMS algorithm does not have an AFC function by itself. here,
AFC stands for Auto-Frequency-Control (automatic frequency control).
A).

The fading will be briefly described. Fading means that the envelope and phase of the received wave fluctuate randomly due to reflection, diffraction, and scattering of radio waves due to the surrounding terrain and buildings. Particularly, in land mobile communication, fading called Rayleigh fading occurs. In this fading, the phase has a uniform distribution, and the envelope has a Rayleigh distribution. The envelope power may be lower than the average power by about 20 dB or 30 dB.
This phenomenon is called fade, and the bit error rate characteristic may be significantly deteriorated during the fade.

Next, the diversity receiver will be described. The diversity receiver prepares a plurality of antennas (here, N antennas) and determines data by combining received signals of N systems. For example, in a receiver having a configuration as shown in FIG. 14, there are N antennas, and N received signals can be obtained. In diversity reception, N antennas are set so that the noise component and the envelope component of the N-system received signals are as uncorrelated as possible. Under the above-described fading, when the fluctuations in the envelope power of the N antennas are made independent, the probability that the N antennas fade simultaneously can be significantly reduced. This is the effect of diversity under fading.

Here, a type of diversity called post-detection combining diversity will be described. In FIG. 14, it is assumed that N = 2, the received signals received from the two antennas 1 and 2 are r ⁽¹⁾ n and r ⁽²⁾ n, respectively, and the value normalized by the power is R ^{(1 )} n and R ⁽²⁾ n. Further, when the envelope powers of the two systems of received signals are a ⁽¹⁾ n and a ⁽²⁾ n and the carrier phases are γ ⁽¹⁾ n and γ ⁽²⁾ n, The maximum ratio combining method will be described. In the equal gain combining method, a combined signal is created as Expression (10) regardless of the envelope power, and in the maximum ratio combining method, the combined signal is weighted by the envelope power as Expression (11) and output.

[0030]

(Equation 8)

That is, in the maximum ratio combining method, when the reception level of one of the antennas is small, the weight for the reception level is reduced, and the influence of noise can be suppressed.

Next, the carrier phase synchronization circuit will be described. For simplicity, it is assumed that the information to be transmitted is two-phase PSK. As shown in FIG. 13, the carrier phase synchronization circuit doubles the received signal. That is, the received signal rn is converted to cnIn
+ Wn, the squared value is

[0033]

(Equation 9)

## EQU1 ## Here, In = exp (jΘn) (Θn =
0, π) and cn = Cn exp (jγn) (where Cn is a positive number), the relationship of equation (13) holds.

[0035]

(Equation 10)

Here, exp (2jΘn) = 1 was used. At this time, by taking the average of rn ^2, the average of rn ² becomes Cn ²
Asymptotic to the average of exp (2jγn). Assuming now that the average carrier phase angle of cn ² In ² is β, γn is β / 2 or β / 2 +
π. This phenomenon is called phase uncertainty.
Usually β / 2 or β / 2 to eliminate this phase uncertainty
The selection of + π is often estimated using a known transmission sequence or the like in advance.

Next, the soft decision will be briefly described. One type of coding is convolutional coding, and the Viterbi algorithm is used for the optimal decoding method of convolutional codes as in the case of maximum likelihood sequence estimation. For the input of this Viterbi algorithm, it is better to input data (such as 0.1 or 0.9) (such as soft decision) that includes reliability, instead of binary quantized data (called hard decision) such as 0 or 1. It shows good error rate characteristics. Therefore, it is desirable to use soft decision data for decoding the convolutional code.

Next, an example of a conventional diversity receiver will be described. FIG. 14 is a block diagram for explaining the operation of the diversity receiver of the first conventional example. This example uses the maximum ratio combining diversity described in "Basics of Mobile Communication" supervised by Okumura et al. (IEICE 1986). It will be realized.

In the drawing, 1-1 to N are antenna reception signal input terminals, 33-1 to N are phase synchronization information input terminals of antenna reception signals, and 34-1 to N are the antenna reception signal input terminals 1-1 to 1-N. N, 35-1 to 35-N are the antenna reception signal input terminals 1-.
1 to N, and phase detection circuits connected to the phase synchronization information input terminals 33-1 to 3-N, respectively. 36-1 to 36-N are the phase detection circuits 35-1 to 35-N and the antenna reception signal input terminal 1-1. To N, 37-1 to
N is an amplification circuit to which the outputs of the phase shift circuits 36-1 to N and the envelope detection circuits 34-1 to N are respectively input;
Reference numeral 38 denotes an addition circuit that adds the outputs of the amplifier circuits 37-1 to 37-N, and reference numeral 39 denotes a determination circuit that determines the output of the addition circuit 38 and outputs a determination value of the transmitted data. Note that 6
Is a judgment value output terminal.

FIG. 13 is a block diagram showing the inside of the phase detection circuits 36-1 to 36-N. In the figure, reference numeral 40 denotes a signal input terminal connected to the antenna reception signal input terminals 1-1 to N; The phase synchronization information input terminals 33-1 to 3-1
N is a phase synchronization information input terminal, 42 is a multiplying circuit, 43 is an averaging circuit, 44 is a frequency dividing circuit, 45 is a phase uncertainty removing circuit, and 46 is a phase information output terminal.

Next, the operation will be described. Each of the envelope detection circuits 34-1 to 34-N is connected to each of the antenna input terminals 1-
It detects and outputs the envelope power from the received signals input from 1 to N. Using the phase synchronization information from the phase synchronization information input terminal 41, the phase detection circuits 36-1 to 36-N detect and output the phases of the reception signals input from the antenna input terminals 1-1 to N.

The phase shifters 35-1 to 35-N shift the phases of the received signals input from the signal antenna input terminals 1-1 to N according to the phases output from the phase detectors 36-1 to 36-N.
Output. The amplifier circuits 37-1 to 37-N receive the envelope power from the envelope detection circuits 34-1 to 34-N, respectively, and amplify and output the outputs of the phase shift circuits 35-1 to 35-N based on the envelope power. The adder circuit 38 adds and outputs N outputs of the respective amplifier circuits 37-1 to 37-N. The output of the adder circuit 38 is determined by the determination circuit 39, and the determination value is output from the determination value output terminal 6. .

The operation of the phase detection circuits 36-1 to 36-N will now be described with reference to FIG. The multiplication circuit 42 receives the reception signals input from the respective antenna input terminals 1-1 to N from the reception signal input terminal 40,
If it is SK, it is multiplied by 2 and if it is 4-phase PSK, it is multiplied by 4 and output. The output of the multiplying circuit 42 is averaged by an averaging circuit 43, and in a frequency dividing circuit 44, for example, the frequency is divided by two in the case of two-phase PSK and divided by four in the case of four-phase PSK. As described in the above description of the carrier phase locked loop, the averaging circuit 4
3 outputs are 2 for 2-phase PSK, 4 for 4-phase PSK
Phase uncertainty. Accordingly, the phase uncertainty removing circuit 45 inputs the phase synchronization information from the phase synchronization information input terminals 33-1 to N from the phase synchronization information input terminal 41, removes the phase uncertainty based on this, and removes the phase uncertainty. Output from the information output terminal 46.

The above-described phase synchronization information is often created using unique words inserted at regular intervals in a normal data sequence. However, in a transmission path in which errors are continuous (for example, a fading transmission path), the carrier phase estimated using the unique word becomes erroneous, and it becomes necessary to remove the phase uncertainty without the unique word. Carrier phase estimated without unique word has a random phase ambiguity for each antenna, the combination if the alphabet size is U, the street U ^N.
There are U combinations of carrier phases that enable proper diversity combining.

Assuming that the correct carrier phase of the antenna p is γ ^(p) as shown in the description of the diversity after detection, for example, assuming that the combination of the estimated carrier phases is γ ⁽¹⁾ , γ ⁽²⁾ ,…, γ ^(N) and γ ⁽¹⁾ + π, γ
^{(2) In the case of} + π,..., Γ ^(N) + π, it is clear that diversity combining can be performed correctly. Where γ ⁽¹⁾ + π, γ
^{(2) In the case of} + π,..., Γ ^(N) + π, the judgment value is reversed. That is, there are U phase uncertainties in the determination value. As described above, in the above-mentioned conventional example 1, the probability that diversity combining can be performed correctly without a unique word is 1 / (U
^N-1 ), and when the number of antennas is large, it is almost impossible to achieve diversity combining without a unique word.

Next, a conventional maximum likelihood sequence estimation apparatus will be described. FIG. 15 is a block diagram of a conventional maximum likelihood sequence estimation device. In the figure, 1 is a reception signal input terminal, 7-2 is a branch metric generation circuit B, 8-1 to M are ACS circuits,
0 is a judgment value creation circuit, and 12 is a transmission line characteristic input terminal.

FIG. 16 shows the branch metric generating circuit B7-.
2 is a block diagram showing the inside of FIG. 2. In the figure, reference numeral 11 denotes a reception signal input terminal connected to the reception signal input terminal 1, and reference numeral 13 denotes a combination pattern of S determination value candidates corresponding to each branch metric. Pattern table, 14-
B1 to BS are branch metric calculation circuits B, and 15-1 to S are branch metric output terminals.

FIG. 17 shows the branch metric calculation circuit B14.
FIG. 19 is a block diagram showing the inside of -B1 to BS, wherein reference numeral 19 denotes the pattern table 1 input from the pattern input terminal 16;
3 and a transmission path characteristic from the transmission path characteristic input terminal 12, and a replica generation circuit for outputting a replica of the received signal. A replica 20 of the received signal output from the replica generation circuit 19 and a received signal input This is a square error generation circuit that receives a reception signal from the reception signal input terminal 1 input via a terminal 11 and outputs the binary square error value from a branch metric output terminal 22 as a branch metric. .

FIG. 18 shows the ACS circuits 8-1 to 8 -M
FIG. 3 is a block diagram showing one of the above.
1 to U are branch metric input terminals, 30-1 to U are path metric generation circuits 1, 31 is a metric path selection circuit,
32 is a metric path output terminal.

Next, the operation of the maximum likelihood sequence estimation device will be described with reference to FIG.
5 will be described. Branch metric generation circuit B7-2
Inputs a received signal from a received signal input terminal 1 and a transmission path characteristic from a transmission path characteristic input terminal 12 to create S branch metrics. (S = U × M)

Here, the branch metric generating circuit B7-2
Will be described with reference to FIGS. 16 and 17. The pattern table 13 in the branch metric generation circuit B7-2
Outputs a combination pattern of S determination value candidates corresponding to each branch metric. Each branch metric calculation circuit B1
The replica generation circuit 19 of 4-B1 to BS transmits the pattern output by the pattern table 13 from the pattern input terminal 16 to the
Further, the transmission path characteristics are input from the transmission path characteristic input terminal 12, respectively, and a replica of the received signal is created.

The square error generating circuit 20 receives the replica of the received signal from the replica generating circuit 19 and the received signal from the received signal input terminal 11, and uses the binary square error value as a branch metric. Branch metric output terminal 15-
1 to S. As described above, S branch metrics are output from the branch metric generation circuit B7-2.

The S branch metrics are then calculated for each ACS
U is input to each of the circuits 8-1 to 8 -M.
The CS circuits 8-1 to 8 -M output surviving paths and path metrics corresponding to the states. (S = U × M) Then AC
The operation of the S circuits 8-1 to M will be described with reference to FIG. It is assumed that the M ACS circuits 8-1 to 8 -M can access each other by sharing the path metric and the surviving path one time past. The path metric creating circuits 30-1 to 30-U receive the corresponding branch metrics from the branch metric input terminals 29-1 to 29-U, further input the path metrics one time past, and create the current time path metrics therefrom. .

The metric path selection circuit 31 receives the path metric of the U system at the current time from each of the path metric creation circuits 30-1 to 30-U, selects one of the path metrics, and selects the corresponding one time past metric. Is updated, and the selected path metric and the surviving path at the current time are output from the metric path output terminal 32. Thus, the ACS circuits 8-1 to 8-1
The M sets of current path metrics and surviving paths output from M are input to the determination value creation circuit 10. The determination value creation circuit 10 determines a determination value based on the path metric, and outputs the determination value from the determination value output terminal 6.

Next, an example of the diversity receiver of the second conventional example will be described. This example is the maximum likelihood sequence estimation described in Hamada et al., "Effect of Improving Bit Error Rate of Mobile Communication by Spatial Diversity Reception and Viterbi Equalizer", RCS92-29, 1992, IEICE Technical Committee on Wireless Communication Systems. This realizes diversity. In addition,
In the drawings, components denoted by the same reference numerals as those described above are the same or corresponding components. FIG. 19 is a block diagram of a diversity receiver. In the figure, 1-1 to N are antenna reception signal input terminals, 12-1 to N are antenna transmission line characteristic input terminals, and 7-3 is a branch metric generation circuit C.

FIG. 20 shows the branch metric generating circuit C7-
3 is a block diagram showing the inside of FIG.
1 to N are antenna reception signal input terminals, 12-1 to N are antenna transmission line characteristic input terminals, and 14-C1 to CS are branch metric calculation circuits C.

FIG. 21 shows the branch metric calculation circuit 14-.
FIG. 3 is a block diagram showing the inside of C1 to CS, in which 19-1 to N are replica generation circuits, 20-1 to N are square error generation circuits 1, and 21 are addition circuits.

Next, the operation of the diversity receiver of the conventional example 2 will be described with reference to FIG. The branch metric generation circuit C7-3 includes antenna reception signal input terminals 1-1 to 1-1.
N-system received signals corresponding to N to N antennas, and N-system transmission line characteristics corresponding to N antennas from antenna transmission line characteristic input terminals 12-1 to 12-N are input, respectively. Create branch metrics. The S branch metrics are input to the ACS circuits 8-1 to 8 -M, and thereafter, the operation is the same as the operation described with reference to FIG. 15.

Here, the branch metric generating circuit C7-
Operation 3 will be described with reference to FIGS. Each of the branch metric calculation circuits 14-C1 to CS in the branch metric generation circuit C7-3 includes an antenna reception signal input terminal 1-.
N-system received signals corresponding to N antennas from 1 to N, and N-system transmission line characteristics corresponding to N antennas are input from antenna transmission line characteristic input terminals 12-1 to 12-N, respectively. Except for the above, it is the same as FIG.

Each branch metric calculation circuit 14-C1 to CN
Will be described with reference to FIG. Each replica creation circuit 19-1 to 19-N has a pattern output from the pattern table 13 from the pattern input terminal 16 and a transmission line characteristic corresponding to the antenna reception signal from the corresponding antenna transmission line characteristic input terminal 12-1 to N. Are input, and a replica of each antenna reception signal is created from these. Then, the replica of the antenna reception signal and the antenna reception signals from the antenna reception signal input terminals 11-1 to 11-N are input to the square error generation circuits 20-1 to 20-N, and the signals corresponding to the respective antennas are output. Outputs the square error of the value. The adder circuit 21 receives N square error values corresponding to the respective antennas and outputs the sum as a branch metric from a branch metric output terminal 22. The branch metric output by such an operation is represented by Expression (14).

[0061]

[Equation 11]

Here, if L = 0,

[0063]

(Equation 12)

The following relationship is obtained.

In this conventional example, the transmission line characteristics are input from outside. Actually, as described in the description of the estimation of the transmission channel, the transmission channel estimation is performed using the training sequence inserted into the data sequence at equal intervals. here,
If the interval between the training sequences is long and the transmission path characteristics fluctuate greatly, it is difficult to operate stably.

[0066]

The diversity receiver according to the prior art 1 cannot stably perform diversity combining unless information for removing the phase uncertainty is input from the outside. Since there is no function, there is a problem that characteristics are deteriorated in the presence of a frequency offset. Further, the diversity receiver of the conventional example 2 needs to input the transmission line characteristics from the outside, and does not operate stably when the transmission line characteristics fluctuate greatly.
Since there is no function, there is a problem that characteristics are deteriorated in the presence of a frequency offset.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to stably operate even when transmission line characteristics fluctuate greatly without inputting external information for removing phase uncertainty. , Or can operate even when transmission path characteristics cannot be input from the outside,
Further, it is another object of the present invention to provide a diversity receiver which can suppress the characteristic degradation due to the frequency offset by providing the AFC function, and in which the performance of the received signal is improved such as the maximum ratio combining.

[0068]

According to a first aspect of the present invention, there is provided a diversity receiver which receives an input signal from the diversity receiver.
Enter the channel characteristics against the received signal and the received baseband signal, and a data decision means for outputting a decision value is an estimate of the transmitted data based on the relevant channel characteristics and the received signal, this the decision value data judging means outputs a to input and the received signal, estimates the channel characteristic for pairs <br/> in the received signal, comprising a transmission path estimating means for outputting to said data determining means Things.

The diversity receiver according to claim 2 is
The data determination unit, a complex conjugate calculation unit that calculates a complex conjugate value of a transmission path characteristic for each of the received signals ,
The complex conjugate value output from this complex conjugate calculation means and the above
A multiplying means for multiplying each of the received signals and a multiplied value outputted from the multiplying means, and an added data judging means for outputting a judgment value which is an estimated value of data transmitted based on the added value It was done.

The diversity receiver according to claim 3 is:
According to claim 1 or 2 diversity receiver, the
A transmission path estimating means for estimating channel characteristics based on the received signal and the decision value from the data decision means, the frequency of estimating the frequency offset of the received signal based on the said received signal <br/> and the determination value An offset estimating means, and a transmission path characteristic phase rotation means for performing phase rotation on the transmission path characteristic estimated by the transmission path estimating means based on the frequency offset estimated by the frequency offset estimating means and outputting the result as transmission path characteristic. is there.

A diversity receiver according to claim 4 is:
The frequency offset estimating means according to claim 3 further comprises means for calculating a stationary phase error and estimating a frequency offset for estimating the frequency offset using the stationary phase error.

A diversity receiver according to claim 5 is as follows:
In the frequency offset estimation means according to claim 3, said receiving
It is provided with means for calculating a phase change between a plurality of symbols from a result of delayed detection of a plurality of symbols of a received signal and a determination value, and estimating a frequency offset for estimating a frequency offset from the phase change.

A diversity receiver according to claim 6 is
A means for outputting a soft decision value as the data decision value is provided.

[0074]

According to the first and second aspects of the present invention,
Since the transmission path estimation means performs the transmission path estimation based on the determination value obtained by the data determination means, the relative carrier phase difference for each antenna is not random but constant as in the conventional case. By outputting the determination value of the transmitted data by the data determination unit based on the path estimation, it is possible to stably realize the maximum ratio combining diversity.

According to the third to fifth aspects of the present invention, since automatic frequency control can be realized, good reception can be performed even on a transmission line having a frequency offset.

According to the sixth aspect of the present invention, by outputting the soft decision output, the bit error rate characteristic at the time of Viterbi decoding can be greatly improved.

[0077]

[Embodiment 1] Hereinafter, embodiments of the present invention will be described. In the drawings, components denoted by the same reference numerals as those described above are the same or equivalent. FIG. 1 is a block diagram showing an embodiment of the diversity receiver according to the present invention.

In FIG. 1, 2-1 to N are complex conjugate circuits for calculating complex conjugate values, 3-1 to N are complex conjugate values output from the complex conjugate circuits 2-1 to N, and antenna reception signals. The multiplication circuit 4 multiplies the reception signals from the input terminals 1-1 to N, and the multiplication circuit 4 adds the multiplication values output from the multiplication circuits 3-1 to N, and calculates an estimated value of the transmitted data from the addition result. The addition judgment circuit 5 outputs a certain judgment value, and the addition judgment circuit 5 outputs transmission path characteristics corresponding to each antenna from the judgment value output by the addition judgment circuit 4 and the reception signals from the antenna reception signal input terminals 1-1 to N. This is a transmission path estimating circuit.

Next, the operation will be described. The same reference numerals as those in the conventional example indicate the same operation. The difference of this embodiment from the conventional example is that the transmission path characteristics corresponding to each antenna are estimated from the reception signals of the N antennas using the judgment values obtained from the signals obtained by the diversity combination. Will be explained with emphasis.

The transmission path estimating circuit 5 determines the judgment value output from the addition judgment circuit 4 and the antenna reception signal input terminal 1-1.
To N, and receives N systems of received signals and outputs estimated values of transmission path characteristics (N pieces) for each antenna. Each of the complex conjugate circuits 2-1 to N calculates a complex conjugate value of the antenna transmission path characteristic output by the transmission path estimation circuit 5, and
To N.

Each of the multiplying circuits 3-1 to N calculates the complex conjugate value of the antenna transmission path characteristic from each of the complex conjugate circuits 2-1 to N and the received signals from the antenna received signal input terminals 1-1 to N. The result is multiplied and output to the addition determination circuit 4. The addition judgment circuit 4 adds N multiplication results from the multiplication circuits 3-1 to N, judges a judgment value which is an estimated value of the transmitted data from the addition result, and outputs the judgment value from the judgment value output terminal 6. Output.

The above operation will be specifically described. In FIG. 1, regarding the received signal at time n, the received signal of antenna 1 is r ⁽¹⁾ n and the received signal of antenna N is r ^(N) n. Regarding the tap coefficient of the transmission path characteristic at time n, the estimated tap coefficient for the received signal of antenna 1 is
⁽¹⁾ n, and the estimated tap coefficient for the received signal of antenna N is g ^(N) n. The addition determination circuit 4 calculates the addition value of the expression (16).

[0083]

(Equation 13)

When the transmission modulation signal is, for example, two-phase PSK
, The judgment value Jn is increased by + when the addition value is 0 or more.
If it is less than 1, 0, the judgment value Jn is output as -1.
In this case, not only the hard decision value but also the above-described soft decision value can be output as the decision value at this time. When the output of the soft decision value is required, the above-mentioned added value as shown in, for example, equation (16) is output.

Next, the transmission path estimating circuit 5 determines the judgment value Jn
Is used to calculate an estimated value of the transmission path characteristic for each of the N antennas. Here, the case where the LMS algorithm is used will be described. The transmission path estimating circuit 5 calculates the estimated tap coefficients for each of the N antennas by using the above-described determination value Jn according to equation (17).

[0086]

[Equation 14]

As described above, in the first embodiment, diversity combining is performed based on the transmission path characteristics of each antenna and the received signal, and the determination value, which is the estimated value of the transmitted data, is output using the result. At the same time, the characteristic of the transmission path for each antenna is estimated from the decision value using the diversity combining result and the received signal for each antenna, and the estimated value is used as the transmission path characteristic for each antenna to determine its complex conjugate and reception. It is possible to realize maximum ratio combining diversity by using it for diversity combining in the form of multiplying the signals and taking the sum.

According to the above embodiment, diversity combining is performed using transmission path characteristics that can unifyly express the carrier phase and envelope amplitude of the received signal for each antenna, and the decision value using the result of the diversity combining is performed. As a result of estimating the transmission path characteristics using, the determination value output has phase uncertainty, but since there is no relative phase error in the transmission path characteristics for the N antennas, external phase uncertainty exists. The maximum ratio combining diversity receiver can be stably provided without inputting information for removing determinism, and as a result, the bit error rate characteristics can be improved.

Further, in the above description, the transmission path estimation LMS
Although the case where the algorithm is used has been described, the transmission path estimation may be performed by an adaptive algorithm such as the RLS algorithm. As described above, if the transmission path is estimated for each symbol of the received signal using the adaptive algorithm, it is possible to follow the fluctuation of the transmission path characteristics even when the fluctuation is high.

Further, by outputting the soft decision value,
The bit error rate characteristics of the subsequent Viterbi decoder can be improved.

Embodiment 2 FIG. FIG. 2 is a block diagram showing Embodiment 2 of the diversity receiver according to the present invention. It is to be noted that components denoted by the same reference numerals as those of the conventional example are the same. The second embodiment differs from the second conventional example (FIG. 17) in that a transmission path estimating circuit 9-1 is provided for each state and that a branch metric calculation method is different. explain.

In FIG. 2, reference numeral 7-1 denotes a reception signal from the antenna 1 to the antenna N from the antenna reception signal input terminals 1-1 to N, and a transmission path estimation circuit 9-1.
.. M from the state 1 to the state M, and a branch metric generating circuit A for generating a branch metric based on these. 8-1 to 8-M receive the branch metric from the branch metric creation circuit A7-1, input the path metric and the surviving path one time past, and perform the ACS processing to obtain the current time corresponding to each state. This is an ACS circuit that outputs the path metric and the surviving path, and is provided for each state.

9-1 to M input the surviving paths corresponding to each state from each of the ACS circuits 8-1 to M, and receive the reception signals of all the antennas 1 to N from the antenna reception signal input terminals 1-1 to N. Is a transmission path estimating circuit that inputs N and outputs N transmission path characteristics corresponding to the antenna 1 to the antenna N for each state.

That is, for example, the transmission path estimating circuit 9-1 outputs N transmission path characteristics from the antenna 1 to the antenna N corresponding to the state 1, and the transmission path estimating circuit 9-
From M, N transmission line characteristics from antenna 1 to antenna N corresponding to state M are output. M transmission line estimating circuits are provided for each state.

FIG. 3 shows the branch metric generating circuit A7-1.
Are transmission line characteristic input terminals for inputting the transmission line characteristics of N from the antenna 1 corresponding to the state 1, and the transmission line estimating circuit 9-1. Is input. Similarly, 12-M-1 to 12-N are antennas 1 corresponding to the state M.
Are input terminals for inputting the transmission line characteristics N to N, and the transmission line characteristics output from the transmission line estimation circuit 9-M are input thereto. And antennas 1 for each state
There are N transmission line characteristic input terminal sets. 14-A1 to AS
Is an antenna 1 input from these transmission path characteristic input terminals.
To N transmission path characteristics, reception signals of antennas 1 to N from reception signal input terminals 11-1 to 11-N, pattern table 13
Is a branch metric calculation circuit to which the output from is input.

FIG. 4 shows the branch metric calculation circuit 14-A.
1 is a block diagram showing the interior of an AS;
23-0 to L are data calculation circuits for each tap, and 24 is an addition circuit.

FIG. 5 shows the calculation circuits for taps 23-0 to 23-0.
L is a block diagram showing the inside of L.
1 to N are replica creation circuits, 25-1 to N are error creation circuits, 26-1 to N are complex conjugate multiplication circuits, 27 is an addition square circuit, and 28 is a tap data output terminal.

FIGS. 10A and 10B are explanatory diagrams for explaining the operation of the replica creation circuits 19-1 to 19-N.
In the figure, 50 is a shift register, 52 is an addition circuit,
53-1 is a zero estimated tap coefficient, 53-2 is a first estimated tap coefficient, 53-3 is a second estimated tap coefficient, 54
Is a replica output terminal, and 55 is a code conversion circuit.

Next, the operation will be described with reference to FIG.
The branch metric generation circuit A7-1 receives the reception signals from the antennas 1 to N from the antenna reception signal input terminals 1-1 to N and changes the state from the transmission path estimation circuits 9-1 to M to the states 1 to M, respectively. Enter the corresponding transmission path characteristics. Then, a branch metric is output from these.

Here, the branch metric generating circuit A7-
Operation 1 will be described with reference to FIG. The difference from the conventional example 2 (FIG. 20) is that the branch metric calculation circuits 14-A1 to 14-A1
The AS is that the AS inputs the channel characteristics corresponding to all the antennas from the antenna 1 to the antenna N for each state. That is, the branch metric calculation circuit 14-A1
From the transmission line characteristic input terminals 12-1-1 to 12-N, the antenna 1
From the antenna 1 to the antenna N, and the branch metric calculation circuit 14-AS outputs the state M of the state M from the antenna 1 to the antenna N from the transmission line characteristic input terminals 12-M-1 to 12-N. Input the transmission line characteristics,
Similarly, each branch metric calculation circuit between them inputs the transmission line characteristics of all antennas corresponding to each state.

A branch metric generating circuit A having such a configuration
At 7-1, a combination pattern of S determination value candidates corresponding to each branch metric is output from the pattern table 13 and input to the corresponding branch metric calculation circuit. The branch metric calculation circuits 14-A1 to AS
FIG. 4 shows a configuration in which this pattern is transmitted from the pattern input terminal 16 to each tap data calculation circuit 23-0 to L.
Is input to Data calculation circuits for taps 23-0 to L
In addition, the reception signals of the antennas 1 to N are input from the antenna reception signal input terminals 11-1 to 11-N, and the transmission line characteristics of the antennas 1 to N are input from the antenna transmission line characteristic input terminals 12-1 to N. Then, data for each tap used for the branch metric value is calculated from these input values.

Here, the tap data calculation circuit 23-0
The operation of L will be described with reference to the example of FIG. In FIG. 5, the pattern from the pattern table 13 input from the pattern input terminal 16 corresponds to each replica creation circuit 19-1.
To N. Each of the replica creation circuits 19-1 to 19-N also has an antenna transmission line characteristic input terminal 12-1 to N
, Transmission path characteristics for each antenna are input, and a replica is created based on these input values.

The operation of replica creation in the replica creation circuits 19-1 to 19-N will be described with reference to the examples of FIGS. The pattern input from the pattern input terminal 16 is input to the shift register 50, and is sequentially output with a delay of one symbol period. This output is respectively multiplied by a zeroth estimated tap coefficient 53-1, a first estimated tap coefficient 53-2, and a second estimated tap coefficient 53-3 input from the antenna transmission line characteristic input terminal 12-1. The result is output to the addition circuit 52.

The adder circuit 52 receives and adds the tap outputs and outputs the sum as a replica from a replica output terminal 54. Note that the code conversion circuit 55 in FIG. 10B performs encoding such as a convolutional code on the pattern input from the pattern input terminal 16 as necessary, and outputs the resultant to the shift register 50. . At this time, encoded data is input as reference data of the LMS algorithm.

The replica created in this way is input to each of the error creating circuits 25-1 to 25-N as shown in FIG. In each of the error creating circuits 25-1 to 25-N, a replica is input from each of the replica creating circuits 19-1 to 19-N, and an antenna reception signal is input from each of the antenna reception signal input terminals 11-1 to 11-N. Is output to each of the complex conjugate multiplication circuits 26-1 to 26-N.

In the complex conjugate multiplication circuits 26-1 to 26-N, only predetermined tap coefficients of the antenna transmission path characteristics are input from the antenna transmission path characteristic input terminals 12-1 to 12-N, and the complex conjugate value of this value is calculated. Calculated, multiplied by the complex conjugate value and the error input from each of the error generation circuits 25-1 to 25-N, and output to the addition square circuit 27. In the addition square circuit 27, the values from the complex conjugate multiplication circuits 26-1 to 26-N are added and then squared, and output from the tap data output terminal 28 as data for each tap.

The tap data thus obtained is output from tap data calculation circuits 23-0 to 23-L of FIG. The adder circuit 24 inputs and adds (L + 1) data from tap 0 data to tap L data, and outputs the result from the branch metric output terminal 22. Branch metric output terminal 2 obtained as described above
2 is output from each branch metric calculation circuit 14- in FIG.
Outputs from A1 to AS are output as branch metrics from the branch metric output terminals 15-1 to 15-S.

Here, as the replica creation circuit,
The shape shown in FIG. 10B can also be used.

The above-mentioned branch metric is expressed by equation (18).

[0110]

(Equation 15)

If L = 0, the branch metric of equation (18) becomes equation (19), and the effect becomes clear.

[0112]

(Equation 16)

The expression (19) is obtained by calculating the value of In closest to the expression (20).
Is equivalent to selecting as a determination value, and this operation corresponds to maximum ratio combining diversity.

[0114]

[Equation 17]

As the judgment value output by the judgment value generating circuit 6, not only the hard decision value but also the above-mentioned soft decision value can be output.

As described above, the diversity receiver described in the second embodiment performs the transmission path estimation for each symbol by the LMS algorithm, the RLS algorithm, or the like for each Viterbi algorithm state. Even when the speed is high, it can follow the fluctuation.

Further, by creating a branch metric as described above, when the transmission line memory is 0, the combination of the received signals becomes the maximum ratio combination.

Further, by outputting the soft decision value, the bit error rate characteristics of the subsequent Viterbi decoder can be improved. That is, the advantages of the first embodiment can be provided.

The branch metric calculation circuit can be realized with the configuration described with reference to FIG. However, a specific state determined in advance in each branch metric calculation circuit is used for the transmission line characteristic.

Embodiment 3 FIG. Next, a third embodiment will be described. In the case of a transmission path in which a received signal has a frequency offset, it is necessary to consider the frequency offset also in estimating the transmission path characteristics. In this embodiment, the influence is suppressed by estimating the frequency offset.

FIG. 6 shows a concrete example of the transmission path estimating circuit 9 shown in FIG. 2, for example.
Components having the same reference numerals as those described above are the same or corresponding components. 6, reference numeral 60 denotes a received signal input terminal, 61 denotes a surviving path input terminal to which a surviving path output from the ACS circuit 8-M is input, 62 denotes a transmission line characteristic output terminal that outputs estimated transmission line characteristics, 6
Reference numeral 3 denotes a transmission path characteristic estimating circuit for estimating transmission path characteristics based on a received signal and a surviving path. This is a transmission line characteristic phase rotation circuit. The frequency offset estimating circuit A65 estimates the frequency offset from the received signal, surviving path, and transmission path characteristics.

FIG. 7 shows the frequency offset estimating circuit A6.
5 is a diagram illustrating an example of implementation of Example No. 5. In FIG. 7, 66 is a complex multiplication circuit A, 67 is a complex conjugate circuit A, 68 is a complex multiplication circuit B, 69 is a complex conjugate circuit B, 70 is an arctangent circuit,
71 is a weighted addition circuit, 72 is a frequency offset holding circuit, 73 is a transmission path characteristic input terminal to which the transmission path characteristic output from the transmission path characteristic phase rotation circuit 64 is input, and 74 is a frequency offset output terminal.

Next, the operation will be described with reference to FIG.
The transmission path characteristic estimating circuit 63 estimates transmission path characteristics from the received signal from the received signal input terminal 60 and the surviving path from the surviving path input terminal 61 according to an adaptive algorithm such as the LMS algorithm.

On the other hand, the frequency offset estimating circuit A65
Estimates the frequency offset from the received signal from the received signal input terminal 60, the surviving path from the surviving path input terminal, and the transmission path characteristics from the transmission path characteristic estimation circuit 63. Based on the frequency offset estimated by the frequency offset estimating circuit A65, the transmission path characteristic phase rotation circuit 64 performs phase rotation on the transmission path characteristic estimated by the transmission path characteristic estimation circuit 63, and outputs the result.

Frequency offset estimating circuit A using FIG.
Operation 65 will be described. The complex conjugate circuit A67 takes the complex conjugate of the surviving path from the surviving path input terminal 61 and outputs the result. The complex multiplying circuit A66 multiplies the complex conjugate value of the surviving path from the complex conjugate circuit A67 by the received signal received from the received signal input terminal 60 and outputs the result.

The complex conjugate circuit B69 takes the complex conjugate of the transmission path characteristic from the transmission path characteristic input terminal 73 and outputs it. The complex multiplying circuit B68 calculates the complex conjugate value of the transmission path characteristic output from the complex conjugate circuit B69 and the complex multiplying circuit A6.
6 is multiplied and output.

The arc tangent circuit 70 is a complex multiplication circuit B68
Takes the arc tangent of the output value and outputs a steady phase error. The weighted addition circuit 71 receives the stationary phase error and the held value of the frequency offset output from the frequency offset holding circuit 72, performs weighted addition thereof, and outputs an updated value of the frequency offset.

The frequency offset holding circuit 72 receives the updated value of the frequency offset output from the weighting and adding circuit 71, holds the updated value as a frequency offset, and outputs it to the frequency offset output terminal 74. By the above operation, the estimated value of the frequency offset shown in the equation (21) is obtained.

[0129]

(Equation 18)

This frequency offset is input to the transmission line characteristic phase rotation circuit 64 as an estimated value, and the phase rotation is performed on the transmission line characteristic. It should be noted that the transmission path characteristic subjected to this phase rotation is given to the transmission path characteristic estimating circuit 63 and used for estimating the next transmission path characteristic.

As described above, by estimating the frequency offset and applying phase rotation to the channel characteristics in accordance with the frequency offset, the channel characteristics are estimated in consideration of the frequency offset, and the channel having the channel characteristics is estimated. But it can operate stably.

Embodiment 4 FIG. Next, a fourth embodiment will be described. As described above, a frequency offset is considered in the case of a transmission path in which a received signal has a frequency offset. In this embodiment, however, the influence of noise upon estimating the frequency offset can be suppressed.

FIG. 8 shows a specific example of the transmission path estimating circuit 9 shown in FIG. 2, for example. The difference from FIG. 6 is that the transmission path characteristics are not used for frequency offset estimation. Components having the same reference numerals as those described above are the same or corresponding components. In FIG. 8, 7
Reference numeral 5 denotes a frequency offset estimating circuit B.

FIG. 9 shows the frequency offset estimating circuit B7.
5 is a diagram illustrating an example of implementation of Example No. 5. 9, reference numeral 76 denotes a Y symbol delay circuit A, 77 denotes a Y symbol delay circuit B,
78 is a complex multiplication circuit C, 79 is a complex conjugate circuit C, 80 is an averaging circuit, and 81 is a 1 / Y circuit.

Next, the operation will be described with reference to FIG.
The difference between FIG. 8 and FIG. 6 is that the transmission path characteristics are not used for frequency offset estimation. The frequency offset estimation circuit B75 inputs the received signal and the surviving path and outputs the frequency offset.

Frequency offset estimating circuit B using FIG.
75 will be described. Y symbol delay circuit A7
6 outputs the received signal after delaying it by Y symbols. The complex conjugate circuit A67 outputs a complex conjugate value related to the Y symbol delay data of the received signal.

The complex multiplying circuit A66 includes a complex conjugate circuit A6.
7 and outputs the result of multiplication of the received signal with the complex conjugate value relating to the delayed data for Y symbols from. On the other hand, the Y symbol delay circuit B77 gives a delay of Y symbols to the surviving path from the surviving path input terminal 61 and outputs the surviving path.
The complex conjugate circuit B64 outputs a complex conjugate value regarding the delay data for the Y symbol of the surviving path.

The complex multiplication circuit B68 calculates the surviving path Y
The multiplication result of the complex conjugate value and the surviving path for the symbol-delayed data is output. The complex conjugate circuit C79 outputs a complex conjugate value of the multiplication result output from the complex multiplication circuit B68. The complex multiplication circuit C78 outputs a complex multiplication result of the output of the complex multiplication circuit A66 and the output of the complex conjugate circuit C79.

The arc tangent circuit 70 takes the arc tangent of the output of the complex multiplication circuit C78 and outputs a phase change occurring between symbols separated by Y symbols. The averaging circuit 80 inputs the phase change, averages the phase change, and outputs a phase change with less influence of noise generated between the symbols. 1 / Y circuit 81
Outputs 1 / Y of this phase change to a frequency offset output terminal 74 as a frequency offset value. By the operation as described above, the estimated value of the frequency offset shown in Expression (22) is obtained.

[0140]

[Equation 19]

As described above, in the fourth embodiment, since the frequency offset is estimated from the phase change between the symbols separated by Y symbols, the influence of noise per symbol is averaged and reduced, so that the frequency can be accurately determined. An offset value can be estimated, and a phase rotation is given to a transmission path characteristic according to the frequency offset value, so that a stable operation can be performed even on a transmission path where a frequency offset exists.

[0142] Incidentally, as the input of the third and fourth embodiments in the channel estimation circuit 63 has been described to estimate the input to channel characteristics and the survivor path from the received signal and the A CS circuit, similar With the configuration described above, it is also possible to input the received signal and the judgment value from the addition judgment circuit 4 in FIG.

Further, each of the above means can be realized by signal processing by software. Further, in each of the above-described embodiments, the description has been given of the case having N antennas, but N may be one.

[0144]

As described above, according to the first aspect of the present invention,
The diversity receiver has the following effects. (A) Diversity combining can be stably realized without inputting information for removing phase uncertainty from the outside. (B) Even if the fluctuation of the transmission path characteristic is high speed, it can follow the fluctuation.

Further, according to the second aspect of the present invention, the diversity combining can be the maximum ratio combining diversity.

According to the third to fifth aspects of the present invention, automatic frequency control can be performed, and stable operation can be performed even in the presence of a frequency offset. According to the sixth aspect of the present invention, in the diversity receiver, the bit error rate characteristics of the subsequent Viterbi decoder can be improved by outputting the soft decision value.

[Brief description of the drawings]

FIG. 1 is a block diagram of a diversity receiver according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a diversity receiver according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a branch metric generation circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a branch metric calculation circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a tap calculation circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a transmission path estimation circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram of a frequency offset estimating circuit according to a third embodiment of the present invention.

FIG. 8 is a block diagram of a transmission path estimation circuit according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram of a frequency offset estimating circuit according to a fourth embodiment of the present invention.

FIG. 10 is an explanatory diagram of a replica creation circuit.

FIG. 11 is a model diagram of a transmission path.

FIG. 12 is an explanatory diagram of a trellis grating.

FIG. 13 is a block diagram of a conventional phase detection circuit.

FIG. 14 is a block diagram of a diversity receiver of Conventional Example 1.

FIG. 15 is a block diagram of a conventional maximum likelihood sequence estimation device.

FIG. 16 is a block diagram of a branch metric creation circuit of a conventional maximum likelihood sequence estimation device.

FIG. 17 is a block diagram of a branch metric calculation circuit of a conventional maximum likelihood sequence estimation device.

FIG. 18 is a block diagram of an ACS circuit of a conventional maximum likelihood sequence estimation device.

FIG. 19 is a block diagram of a diversity receiver of Conventional Example 2.

FIG. 20 is a block diagram of a branch metric generation circuit of the diversity receiver of the second conventional example.

FIG. 21 is a block diagram of a branch metric calculation circuit of the diversity receiver according to the embodiment of the present invention and the conventional example 2;

[Explanation of symbols]

1-1 to N antenna reception signal input terminal 2-1 to N complex conjugate circuit 3-1 to N multiplication circuit 4 addition determination circuit 5 transmission path estimation circuit 6 determination value output terminal 7-1 branch metric generation circuit A 7-2 Branch metric creation circuit B 7-3 Branch metric creation circuit C 7-1 to M ACS circuit 9-1 to M Transmission line estimation circuit 10 Judgment value creation circuit 11-1 to N Received signal input terminals 12-1 to N state 1 Transmission path characteristic input terminal 12-M to N state M Transmission path characteristic input terminal 13 Pattern table 14-A1 to AS Branch metric calculation circuit A 14-B1 to BS Branch metric calculation circuit B 14-C1 to CS Branch metric calculation circuit C 15-1 to S branch metric output terminal 16 pattern input terminal 19-1 to N replica creation circuit 20-1 to N square error creation circuit 21 addition circuit 22 branch mete Lick output terminal 23-0 to L tap data calculation circuit 24 addition circuit 25-1 to N error creation circuit 26-1 to N complex conjugate multiplication circuit 27 addition square circuit 28 tap data output terminal 29-1 to U branch Metric input terminal 30-1 to U path metric creating circuit 31 Metric path selecting circuit 32 Metric path output terminal 50 Shift register 51-1 0th actual tap coefficient 51-2 First actual tap coefficient 51-3 Second Tap coefficient 52 Addition circuit 53-1 Zeroth estimated tap coefficient 53-2 First estimated tap coefficient 53-3 Second estimated tap coefficient 54 Replica output terminal 55 Code conversion circuit 60 Received signal input terminal 61 Survival path input terminal 62 channel characteristics output terminal 63 the channel estimation circuit 64 transmission path characteristic phase rotation circuit 65 laps Number offset estimating circuit A 66 Complex multiplying circuit A 67 Complex conjugate circuit A 68 Complex multiplying circuit B 69 Complex conjugate circuit B 70 Arc tangent circuit 71 Weighted addition circuit 72 Frequency offset holding circuit 73 Transmission path characteristic input terminal 74 Frequency offset output terminal 76 Y symbol delay circuit A 77 Y symbol delay circuit B 78 Complex multiplication circuit C 79 Complex conjugate circuit C 80 Averaging circuit 81 1 / Y circuit

Continuation of the front page (56) References JP-A-5-63618 (JP, A) JP-A-58-123251 (JP, A) JP-A-3-73623 (JP, A) JP-A-5-316083 (JP, A) JP-A-5-110617 (JP, A) JP-A-5-235791 (JP, A) JP-A-3-283827 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB H03H 15/00-21/00 H03M 13/00-13/22 H04B 1/76-3/44 H04B 3/50-3/60 H04B 7/00-7/12 H04L 1/02-1/06

Claims (6)

(57) [Claims] The present invention has the following configuration, and transmits transmitted data.
A diversity receiver that outputs a judgment value that is an estimated value ; (a) a base bang input to the diversity receiver
The received signal of the de inputs the transmission path characteristics for the received signal, based on the relevant channel characteristics and the received signal, the upper
Data decision means for outputting the serial determination value, (b) the decision value and the output from the data decision means
Enter the received signal, it estimates the channel characteristic for the received signal, channel estimation means for outputting to the data decision means. 2. A diversity receiver according to claim 1, wherein said data determination means has the following configuration : (a) calculates a complex conjugate value of a transmission path characteristic for each of said received signals. (B) multiplying means for multiplying the received signal by the complex conjugate value output from the complex conjugate calculating means, (c) adding the multiplied values output from the multiplying means, Adding data determination means for outputting a determination value which is an estimated value of the transmitted data based on the added value; 3. The diversity receiver according to claim 1, wherein a transmission path estimating means for estimating a transmission path characteristic based on said received signal and a judgment value from said data judgment means, and said received signal and said judgment value. A frequency offset estimating means for estimating a frequency offset of the received signal based on the frequency offset; A diversity receiver comprising transmission line characteristic phase rotation means for outputting as a transmission line characteristic. 4. A diversity receiver characterized in that the frequency offset estimating means of claim 3 has the following configuration : (a) receiving the received signal , the determination value, and the transmission path characteristic; A stationary phase error estimating means for estimating a stationary phase error existing between the received signal and the transmission path characteristic; and (b) inputting the stationary phase error output from the stationary phase error estimating means and outputting a frequency offset. Frequency offset calculation means. Frequency offset estimating means 5. The method of claim 3, the following diversity receiver characterized by having a structure; (a) to input the received signal provides a delay of Y symbols received signal delay means (B) judgment value delay means for inputting the judgment value and providing a delay of Y symbols, (c) a symbol separated by Y symbols based on the output from the reception signal delay means and the judgment value delay means (D) inputting the phase change estimated by the phase change estimating means,
Frequency offset calculating means for estimating a frequency offset by averaging the frequency offset. 6. The diversity receiver according to claim 1, further comprising means for outputting a soft decision value as a data decision value.