JP3169406B2 - Nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory deviceInfo
- Publication number
- JP3169406B2 JP3169406B2 JP32393091A JP32393091A JP3169406B2 JP 3169406 B2 JP3169406 B2 JP 3169406B2 JP 32393091 A JP32393091 A JP 32393091A JP 32393091 A JP32393091 A JP 32393091A JP 3169406 B2 JP3169406 B2 JP 3169406B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- ferroelectric
- memory device
- substrate
- semiconductor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims description 28
- 239000003990 capacitor Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 230000010287 polarization Effects 0.000 claims description 12
- 230000005669 field effect Effects 0.000 claims description 9
- 230000002269 spontaneous effect Effects 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 31
- 238000009792 diffusion process Methods 0.000 description 23
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 102200091804 rs104894738 Human genes 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910005900 GeTe Inorganic materials 0.000 description 1
- 229910020684 PbZr Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 150000001786 chalcogen compounds Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002366 halogen compounds Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- -1 n 1 -x Cd x Te Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003980 solgel method Methods 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、EEPROM(Electr
ical Erasable and Programmable ROM)のような不揮発
性半導体記憶装置に係り、特に、ゲート絶縁膜として強
誘電体膜を用いたMFSFET(Metal Ferroelectric
Semiconductor FET)構造の素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EEPROM (Electr
TECHNICAL FIELD The present invention relates to a nonvolatile semiconductor memory device such as an imaginary erasable and programmable ROM, and particularly relates to an MFSFET (Metal Ferroelectric) using a ferroelectric film as a gate insulating film.
Semiconductor FET).
【0002】[0002]
【従来の技術】以下、図3を参照して、従来のMFSF
ET素子の構成を説明する。図中、符号1は例えばP型
のシリコン基板であり、このシリコン基板1にN+ 領域
であるドレイン拡散層2およびソース拡散層3が形成さ
れている。ドレイン拡散層2およびソース拡散層3との
間の基板上に、例えばチタン酸ジルコン酸鉛(PZT)
等からなる強誘電体膜4が形成され、その上にゲート電
極5が形成されている。なお、図中の符号6は層間絶縁
膜、7はドレインおよびソースに接続する金属配線であ
る。2. Description of the Related Art Referring to FIG.
The configuration of the ET element will be described. In the drawing, reference numeral 1 denotes, for example, a P-type silicon substrate, on which a drain diffusion layer 2 and a source diffusion layer 3 which are N + regions are formed. On the substrate between the drain diffusion layer 2 and the source diffusion layer 3, for example, lead zirconate titanate (PZT)
A ferroelectric film 4 is formed, and a gate electrode 5 is formed thereon. Reference numeral 6 in the drawing denotes an interlayer insulating film, and reference numeral 7 denotes a metal wiring connected to a drain and a source.
【0003】上述したMFSFET素子の強誘電体膜4
は、図4に示すようなヒステリシス特性を持つ。図中、
横軸は強誘電体膜に作用する電界、縦軸は強誘電体膜の
分極電荷量である。ここで、強誘電体膜4に電界Esat
以上を与えるような正電圧をVMAX とする。この電圧V
MAX をゲート電極5に印加すると、強誘電体膜4は図4
中のAの状態にまで分極し、図3に示した素子のソース
・ドレイン間にチャネルが形成される。この後、ゲート
電圧を0Vに戻しても、ゲート電極5は図4のBの状態
になり、分極(自発分極)が残留し、前記チャネルが形
成されたままとなる。The ferroelectric film 4 of the above-mentioned MFSFET device
Has a hysteresis characteristic as shown in FIG. In the figure,
The horizontal axis represents the electric field acting on the ferroelectric film, and the vertical axis represents the amount of polarization charge of the ferroelectric film. Here, an electric field E sat is applied to the ferroelectric film 4.
A positive voltage so as to provide more than the V MAX. This voltage V
When MAX is applied to the gate electrode 5, the ferroelectric film 4
Polarized to the state of A in the middle, and a channel is formed between the source and the drain of the device shown in FIG. Thereafter, even if the gate voltage is returned to 0 V, the gate electrode 5 is brought into the state shown in FIG. 4B, polarization (spontaneous polarization) remains, and the channel remains formed.
【0004】逆に、ゲート電極5に−VMAX の負電圧
(または、基板に+VMAX の正電圧)を印加すると、強
誘電体膜4は図4のCの状態にまで分極する。その後、
電圧を0Vに戻すと、Dの状態となって負の分極(自発
分極)が残留する。この過程においては、ソース・ドレ
イン間にチャネルが形成されない。[0004] Conversely, a negative voltage of -V MAX gate electrode 5 (or positive voltage of the substrate to the + V MAX) is applied to the ferroelectric film 4 is polarized to the state of C of FIG. afterwards,
When the voltage is returned to 0 V, the state becomes D and negative polarization (spontaneous polarization) remains. In this process, no channel is formed between the source and the drain.
【0005】以上のようにな強誘電体膜4の自発分極の
極性を、データの『0』,『1』に対応付けることによ
って、情報を不揮発的に記憶できるメモリが構成され
る。[0005] By associating the polarity of the spontaneous polarization of the ferroelectric film 4 with data "0" and "1", a memory capable of storing information in a nonvolatile manner is constructed.
【0006】[0006]
【発明が解決しようとする課題】MFSFET素子は上
述したような特性を有しているものの、現在まで、実用
化レベルの素子が発表されていない。その理由は、
(1)強誘電体物質をスパッタリングによってシリコン
基板に積層する際に基板にダメージを与えること、
(2)強誘電体物質をシリコン基板に積層した後、熱処
理が施されるが、このとき強誘電体物質が基板中に拡散
してFET特性を劣化させること、(3)シリコン基板
上に強誘電体物質を直接積層した場合、強誘電体膜の結
晶配向性が悪くなり、所望のヒステリシス特性を得にく
いこと等である。Although the MFSFET device has the above-mentioned characteristics, no device of a practical use level has been published until now. The reason is,
(1) damaging a substrate when a ferroelectric substance is laminated on a silicon substrate by sputtering;
(2) After the ferroelectric substance is laminated on the silicon substrate, heat treatment is performed. At this time, the ferroelectric substance diffuses into the substrate to deteriorate the FET characteristics. When the dielectric substance is directly laminated, the crystal orientation of the ferroelectric film is deteriorated, and it is difficult to obtain a desired hysteresis characteristic.
【0007】そこで、前記(1)、(2)の不都合を回
避するために、強誘電体膜とシリコン基板との間に、S
iO2 等の絶縁膜からなるバッファ層を設けたMFSF
ET素子が提案されている(「電気通信学会技術研究報
告」vol.78 No.179 pp.1〜81978) 。Therefore, in order to avoid the disadvantages (1) and (2), an S film is provided between the ferroelectric film and the silicon substrate.
MFSF provided with a buffer layer made of an insulating film such as iO 2
An ET element has been proposed ("Technical Research Report of the Institute of Electrical Communication, Vol. 78, No. 179, pp. 1-81978").
【0008】しかしながら、上述した絶縁膜からなるバ
ッファ層を設けた素子によれば、ゲート構造が、強誘電
体膜とバッファ層の積層キャパシタになるため、ゲート
電極5に印加された電圧の多くがバッファ層に加わり、
強誘電体膜に加わる分圧が小さくなるので、それだけ動
作電圧を大きく設定しなければならないという別異の問
題点を生じる。また、上記のバッファ層によっても、強
誘電体膜の結晶配向性を良好にすることは困難である。However, according to the above-described device provided with the buffer layer made of an insulating film, the gate structure becomes a laminated capacitor of the ferroelectric film and the buffer layer, so that most of the voltage applied to the gate electrode 5 is reduced. Joins the buffer layer,
Since the partial pressure applied to the ferroelectric film is reduced, another problem arises in that the operating voltage must be set higher accordingly. Also, it is difficult to improve the crystal orientation of the ferroelectric film even with the above buffer layer.
【0009】本発明は、このような事情に鑑みてなされ
たものであって、低電圧動作が可能であり、しかも結晶
性のよい強誘電体膜を有する不揮発性半導体記憶装置
(MFSFET素子)を実現することを目的としてい
る。SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and a non-volatile semiconductor memory device (MFSFET element) capable of operating at a low voltage and having a ferroelectric film with good crystallinity has been developed. It is intended to be realized.
【0010】[0010]
【課題を解決するための手段】本発明は、このような目
的を達成するために、次のような構成をとる。すなわ
ち、本発明は、電界効果トランジスタのチャネル領域上
に強誘電体キャパシタを備え、前記キャパシタの強誘電
体膜の自発分極を利用して情報を記憶する不揮発性半導
体記憶装置において、半導体基板上または基板上に形成
された半導体層上に、前記キャパシタの下部電極および
前記電界効果トランジスタのゲート電極とを兼ねる金属
原子を含む導電体膜を直接形成させたものである。The present invention has the following configuration in order to achieve the above object. That is, the present invention comprises a ferroelectric capacitor on a channel region of a field effect transistor, the nonvolatile semiconductor memory device that stores the information by utilizing the spontaneous polarization of the ferroelectric film of the capacitor, on a semiconductor substrate or Form on substrate
On the semiconductor layer that is one in which a conductive film containing a metal atom serving as a gate electrode of the lower electrode and the field effect transistor of the capacitor was formed directly.
【0011】[0011]
【作用】本発明の作用は次のとおりである。すなわち、
本発明によれば、強誘電体キャパシタに印加された電圧
の殆ど全ては、上部電極と下部電極(導電体膜)との間
の強誘電体膜に作用するので、この種の不揮発性半導体
記憶装置を低電圧動作させることができる。また、金属
原子を含む導電体膜は、強誘電体膜との整合性が良いの
で、強誘電体膜の結晶配向性が向上する。The operation of the present invention is as follows. That is,
According to the present invention, almost all of the voltage applied to the ferroelectric capacitor acts on the ferroelectric film between the upper electrode and the lower electrode (conductor film). The device can be operated at a low voltage. In addition, since the conductor film containing metal atoms has good matching with the ferroelectric film, the crystal orientation of the ferroelectric film is improved.
【0012】[0012]
【実施例】以下、図面を参照して本発明の一実施例を説
明する。図1は、本発明の一実施例に係る不揮発性半導
体記憶装置の構成を示した断面図である。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a configuration of a nonvolatile semiconductor memory device according to one embodiment of the present invention.
【0013】図中、符号11は半導体基板としてのP型
のGaAs基板である。なお、基板材料としては、シリ
コン基板、あるいはシリコン基板上に成長させたGaA
s等であってもよい。GaAs基板11中には、N+ 領
域であるドレイン拡散層12とソース拡散層13とが形
成されている。両拡散層12および13の間のチャネル
領域には、トランジスタの閾値を制御するためのN- 拡
散層14が形成されている。In FIG. 1, reference numeral 11 denotes a P-type GaAs substrate as a semiconductor substrate. The substrate material is a silicon substrate or GaAs grown on a silicon substrate.
s or the like. In the GaAs substrate 11, a drain diffusion layer 12 and a source diffusion layer 13, which are N + regions, are formed. In the channel region between the two diffusion layers 12 and 13, an N - diffusion layer 14 for controlling the threshold value of the transistor is formed.
【0014】N- 拡散層14の上には、電界効果トラン
ジスタTrのゲート電極と、強誘電体キャパシタFCの
下部電極とを兼ねる金属電子を含んだ導電体膜15と、
強誘電体膜16と、上部電極17とが、その順に積層さ
れている。ここでは、導電体膜15として白金(Pt)
を用い、強誘電体膜16としてPZT(PbZrX Ti
1-X O3 )を用いている。その理由は、PZTをPt上
に形成すると、結晶配向性のよい強誘電体膜が得られる
からである。On the N - diffusion layer 14, a conductive film 15 containing metal electrons also serving as a gate electrode of the field effect transistor Tr and a lower electrode of the ferroelectric capacitor FC;
The ferroelectric film 16 and the upper electrode 17 are stacked in that order. Here, platinum (Pt) is used as the conductive film 15.
And PZT (PbZr x Ti) as the ferroelectric film 16
1-X O 3 ) is used. The reason is that when PZT is formed on Pt, a ferroelectric film having good crystal orientation can be obtained.
【0015】なお、導電体膜15としては、Pt以外に
Au等を用いることもできる。また、強誘電体膜として
は、PZTに限らず、同種のABO3 型(A,Bは金属
元素)であるペロブスカイト構造のもの(例えば、PL
ZT、PbTiO3 、BaTiO3 等)であってもよ
い。また、他の強誘電体物質として、BaMgF4 、N
aCaF3 、K2 ZnCl4 等のハロゲン化合物や、Z
n1-X CdX Te、GeTe、Sn2 P2 S6 等のカル
コゲン化合物を用いることもできる。The conductor film 15 may be made of Au or the like in addition to Pt. The ferroelectric film is not limited to PZT, but has a perovskite structure of the same type of ABO 3 type (A and B are metal elements) (for example, PLZT).
ZT, PbTiO 3 , BaTiO 3, etc.). In addition, BaMgF 4 , N
halogen compounds such as aCaF 3 and K 2 ZnCl 4 ;
Chalcogen compounds such as n 1 -x Cd x Te, GeTe, and Sn 2 P 2 S 6 can also be used.
【0016】また、導電体膜15の金属原子が基板中へ
スパイクするのを防止するために、導電体膜15を積層
構造にするのが好ましい。例えば、シリコン基板では、
導電体膜15として、Pt/PtSiや、Au/AuS
iを用いるのが好ましい。Further, in order to prevent metal atoms of the conductor film 15 from spiking into the substrate, it is preferable that the conductor film 15 has a laminated structure. For example, on a silicon substrate,
As the conductor film 15, Pt / PtSi, Au / AuS
It is preferred to use i.
【0017】上部電極17としては、Pt等の金属の他
に、燐等をドープしたポリシリコン膜を用いてもよい。
なお、図1中の符号18は燐をドープしたSiO2 (P
SG)やボロンをドープしたPSG等からなる層間絶縁
膜、19はドレイン拡散層12およびソース拡散層13
にそれぞれ個別に接続される金属配線である。As the upper electrode 17, a polysilicon film doped with phosphorus or the like may be used in addition to a metal such as Pt.
Reference numeral 18 in FIG. 1 denotes SiO 2 (P
SG), an interlayer insulating film made of boron-doped PSG or the like, and 19 is a drain diffusion layer 12 and a source diffusion layer 13.
Are individually connected to metal wiring.
【0018】図2は、上述した不揮発性半導体記憶装置
(MFSFET素子)の等価回路図である。図中、Tr
は、ドレイン拡散層12、ソース拡散層13、N- 拡散
層14、および導電体膜15からなる電界効果トランジ
スタである。FCは、導電体膜15、強誘電体膜16、
および上部電極17からなる強誘電体キャパシタであ
る。FIG. 2 is an equivalent circuit diagram of the above-mentioned nonvolatile semiconductor memory device (MFSFET element). In the figure, Tr
Is a field effect transistor including a drain diffusion layer 12, a source diffusion layer 13, an N − diffusion layer 14, and a conductor film 15. FC is a conductor film 15, a ferroelectric film 16,
And a ferroelectric capacitor including the upper electrode 17.
【0019】上述したMFSFET素子の製造方法を簡
単に説明する。まず、GaAs基板11中にN- 拡散層
14を形成する。続いて、導電体膜15、強誘電体膜1
6、上部電極17をその順に積層する。強誘電体膜16
を形成するためのPZT等の強誘電体物質は、スピンコ
ートによるゾルゲル法やMOD(Metal Organic Decomp
osition)法、あるいはスパッタリング法、MOCVD(M
etal Organic Chemical Vapor Deposition) 法、レーザ
アブレーション法で被着する。前記積層された各膜を、
イオンミリイング、反応性イオンエッチング(RIE)
等の異方性エッチングで連続的に加工する。以上のよう
にして形成された強誘電体キャパシタFCをマスクとし
て、N型不純物をイオン注入して、ドレイン拡散層12
およびソース拡散層13を形成する。次に、層間絶縁膜
18をCVD(Chemical Vapor Deposition)法で堆積
し、ドレイン・ソース拡散層12、13の領域にコンタ
クトホールを形成した後、金属膜を被着し、これをパタ
ーンニングして金属配線19を形成する。A method for manufacturing the above-mentioned MFSFET device will be briefly described. First, an N - diffusion layer 14 is formed in a GaAs substrate 11. Subsequently, the conductor film 15, the ferroelectric film 1
6. The upper electrode 17 is laminated in that order. Ferroelectric film 16
The ferroelectric substance such as PZT for forming the sol is formed by a sol-gel method using spin coating or MOD (Metal Organic Decomp.).
osition) method, sputtering method, MOCVD (M
(etal Organic Chemical Vapor Deposition) method, laser ablation method. Each of the laminated films is
Ion milling, reactive ion etching (RIE)
Process continuously by anisotropic etching such as Using the ferroelectric capacitor FC formed as described above as a mask, an N-type impurity is ion-implanted to form the drain diffusion layer 12.
And a source diffusion layer 13 is formed. Next, an interlayer insulating film 18 is deposited by a CVD (Chemical Vapor Deposition) method, a contact hole is formed in a region of the drain / source diffusion layers 12 and 13, and a metal film is deposited and patterned. The metal wiring 19 is formed.
【0020】次に、上述したMFSFET素子の動作を
説明する。GaAs基板11等の半導体基板上に、Pt
等の金属、あるいはPtSi等の導電性の金属化合物か
らなる導電体膜15を直接形成すると、ショットキー障
壁ができ、導電体膜15の両側にドレイン拡散層12お
よびソース拡散層13を形成することにより、FET素
子が構成される。このFET素子は、ゲート電極である
導電体膜15に電圧を発生させることにより、導通・非
導通の各状態に切り換えることができる。Next, the operation of the above-mentioned MFSFET device will be described. Pt is deposited on a semiconductor substrate such as a GaAs substrate 11.
When the conductor film 15 made of a metal such as PtSi or a conductive metal compound such as PtSi is directly formed, a Schottky barrier is formed, and the drain diffusion layer 12 and the source diffusion layer 13 are formed on both sides of the conductor film 15. Thereby, an FET element is configured. The FET element can be switched between a conductive state and a non-conductive state by generating a voltage on the conductive film 15 serving as a gate electrode.
【0021】そこで、前記導電体膜15を下部電極とす
る強誘電体キャパシタFCを、FET素子のチャネル領
域上に形成し、前記強誘電体キャパシタFCの上部電極
17に電圧(図1の実施例では負電圧)を印加すると、
導電体膜15に電圧(実施例では正電圧)が発生し、こ
れによりチャネルが形成されてFETが導通状態にな
る。その後、上部電極17の電圧を0Vにしても、強誘
電体膜16の自発分極により、導電体膜15と基板11
間の電圧が保持され、FETは導通状態のまま維持され
る。Therefore, a ferroelectric capacitor FC having the conductive film 15 as a lower electrode is formed on the channel region of the FET element, and a voltage is applied to the upper electrode 17 of the ferroelectric capacitor FC (the embodiment of FIG. 1). Applying a negative voltage)
A voltage (positive voltage in the embodiment) is generated in the conductor film 15, whereby a channel is formed and the FET becomes conductive. Thereafter, even when the voltage of the upper electrode 17 is set to 0 V, the spontaneous polarization of the ferroelectric film 16 causes the conductive film 15 and the substrate 11
The voltage between them is held, and the FET is kept conductive.
【0022】一方、強誘電体キャパシタFCの上部電極
17に正電圧を印加するか、あるいは図2に示すよう
に、導電体膜15から導出した端子T’に負電圧を印加
すると、強誘電体膜16の自発分極の極性が反転し、F
ETが非導通状態になって、そのまま維持される。On the other hand, when a positive voltage is applied to the upper electrode 17 of the ferroelectric capacitor FC or a negative voltage is applied to the terminal T ′ derived from the conductor film 15 as shown in FIG. The polarity of the spontaneous polarization of the film 16 is reversed, and F
ET becomes non-conductive and is maintained as it is.
【0023】以上のように、MFSFET素子の導通・
非導通を、データの『0』、『1』に対応付けることに
よって、電源電圧を印加しなくても書き込み状態を維持
する、不揮発性メモリが実現される。As described above, the conduction of the MFSFET element
By associating non-conduction with data “0” and “1”, a nonvolatile memory that maintains a written state without applying a power supply voltage is realized.
【0024】[0024]
【発明の効果】以上の説明から明らかなように、本発明
によれば、電界効果トランジスタのチャネル領域上に強
誘電体キャパシタを備え、前記キャパシタの強誘電体膜
の自発分極を利用して情報を記憶する不揮発性半導体記
憶装置において、半導体基板上または基板上に形成され
た半導体層上に、前記キャパシタの下部電極および前記
電界効果トランジスタのゲート電極とを兼ねる金属原子
を含む導電体膜を直接形成させているので、強誘電体キ
ャパシタに印加された電圧の殆ど全てが強誘電体膜に作
用する。したがって、強誘電体膜と半導体基板との間に
絶縁膜からなるバッファ層を設けていた従来の記憶装置
に比べて、記憶装置を低い電圧で動作させることができ
る。As is apparent from the above description, according to the present invention , a strong effect is formed on the channel region of the field effect transistor.
A ferroelectric film comprising a dielectric capacitor
Nonvolatile semiconductor memory that stores information using spontaneous polarization
Memory device, formed on a semiconductor substrate or on a substrate
Since the conductor film containing metal atoms also serving as the lower electrode of the capacitor and the gate electrode of the field-effect transistor is directly formed on the semiconductor layer , almost all of the voltage applied to the ferroelectric capacitor is reduced. Acts on ferroelectric films. Therefore, the memory device can be operated at a lower voltage than a conventional memory device in which a buffer layer made of an insulating film is provided between a ferroelectric film and a semiconductor substrate.
【0025】また、金属原子を含む導電体膜の上に、結
晶配向性のよい強誘電体膜を形成することができるの
で、強誘電体膜の自発分極が大きくなり、それだけ読み
取りマージンが増大し、実用性の高い不揮発性半導体記
憶装置を実現することができる。In addition, since a ferroelectric film having good crystal orientation can be formed on a conductive film containing metal atoms, spontaneous polarization of the ferroelectric film increases, and the reading margin increases accordingly. Thus, a highly practical nonvolatile semiconductor memory device can be realized.
【図1】本発明の一実施例に係る不揮発性半導体記憶装
置の素子構造を示した断面図である。FIG. 1 is a sectional view showing an element structure of a nonvolatile semiconductor memory device according to one embodiment of the present invention.
【図2】図1に示した装置の等価回路図である。FIG. 2 is an equivalent circuit diagram of the device shown in FIG.
【図3】従来例に係るMFSFET素子の構造を示した
断面図である。FIG. 3 is a cross-sectional view showing a structure of a conventional MFSFET device.
【図4】強誘電体膜のヒステリシス特性を示した図であ
る。FIG. 4 is a diagram showing a hysteresis characteristic of a ferroelectric film.
11…GaAs基板 12…ドレイン拡散層 13…ソース拡散層 14…N- 拡散層 15…導電体膜 16…強誘電体膜 17…上部電極 18…層間絶縁膜 19…金属配線 Tr…電界効果トランジスタ FC…強誘電体キャパシタDESCRIPTION OF SYMBOLS 11 ... GaAs substrate 12 ... Drain diffusion layer 13 ... Source diffusion layer 14 ... N - diffusion layer 15 ... Conductor film 16 ... Ferroelectric film 17 ... Upper electrode 18 ... Interlayer insulating film 19 ... Metal wiring Tr ... Field effect transistor FC ... Ferroelectric capacitors
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) G11C 11/22 G11C 16/04 H01L 21/8247 H01L 29/788 H01L 29/792 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) G11C 11/22 G11C 16/04 H01L 21/8247 H01L 29/788 H01L 29/792
Claims (1)
に強誘電体キャパシタを備え、前記キャパシタの強誘電
体膜の自発分極を利用して情報を記憶する不揮発性半導
体記憶装置において、半導体基板上または基板上に形成された半導体層上 に、
前記キャパシタの下部電極および前記電界効果トランジ
スタのゲート電極とを兼ねる金属原子を含む導電体膜を
直接形成させたこと、 を特徴とする不揮発性半導体記憶装置。[Claim 1 further comprising a ferroelectric capacitor on a channel region of a field effect transistor, the nonvolatile semiconductor memory device that stores the information by utilizing the spontaneous polarization of the ferroelectric film of the capacitor, the semiconductor substrate or substrate On the semiconductor layer formed above ,
A conductor film containing metal atoms also serving as a lower electrode of the capacitor and a gate electrode of the field effect transistor
A non-volatile semiconductor memory device formed directly .
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32393091A JP3169406B2 (en) | 1991-11-11 | 1991-11-11 | Nonvolatile semiconductor memory device |
US07/973,074 US5303182A (en) | 1991-11-08 | 1992-11-06 | Nonvolatile semiconductor memory utilizing a ferroelectric film |
US08/149,068 US5345415A (en) | 1991-11-08 | 1993-11-09 | Nonvolatile semiconductor memory utilizing a ferroelectric film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32393091A JP3169406B2 (en) | 1991-11-11 | 1991-11-11 | Nonvolatile semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05135570A JPH05135570A (en) | 1993-06-01 |
JP3169406B2 true JP3169406B2 (en) | 2001-05-28 |
Family
ID=18160220
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32393091A Expired - Fee Related JP3169406B2 (en) | 1991-11-08 | 1991-11-11 | Nonvolatile semiconductor memory device |
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JP (1) | JP3169406B2 (en) |
Cited By (1)
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---|---|---|---|---|
US11502103B2 (en) * | 2018-08-28 | 2022-11-15 | Intel Corporation | Memory cell with a ferroelectric capacitor integrated with a transtor gate |
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---|---|---|---|---|
US6385120B1 (en) * | 2000-12-22 | 2002-05-07 | Texas Instruments Incorporated | Power-off state storage apparatus and method |
KR100866314B1 (en) * | 2006-12-13 | 2008-11-03 | 서울시립대학교 산학협력단 | MFMS FET and ferroelectric memory device |
KR101559995B1 (en) * | 2007-10-26 | 2015-10-15 | 서울시립대학교 산학협력단 | MFMS-FET ferroelectric memory device and Methods of manufacturing the same |
-
1991
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US11502103B2 (en) * | 2018-08-28 | 2022-11-15 | Intel Corporation | Memory cell with a ferroelectric capacitor integrated with a transtor gate |
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