JP3168657B2 - Branch instruction control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a register file (RE)
Instruction that performs branching using the value of (G) as the instruction address of the branch destination
(Register branch instruction).

Generally, in an information processing apparatus, a branch instruction used when returning from a subroutine is a specific register of a register file (REG), for example, the register number is the last number of the register file (REG). The return destination is often given by a register.

This is a fixed result in order to make it easy to provide an interface between programs, and the compiler often uses only a fixed register number for the register branch instruction.

Focusing on this point, by providing a special copy register (RAR) only for the register of the register number (RARN) holding the return address, the register file (REG) can be read in a read cycle. The return address can be generated without waiting for the result, and it can be expected that the register branching speeds up.

[0005]

2. Description of the Related Art FIGS. 6 to 8 are diagrams for explaining a conventional branch operation. FIG. 6 shows a case of a register branch.
8 shows a case of a relative branch using an instruction buffer and a program counter (PC). FIG.
A case where a high-speed branch is performed using a dedicated register port is shown.

Here, a so-called pipeline-controlled information processing device is taken as an example. "Inst Fetch" indicates an instruction fetch state, "Decode" indicates a decode state, and "Execute" indicates an execution state. ,In particular,
The memory access instruction calculates the operand address, the other instructions indicate a state in which an arithmetic operation, a logical operation, and the like are performed, “Data Fetch” indicates the state of operand data fetch, and “Write” indicates a register file (REG file). ).

A branch instruction used when returning from a subroutine (return) is generally a register file (REG).
1 (for example, when the register file (REG) 1 is composed of 16 registers, the register number is “15”) and the branch destination (return destination) is given. Can be

[0008]

FIG. 6 schematically shows the operation of the register branch. The branch instruction (BRANCH) is
Referring to the register file (REG) 1 to recognize the address of the branch destination and perform the branch, as shown in the figure,
Disrupts the pipeline and slows down the execution of the pipeline.
In this example, there is a delay of 1τ.

However, in the case of a relative branch using the instruction buffer (IB) 5 and the program counter (PC) 6 or an absolute branch using the instruction buffer (IB) 5, the instruction buffer (read ahead) performed by the pipeline is used. IB) 5 and the above-mentioned “Inst F
By performing the address calculation in the "etch" state,
As shown in (1), the delay of the pipeline due to the branch can be eliminated.

Also in the case of branching by the above-mentioned register, the contents of the prefetched instruction buffer (IB) 5 are used and the branch address is generated by the dedicated register read port 10a, as shown in FIG. As described above, it is possible to prevent the flow of the pipeline from being disturbed.However, a dedicated read port 10a is required for the register file (REG) 1, which increases the physical quantity and increases the capacity of the register file (REG) 1. The complexity of the output port selector leads to an increase in the access time of the port, resulting in a problem of increasing the machine cycle.

The present invention has been made in view of the above-mentioned conventional drawbacks, and provides a branch instruction control circuit of an information processing apparatus provided with an instruction (register branch instruction) for performing a branch using a value of a register file (REG) as a branch destination instruction address. It is an object of the present invention to provide a branch instruction control circuit capable of suppressing an increase in register ports and an increase in access time.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. The above problem is solved by a branch instruction control circuit configured as follows.

A specific register 10 of a register file (REG) 1 comprising a plurality of registers to be read and written by a program 10
In the information processing apparatus provided with a register branch instruction for performing a branch having the value of the branch destination as an instruction address, a specific register 10 of the register file (REG) 1, a copy register (RAR) 2 having the same contents, A prefetched instruction is a branch instruction, and a return address match detection circuit A30 for detecting a match between a value of a register address field indicating a branch destination address of the branch instruction and an address of the specific register 10; The register file (REG) 1
And the specific register 10
A write address match detection circuit B 31 for detecting a match with the address of the register file (REG) 1, output data of the copy register (RAR) 2, and an instruction address addition circuit (IF ADDER) 7. The instruction fetch address selection circuit (IF) that selects and selects the instruction address generated by the above-described method by controlling the address coincidence signal of the return address coincidence detection circuit A 30 and the instruction fetch control signal to output the instruction fetch address.
ADRS SELECT) 3 and when a write address match detection signal is obtained from the write address match detection circuit B 31, a specific register of the register file (REG) 1 is stored in the copy register (RAR) 2. 10, the same data as the data to be written into the copy register is written. When the instruction fetch control signal instructs execution of the register branch instruction and the address match signal from the return address match detection circuit A 30 is obtained,
(RAR) 2
(IF ADRS SELECT) 3 and output. When the instruction fetch control signal indicates the execution of the register branch instruction and the address match signal from the return address match detection circuit A 30 is not obtained, The value of the register file (REG) 1 is selected and output by the instruction fetch address selection circuit (IF ADRS SELECT) 3.

[0014]

As described above, in many cases, the register number of the register file (REG) 1 holding the required return address when returning from the subroutine (return) is set to, for example, When the number of register files (REG) 1 is 16, it is fixed to the 16th register (that is, the register whose register number is “15”).

Therefore, most compilers and the like only use a fixed register number for a register branch instruction. The present invention focuses on the fact that there is this phenomenon in the operation of a register branch instruction in a program, and in the register file (REG) 1, a register of a specific register number (RARN) holding this return address. 10 only, a special copy register (RAR) 2 is provided so that the register number indicated by the prefetched register branch instruction is the register number of the specific register 10 (for example, 15
When an address match signal is obtained from the return address match detection circuit A 30 for detecting the match with the (RARN), a branch address is generated using the value of the copy register (RAR) 2. In this way, register branching is performed at high speed without using the read output from the register file (REG) 1.

Naturally, in the present invention, when there is a write instruction to the specific register 10 of the register file (REG) 1, the same write data is also written to the copy register (RAR) 2. It is necessary to keep it.

However, even with the register branch instruction, the register number specified by the register branch instruction does not match the specific register number (RARN), and the copy register (RAR) 2 cannot be used. Occasionally, a register branch using the conventional register file (REG) 1 is performed.

Therefore, according to the present invention, the speed of register branch can be increased without increasing the register output port 10a of the register file (REG) 1 and without increasing the access time of the register output port 10a. There are effects that can be performed.

Further, according to the branch instruction control circuit according to the present invention, even when register interference with the specific register 10 occurs, the same operation as in the related art can be performed without using a special circuit, as described later. By using the bypass circuit, register branching can be performed at high speed, which does not hinder the present invention.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 described above is a principle configuration diagram of the present invention.
FIG. 3 is a diagram showing one embodiment of the present invention, and FIG.
Shows an operation flow, and FIG. 3 shows a logical condition of the instruction address selection circuit. FIGS. 4 and 5 are diagrams showing the operation of register branching when there is register interference.
FIG. 4 shows the case where the instruction before the register branch instruction is a load instruction, and FIG. 5 shows the case where the instruction before the register branch instruction is an operation instruction.

In the present invention, a register file (REG) 1 comprising a plurality of registers to be read and written by a program 1
In the information processing apparatus provided with a register branch instruction for performing a branch using the value of the specific register 10 as a branch destination instruction address, the specific register of the register file (REG) 1
10, a copy register (RAR) 2 having the same contents, a value of a register address field indicating a branch destination address of the branch instruction where the prefetched instruction is a branch instruction, and an address of the specific register 10. A return address match detection circuit A 30 for detecting a match with the register file (REG) 1, a write address match detection circuit B 31 for detecting a match between the write address for the register file (REG) 1 and the address of the specific register 10, Register file (REG) 1 read data and the above copy register
(RAR) 2 output data and the instruction address adder (IF
ADDER) An instruction fetch address selection circuit for controlling and selecting an instruction address generated by 7 or the like by using an address match signal of the return address match detection circuit A 30 and an instruction fetch control signal, and outputting an instruction fetch address. 3 is the means necessary to carry out the present invention. Note that the same reference numerals indicate the same object throughout the drawings.

Hereinafter, the configuration and operation of the branch instruction control circuit according to the present invention will be described with reference to FIGS. First, FIG. 3 shows the branch instruction control circuit according to the present invention shown in FIG. 1, particularly, an instruction address selection circuit (IF ADRS SELEC).
T) The selection logic of 3 is shown.

A prefetched register branch instruction (Regis
The register number (Return-reg-adrs) indicating the branch destination address of (ter-Branch-Instruction) is stored in the register file (R
EG) 1 indicating the number (RARN) of the specific register 10 and when the address match detection signal is output from the return address match detection circuit A 30 described above, the copy register (RAR) 2 of the present invention is used. Is output as the instruction fetch address of the branch destination (indicated by *). If the address match detection signal is not output from the return address match detection circuit A 30, the register file (REG) 1 is read. Is completed, the read data is output (indicated by **) as the instruction fetch address of the branch destination.

A non-register branch instruction (Non-Reg
In the case of ister-Branch-Instruction), the value of the program counter (PC) + the relative value (OFFSET), which is the output of the dedicated instruction address adder (IF ADDER) 7 shown in FIG. Shown), but not a branch instruction (Non-Branch-In
struction) contains the program counter (PC) + instruction length (LEN
GTH of INSTRUCTION) is output (indicated by ##).

The instruction address selection circuit (IF ADRS S
Although not directly related to the logic of (ELECT) 3, in FIG. 1, a write address match detection circuit B 31 detects a match between a write address for the register file (REG) 1 and an address of the specific register 10. When a match is obtained (when a match signal is output), the same data as the data (Write Data) to be written to the register 10 of the specific register number (RARN) of the register file (REG) 1 is written according to the present invention. It operates to write to the copy register (RAR) 2.

The operation of register branching by the branch instruction control circuit of the present invention which operates as described above will be described below with reference to the operation flow of FIG. 1) First, the instruction prefetched in the instruction buffer (IB) 5 is pre-decoded in the “Inst Fetch” state, and the register branch instruction (BRANCH) and the register number indicating the branch destination address are stored in the register file. (REG) 1 coincides with the specific register number (RARN) of FIG.
When the address match detection circuit A 30 detects the address (ie, when the RAR is hit), the address match signal causes the value of the copy register (RAR) 2 to be used as the address of the instruction at the branch destination and the “Decode” state And set it to the program counter (PC) and use it as the instruction fetch address.

At this time, in many cases, the instruction fetch address is, as shown in the operation flow of FIG.
Used as the address of the instruction cache memory (ICACHE) 8.

2) Predecode the instruction prefetched in the instruction buffer (IB) 5 in the "Inst Fetch" state,
A register branch instruction (BRANCH), but the register number indicating the branch destination address does not match the specific register number (RARN) of the register file (REG) 1 (i.e.,
When the RAR is not hit), as shown in the operation flow of FIG. 2, the instruction at the branch destination is stopped by 1τ (that is, interlocked) and the register branch instruction (BRANCH) is registered in the register file (REG). Waiting to read 1 and when the reading of the register file (REG) 1 is completed, the value is determined as the address of the branch target instruction, and the program counter (PC) is set in the “Inst Fetch” state of the branch target instruction. ) Set to 6 to use as an instruction fetch address.

The instruction prefetched in the instruction buffer (IB) 5 is pre-decoded, and if the instruction is not a register branch instruction (BRANCH), the same control as in the prior art is performed. 3) Instruction buffer (IB) 5
In the case of a branch instruction other than a register branch instruction by pre-decoding in the `` nst Fetch '' state, a field for generating a branch destination address of the prefetched instruction buffer (IB) 5 and a program counter (PC) 6 etc. , "Inst Fet
In the "ch" state, the address of the branch destination instruction is generated using the above-mentioned instruction address addition circuit (often constituted by an adder) (IF ADDER) 7 and the branch destination instruction ( In the “Inst Fetch” state of the following instruction), the program counter (PC) 6 is set and used as an instruction fetch address. << Refer to Fig. 7 >> 4) The instruction read ahead in the instruction buffer (IB)
When the instruction is pre-decoded in the “nst Fetch” state and the instruction is not a branch instruction, the program counter (PC) 6
When, the instruction length and the like of the instruction set in the instruction buffer (IB) 5, and generates the address of the instruction subsequent, "Inst Fetch" state in the program counter of the next instruction (P
C) Set to 6 to use as an instruction fetch address.

When writing to the copy register (RAR) 2 according to the present invention, the number of the write register is the number (RARN) of the specific return address of the register file (REG) 1.
(That is, when a match detection signal is obtained from the write address match detection circuit B 31 in FIG. 1).
To do.

Therefore, the preceding instruction sets the copy register (R
When writing to (AR) 2, register interference occurs.Normally, until the value of the copy register (RAR) 2 becomes correct, the register branch instruction (BRANCH) of the copy register (RAR) 2 The branch destination address by value cannot be set in the program counter (PC) 6.

The operation in this case is shown in FIGS. FIG. 4 shows a case where the preceding instruction is a load (LOAD) instruction. As shown in FIG. 4, the register branch instruction (B
RANCH) is interlocked in the "Decode" state.

In a normal operation, regardless of whether the instruction is a branch instruction or an operation instruction, if the instruction refers to the register file (REG) 1, if the register interference occurs,
It is configured to interlock. Therefore, if an attempt is made to control only the register branch instruction (BRANCH) so as to avoid the interlock due to the register interference, the corresponding circuit becomes complicated and does not have a good effect on the start timing of the subsequent instruction.

That is, in the branch control circuit to which the present invention is applied, as shown in FIG. 4, when there is register interference between the preceding instruction and the register branch instruction (BRANCH), the conventional control is not performed. By using the same bypass circuit, high-speed register branching can be performed. In this case, the instruction fetch address selection circuit (IF ADRS SEL
ECT) 3, as shown in the selection logic of FIG. 3, write data (Write Data) to the register file (REG) 1
Will be selected.

Therefore, even if the present invention is applied, it is not necessary to add or change a further circuit for register interference control.
It does not hinder the present invention. In FIG. 4 above,
FIG. 5 shows a case where the preceding instruction is a load instruction.
The case where the preceding instruction is an operation instruction (ADD) is shown. FIG.
As in the case of (1), a high-speed register branch is performed using a bypass circuit.

In an information processing apparatus that does not have a bypass circuit for performing high-speed operation when the register interference occurs, writing to the register file (REG) 1 and the copy register (RAR) 2 is performed once. The address generation may be performed from this point, and in this case, the circuit is not increased or changed. Of course, as described above, even when the pipeline control is not performed, the effect of the copy register (RAR) 2 does not change, and the added amount does not change.

Thus, the present invention provides a register file
In a branch instruction control circuit of an information processing apparatus provided with an instruction (register branch instruction) for performing a branch using the value of (REG) as a branch destination instruction address, a register number (return address holding a return address from a subroutine) is stored. RARN) register file (REG) and copy register (R
AR), the prefetched instruction is a register branch instruction, and the register number indicating the branch destination address of the register branch instruction is the register number (RARN) of the register file (REG) holding the return address. When the value matches, the value of the copy register (RAR) is set as the address of the next instruction (branch destination instruction) in the program counter (PC), and the instruction fetch address is used. The value read in the read state of (REG) is set as the address of the next instruction (branch destination instruction) in the program counter (PC) and used as the instruction fetch address.

[0038]

As described in detail above, the branch instruction control circuit of the present invention corresponds to the register file (REG) of the register number (RARN) holding the return address which is the return address from the subroutine. , Copy register (R
AR), the prefetched instruction is a register branch instruction, and the register number indicating the branch destination address of the register branch instruction is the register number (RARN) of the register file (REG) holding the return address. When the value matches, the value of the copy register (RAR) is set as the address of the next instruction (branch destination instruction) in the program counter (PC) and used as the instruction fetch address. ) Is set in the program counter (PC) as the address of the next instruction (branch destination instruction) and used as the instruction fetch address.
There is an effect that register branching can be performed at high speed without increasing the number of output ports of the register file (REG) and without increasing the access time of the port.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention.

FIG. 2 shows an embodiment of the present invention (part 1).

FIG. 3 shows an embodiment of the present invention (part 2).

FIG. 4 is a diagram showing an operation of register branch when register interference occurs (part 1);

FIG. 5 is a diagram showing an operation of register branch when register interference occurs (part 2);

FIG. 6 is a view for explaining a conventional branch operation (part 1);

FIG. 7 illustrates a conventional branch operation (part 2).

FIG. 8 is a view for explaining a conventional branch operation (part 3);

[Explanation of symbols]

1 Register file (REG) 2 Copy register (RAR) 3 Instruction address selection circuit (IF ADRS SELECT) 30 Return address match detection circuit A 31 Write address match detection circuit B 4 Instruction fetch address selection circuit (IF ADRS SELEC)
T) 5 Instruction buffer (IB) 6 Program counter (PC) 7 Instruction address adder (IF ADDER) , address match detection signal Instruction control signal (IF-Control) Write data (Write Data) Bypass circuit Copy register (RAR) output

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-54-36148 (JP, A) JP-A-1-118930 (JP, A) JP-A-2-121034 (JP, A) JP-A-2- 232726 (JP, A) JP-A-3-77137 (JP, A) JP-A-1-222332 (JP, A) JP-A 1-258032 (JP, A) JP-A 2-155038 (JP, A) JP-A-4-348430 (JP, A) JP-A-5-120013 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/32-9/42

Claims (1)

(57) [Claims] A specific register (1) of a register file (REG) (1) comprising a plurality of registers to be read and written by a program.
An information processing apparatus provided with a register branch instruction for performing a branch using the value of (0) as a branch destination instruction address, comprising: a specific register (10) of the register file (REG) (1);
A copy register (RAR) (2) having the same contents, a value of a register field indicating a branch destination address of the branch instruction where the prefetched instruction is a branch instruction, and an address of the specific register (10). A return address match detection circuit A (30) for detecting a match with the register file (REG) (1) and a write address match detection for detecting a match between the address of the specific register (10) and the write address of the register file (REG) (1). Circuit B (31) and the register file (R
EG) (1) read data and the above copy register (RAR)
Output data () and the instruction address adder (IF ADDE
R) (7), etc., with the address match signal of the return address match detection circuit A (30).
And an instruction fetch address selection circuit (IF ADRS SELECT) (3) for controlling and selecting by the instruction fetch control signal () and outputting an instruction fetch address. When the write address match detection signal () from (31) is obtained, the register file (RE) is stored in the copy register (RAR) (2).
G) The same data as the data () to be written to the specific register (10) of (1) is written, and the instruction fetch control signal () instructs execution of the register branch instruction, and the return address match detection circuit A ( When the address match signal () from (30) is obtained, the value () in the copy register (RAR) (2) is selected and output by the instruction fetch address selection circuit (IF ADRS SELECT) (3). When the instruction fetch control signal () instructs execution of a register branch instruction and the address match signal () from the return address match detection circuit A (30) is not obtained, the register file (REG) A branch instruction control circuit characterized in that the value of (2) is selected and output by the instruction fetch address selection circuit (IF ADRS SELECT) (3).