JP3168560B2 - Failure judgment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for determining whether a failure of an electronic circuit detected by a failure detection unit is a true failure, and more particularly to a failure determination for a failure in a mode in which bit errors and the like occur intermittently. Circuit.

[0002]

2. Description of the Related Art In a device constituted by a conventional electronic circuit, when a failure occurs in an electronic circuit, a failure detection unit detects the failure and notifies the processing system device such as a processor for controlling the device of a failure. If the device has a redundant configuration, the device is switched by a processing system device such as a processor. Further, a processing system device such as a processor notifies a maintenance person or a user of the failure of the device, thereby causing the maintenance person or the user to recognize the necessity of the failure recovery work of the device. However, when a failure of an electronic circuit is detected once and a processing system device such as a processor is notified of the failure of the electronic circuit, the failure of the electronic circuit due to a malfunction caused by some kind of noise or the like may occur. Since a failure that has occurred fixedly due to deterioration of the electronic circuit or the like cannot be identified, it is not possible to notify only a fixedly occurring failure to a processing system device such as a processor. Therefore, a predetermined value for failure determination for a circuit that detects a failure in an electronic circuit is determined in advance, and when it is detected that the counter value of a counter that measures the number of times of failure detection exceeds the specified value, a failure determination in the device is performed. The unit determines that the failure of the electronic circuit is a fixed failure, and notifies the processing system device such as a processor that controls the electronic circuit of the failure of the electronic circuit.

FIG. 2 is a block diagram showing the arrangement of a failure detection unit and a failure determination unit in a conventional device constituted by an electronic circuit. The electronic circuit device includes n failure detection units 101 to 10n and a failure determination unit. The failure determination unit includes a counter 11 that measures the number of times a failure is detected.
0, a comparing unit 111 for comparing a counter value of the counter 110 with a predetermined value (N) for failure determination, and a counter 11
A reset signal transmitting unit 112 for transmitting a reset signal for clearing the counter value of 0 to “0”, a clock unit 113 for supplying a clock, and a cycle for detecting a failure using the clock of the clock unit 113 and a comparing unit 111 Is provided with a cycle determination circuit unit 114 for determining a cycle (same as a failure detection cycle) for performing the comparison. The counter 110 is connected to the failure detection units 101 to 10n and the reset signal transmission unit 112, the comparison unit 111 is connected to a processing system device 115 such as a processor, and the cycle determination circuit unit 114 is connected to the clock unit 113 and the comparison unit 111, and failure detection units 101 to 10
n. When the electronic circuit device is activated, the comparison unit 11
Reference numeral 1 denotes a specified value (N) for failure determination set in firmware or the like in the processing system device 115 when the processing system device 115 is manufactured, using a specified value setting signal transmitted from the processing system device 115 to the comparison unit 111. It has a function of setting a register in the comparison unit 111. If any of the failure detection units 101 to 10n detects a failure in the electronic circuit, the cycle determination circuit unit 11
4 based on the cycle determined by the failure detection unit, the failure detection unit that has detected the failure transmits a failure detection signal notifying that the failure has been detected to the counter 110, and the counter 110 adds a counter value (k) in the counter 110 to the counter value (k). On the other hand, at the same time as calculating k = k + 1, k is notified to the comparing unit 111. The comparing unit 111 compares the specified value (N) with k, and when the result of the comparison is N ≦ k (case 1), sends a failure notification signal notifying that the electronic circuit has failed to the processing system device 115. .
When the comparison result is N> k (case 2), if the comparison unit 111 does not newly receive k within one cycle determined by the cycle determination circuit unit 114, the comparison unit 111 sends the reset signal transmission unit A reset instruction is issued to the counter 112, and the reset signal sending unit 112 sets the counter value in the counter 110 to "0"
When the comparison unit 111 newly receives k from the counter 110 within the range of the cycle, the comparison unit 111
Compares N and k, and performs the processing of Case 1 or Case 2 according to the result.

FIG. 3 is a diagram showing a failure of an electronic circuit (201, 20).
FIG. 4 is a conceptual diagram illustrating a change in the counter value when (4, 206 to 20n) is detected. When the failure detection unit detects the failure 201, it updates the counter value 211 from “0” to “1”. When detecting a failure of the electronic circuit in the failure detection cycle 202 determined by the cycle determination circuit unit, the failure 201 is detected,
After the failure detection cycle 202 has elapsed 203, a failure 204 is detected, and the counter value 211 is updated from “1” to “2”.
Since the failure of the electronic circuit is not detected 205 after the failure detection cycle 202 has elapsed since 03, the failure determination unit
Temporary failure due to malfunction of 204 (electronic circuit is normal)
And the counter value 211 is cleared from "2" to "0" in case a new failure is detected. That is,
If the failure of the electronic circuit is not detected even once continuously, the counter value is cleared to “0”. When the fault 206 is newly detected, the counter value 211 is updated from “0” to “1” in the same manner as when the fault 201 is detected, and the fault 20 is detected.
6, when the failure 207 is detected after the failure detection cycle 202 has elapsed, the counter value 211 is updated from “1” to “2”. Further, the failure 2 is sequentially detected at the failure detection cycle 202 intervals.
When 08 to 20n is detected, the counter value 211 is counted up, and a predetermined failure determination standard value (N) 21
Since the counter value 211 exceeds 0, the failure determination unit determines that the failures 206 to 20n are true failures, and notifies a processing system device such as a processor that the electronic circuit has failed.

[0005]

In the above-mentioned prior art, a failure as shown in FIG. 3 in which the number of times of detection of a failure (counter value) does not exceed a predetermined failure determination limit value (N) is determined. Is not determined to be a true failure, a failure notification signal is not sent to a processing system device such as a processor. Therefore, a processing system device such as a processor cannot recognize a failure in which a bit error or the like occurs intermittently on an electronic circuit. Further, when a failure that does not determine the failure detected by the failure determination unit as a true failure (a several-bit error that occurs during data transfer or the like) occurs, the processing system device such as a processor has the failure. I could not recognize this. Further, since the value held by the firmware or the like is fixedly set in the comparison unit as the prescribed value (N) for failure determination, the electronic circuit device is matched with the failure rate, use environment, operation time, and the like of the electronic circuit device. The specified value (N) could not be changed programmatically during operation of the device. The purpose of the present invention is to provide a
For a failure in which a bit error or the like occurs intermittently, the failure determination is properly performed, and when it is determined that the failure is a true failure, a failure is notified to a processing system device such as a processor, and a failure determination unit. Notify a processing device such as a processor that a failure that does not determine that it is a true failure has occurred, and match the failure rate, use environment, operation time, etc. of the device while operating the electronic circuit device It is an object of the present invention to provide a failure determination device that can set a specified value of the determined failure in a programmable manner.

[0006]

In order to achieve the above object, a failure judgment circuit according to the present invention is provided in a device constituted by an electronic circuit, and a fixed failure and a bit error which occur fixedly in the electronic circuit. etc. are Oh intermittent faults, and noise such as identification and judging trouble determining circuit a temporary failure temporarily occurs due to a malfunction caused by intermittently generating
Ri, a failure detecting means for detecting the failure, and a determining failure determination means the contents of the detected fault, the fault determining means, and the short for failure determination section for determining the permanent fault, the A long-term failure determination unit that determines an intermittent failure, wherein each of the determination units includes a counter that counts a failure detection signal notified from the failure detection unit, and a value set by the counter. A comparison unit for comparing the specified value with a specified value; a reset signal transmission unit for transmitting a reset signal for clearing the count value of the counter; and a cycle monitoring unit for monitoring the counting cycle of the counter, wherein the value counted by each counter is provided. A fault determination circuit that determines that only the fixed fault and the intermittent fault are true faults and that the fault information is notified to a processing device including a processor when the predetermined value exceeds a predetermined value.
A is, the failure determining means further special failure determination unit
The special failure determination unit includes the short-time failure determination
Special counter that counts by receiving the count signal from the counter of the section
A time measurement counter, and a cowl of the long-time failure determination unit.
Special long time counter that counts by receiving the counting signal from the
Measurement counter, special short time measurement counter and special length
Calculates the correlation value of the values counted by the time counter
And compares the calculated correlation value with a preset specified value.
The special comparison unit, the special short-time measurement counter and the special
Reset signal to clear the count value of the long-time measurement counter
Reset signal sending unit that sends a signal and a special failure judgment cycle
And a cycle monitoring unit for monitoring the calculated correlation value.
By exceeding the preset value, the short-time
The failure determination unit and the long-time failure determination unit
Error, including several-bit errors that occur during data transfer
The special failure is determined to be a true failure, and the failure information is determined by the processor.
Is notified to a processing device including

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a long-time measurement counter is provided in a failure judgment circuit and used together with a short-time measurement counter. In other words, a predetermined value for failure determination is set in advance in a comparison unit that determines the counter value of each of the short-time measurement counter and the long-time measurement counter that measures the number of times a failure has been detected, so that failure of the electronic circuit is fixed. In the event of occurrence, the comparator for the short-time measurement counter determines that the detected fault is a true fault by detecting that the counter value exceeds a predetermined value, and fixes the fault. And a processing unit such as a processor, and when an electronic circuit failure occurs intermittently, the comparison unit for the long-time measurement counter performs a predetermined failure determination. By detecting that the counter value exceeds the specified value, the failure is determined as a true failure, and a processing system device such as a processor is notified that the failure has occurred intermittently. In addition, when a failure that cannot be determined by the failure determination unit as a true failure by the failure detection unit (a few-bit error that occurs during data transfer) occurs, a short-time measurement counter is set within a certain period. A weighted value is added to each of the integrated value and the integrated value of the counter value of the long-time measurement counter, and if the added value exceeds a predetermined value, the fault occurs. Is notified to a processing device such as a processor. Further, during the operation of the electronic circuit device, the user or the maintenance person of the device determines the specified value of the failure determination from the operation status of the electronic circuit, the failure rate, etc. When it becomes necessary to change the value, the user or the maintenance person issues a command to change the specified value to the processing device from a workstation or the like connected to the processing device such as a processor, and receives the command. The processing device that has processed the command and resets the comparison unit to a new specified value. Alternatively, based on values obtained by parameterizing the failure rate, use environment, operation time, and the like for the electronic circuit device,
A processing system device such as a processor calculates an optimum specified value for failure determination, and resets a new specified value to the comparing unit.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram of a failure detection unit and a failure determination unit in an electronic circuit device according to a first embodiment of the present invention. The electronic circuit device includes n failure detection units 301 to
30n and a failure determination unit. The failure determination unit includes a short-time failure determination unit and a long-time failure determination unit. The short-time failure determination unit includes a short-time measurement counter 310,
A short-time comparison unit 312, a reset signal transmission unit 314, a clock unit 318, and a cycle determination circuit unit 319 are provided.
11, long-time comparison unit 313, reset signal sending unit 31
5. A period (T) monitoring unit 316 and an activation unit 317 are provided. The short-time measurement counter 310 is connected to the failure detection units 301 to 30n, the short-time comparison unit 312, and the reset signal transmission unit 314, and the long-time measurement counter 311
Are the failure detection units 301 to 30n and the long-time comparison unit 31
3, a start unit 317, and a reset signal sending unit 315, and the cycle determination circuit unit 319 includes a short-time comparison unit 312,
The clock unit 318 is connected to the failure detection units 301 to 30n, and the period (T) monitoring unit 316
15, a short-time comparison unit 312 connected to the activation unit 317
The long-time comparison unit 313 is connected to a processing system device 320 such as a processor. When detecting a failure in the electronic circuit, the failure detection units 301 to 30n use a failure detection signal notifying that the failure has been detected, and use the failure detection signal to notify the failure detection that the failure has been detected. It notifies the measurement counter 311.

The short-time failure determination section has a function of determining whether or not the number of times of continuous detection of a failure in the electronic circuit exceeds a prescribed value for failure determination. The clock unit 318 has a function of supplying a clock having a constant period. The cycle determination circuit unit 319 uses the clock supplied from the clock unit 318 to perform a comparison between the cycle in which the failure detection units 301 to 30n detect a failure and the short-time comparison unit 312 (the same as the failure detection cycle). Has the function of determining The short-time measurement counter 310 is a counter used for short-time measurement. When a failure detection signal is received from the failure detection units 301 to 30n, the counter value (SCV: Short cycle) held by the short-time measurement counter 310 is held. Counter Valu
With respect to e), a function of calculating SCV = SCV + 1 and notifying the calculated SCV to the short-time comparison unit 312 is provided. Further, the short-time measurement counter 310 has a function of clearing the held counter value to “0” by receiving a reset signal from the reset signal sending unit 314. When the electronic circuit device is activated, the short-time comparison unit 312 stores the processing system device 32 such as a processor.
Using a specified value setting signal transmitted from 0 to the comparison unit 312 for a short time, a predetermined value (TVS: Threshold Value fo) for a predetermined failure determination from a processing system device 320 such as a processor.
r Short cycle) can be set in a register in the comparison unit for short time 312. When the SCV is notified from the measurement counter 310 for short time, the SCV and TVS are compared.
If the comparison result is (TVS ≦ SCV) (Case 1), the failure of the electronic circuit is notified to the processing system device 320 such as a processor, and the comparison result is (TVS> SCV).
V) (Case 2), if no SCV is newly received within the range of one cycle determined by the cycle determining circuit unit 319, a reset instruction is issued to the reset signal sending unit 314,
If a new SCV is received within the period, T
It has a function of comparing VS and SCV, and performing the processing of Case 1 or Case 2 according to the result.
The reset signal sending section 314 has a function of sending a reset signal to the short-time measurement counter 310 when receiving a reset signal sending instruction from the short-time comparing section 312.

The long-term failure judging section has a function of judging whether or not the integrated value of the number of times of detecting the failure of the electronic circuit exceeds a prescribed value of the failure judgment within a certain period. The long-time measurement counter 311 has a counter value (LCV: Longcycle Counter Value) used for long-time measurement,
CV = LCV + 1 is calculated, and the LCV is compared with the long-time comparison unit 3.
13 and a function of notifying the activation unit 317. Further, the long-time measurement counter 311 has a function of clearing the held counter value to “0” by receiving a reset signal from the reset signal sending unit 315. The activation unit 317 receives the LCV from the long-time measurement counter 311, and when LCV = 1, before receiving the LCV, LCV = 0 and no failure has occurred. 311 determines that the monitoring of the cycle for measuring the number of detections has not been started, and does not instruct the cycle (T) monitoring unit 316 to start the cycle monitoring. The period (T) monitoring unit 316 starts period (T) monitoring according to an instruction from the activation unit 317,
After the elapse, the reset signal is sent to the reset signal sending unit 3
15 is provided. When the electronic circuit device is activated, the long-time comparison unit 313 uses a specified value setting signal transmitted from the processing system device 320 such as a processor to the long-time comparison unit 313 to generate a predetermined value from the processing system device 320 such as a processor. Specified failure judgment value (TVL: Thre
shold Value for Long cycle)
When the LCV is notified from the long-time measurement counter 311, the LCV and the TV
L is compared, and if the comparison result is (LCV ≦ TVL), the failure information is notified to the processing system device 320 such as a processor. If the comparison result is (LCV> TVL), the long-time measurement counter 311 It has a function of waiting until an LCV is newly notified, and performing the comparison when the LCV is newly notified. Reset signal sending unit 3
Reference numeral 15 has a function of sending a reset signal to the long-time measurement counter 311 when receiving a reset signal sending instruction from the cycle (T) monitoring unit 316. When any one of the failure detection units 301 to 30n detects a failure in the electronic circuit, the failure detection unit that has detected the failure detects
The failure detection signal is transmitted to the failure detection unit 301 and the long-time measurement counter 311.

The short-time measurement counter 310 has the SCV =
SCV + 1 is calculated and notified to the short-time comparison unit 312,
The short-time comparison unit 312 compares the SCV and the TVS, and when the comparison result is (TVS ≦ SCV) (case 1),
Processing system device 3 such as a processor that the electronic circuit has failed
20 and the result of comparison is (TVS> SCV) (Case 2). If no SCV is newly received within one cycle determined by the cycle determination circuit unit 319, the reset signal transmission unit 314 When a reset instruction is issued and an SCV is newly received within the range of the cycle, the TVS and the SC
V is compared, and the processing of case 1 or case 2 is performed according to the result. On the other hand, the long-time measurement counter 311 that has received the failure detection signal calculates LCV = LCV + 1 and notifies the long-time comparison unit 313 and the activation unit 317.
The long-time comparison unit 313 compares the LCV and the TVL, and when the comparison result is (TVL ≦ LCV), notifies the processing system device 320 such as a processor of failure information, and compares the comparison result (TVL> LCV). In case of, measurement counter 3 for long time
It is on standby until LCV 11 is newly notified.
When the LCV received from the long-time measurement counter 311 is LCV = 1, the activation unit 317 monitors the period (T) monitoring unit 31
6 is instructed to start period monitoring, and a period (T) monitoring unit 316 is provided.
Starts the cycle (T) monitoring when receiving the instruction, and instructs the reset signal sending unit 315 to send a reset signal after the elapse of the T time.
When the instruction is received, the long-time measurement counter 3
A reset signal is sent to 11 to clear the LCV to "0".

FIG. 4 is a conceptual diagram showing a case where a fault in which a bit error or the like occurs intermittently is detected, and the long-time fault determining unit determines that the fault is a true fault. The method of counting up the number of failure detections in the short-time failure determination unit is performed in the same manner as the conventional method, and since the failures 401 to 40n do not occur continuously, the SCV 410 determines the predetermined value of the failure determination (TVS). Does not exceed 411. Therefore, the short-time failure determination unit does not determine 401 to 40n as true failures. On the other hand, in the method of counting up the number of times of failure detection in the long-time failure determination unit, the failure detection unit detects the failure 401, updates the LCV 413 from “0” to “1”, and starts the cycle (T) monitoring 412 at the same time. I do. Further, faults 402 to 40n are detected within the period (T), and the LCV is set to (n
-1) Counting up times, and when the predetermined value (TVL) 414 of the failure determination becomes equal to the LCV, the long-time failure determination unit determines 401 to 40n as a true failure, and And other processing system devices.

FIG. 5 shows a method for detecting a failure that has occurred in a fixed manner.
It is a conceptual diagram when the short-time failure determination part determines the failure as a true failure. When the failure detecting unit detects the failure 501, the SCV 513 is updated from “0” to “1”,
At the same time as updating V514 from “0” to “1”, the period (T) monitoring 510 is started. Further, failures 502 to 5
0n occur continuously, the SCV and LCV are set to (n
-1) Counting up times, the TVL 512 and the LCV become the same, and the short-time failure determination unit determines 501 to 50n as true failures and notifies failure information to a processing system device such as a processor.

FIG. 6 shows a fault temporarily generated due to a malfunction due to noise or the like, and neither the short-time fault judging section nor the long-term fault judging section judges the fault as a true fault. It is a conceptual diagram in the case. When the failure detection unit detects the failure 601, it updates the SCV 612 from “0” to “1”, updates the LCV 614 from “0” to “1”, and starts the cycle (T) monitoring 610 at the same time. Thereafter, since the failure detection unit does not detect a failure, the SCV is cleared to “0” without exceeding a predetermined failure determination value 611, the LCV continues to hold “1”, and the cycle (T) monitoring is performed. 6
After the start of 10 and the elapse of the T time, 615 is cleared to “0”. Therefore, the fault 601 is not determined as a true fault by both the short-time fault determining unit and the long-time fault determining unit.
As shown in the present embodiment, by using both the short-time fault judging unit and the long-time fault judging unit, a malfunction that occurs fixedly, a fault that occurs intermittently, and a malfunction due to noise or the like can be caused. In this manner, a temporarily occurring failure can be identified and determined, and a fixed or intermittent failure can be notified to a processing system device such as a processor.

(Second Embodiment) In the first embodiment, there is a difference in the component configuration between the short-time fault judging unit and the long-time fault judging unit. In this embodiment, as shown in FIG. Next, a description will be given of a failure determination unit that makes the short-time failure determination unit and the long-time failure determination unit the same in component configuration and that is economical.
The short-time failure determining unit includes a counter 710 and a comparing unit 71.
2. Reset signal sending unit 714 and cycle monitoring unit 71
6, a counter 711, a comparing unit 713, a reset signal transmitting unit 715, and a period monitoring unit 717 are provided in the long-term failure determining unit, similarly to the short-time failure determining unit. The counter 710 is connected to the comparing unit 712 and the reset signal sending unit 714, and the reset signal sending unit 714
Is connected to the cycle monitor 716, and the counter 711 is
Connected to the comparing unit 713 and the reset signal sending unit 715,
The reset signal sending unit 715 is connected to the cycle monitoring unit 717. In the short-time failure determination unit, the counter 710 receiving the failure detection signal calculates SCV = SCV + 1 for the counter value (SCV), and notifies the comparison unit 712 of the calculated SCV. The comparing unit 712 compares the SCV with a predetermined value (TVS) for failure determination, and if the comparison result is (TVS ≦ SCV), the failure notification signal is processed by a processing system device such as a processor (not shown). And if the result of the comparison is (TVS> SCV), the reception of a new SCV is waited. If the SCV is newly notified, the above comparison is performed. The cycle monitoring unit 716 determines the cycle (ST: Short T
ime) and reset signal sending unit 7 every time ST elapses.
14 is instructed to send a reset signal, and when the reset signal sending unit 714 receives the instruction, the SCV
Is cleared to "0". In the long-term failure determination unit, the counter 711 that has received the failure detection signal calculates LCV = LCV + 1 for the counter value (LCV), and notifies the comparison unit 713 of the calculated LCV. Comparison section 713
Is a predetermined value (TVL) for failure determination and LC
V. If the comparison result is (TVL ≦ LCV), a failure notification signal is notified to a processing system device (not shown) such as a processor, and if the comparison result is (TVL> LCV), a new When the reception of the LCV is awaited and the LCV is newly notified, the comparison is performed. Period monitor 717
Monitors the period (LT: Long Time), and instructs the reset signal sending unit 715 to send a reset signal every time LT elapses. When the reset signal sending unit 715 receives the instruction, the LCV Is cleared to “0”. That is, the TV set in the short-time failure determination unit and the long-time failure determination unit
By changing the values of S, TVL, ST, and LT, it is possible to make both determination units have the same component configuration.

(Third Embodiment) FIG. 8 shows a failure mode (a few bit error or the like occurring at the time of data transfer, etc.) when it is not possible to determine a true failure only by the failure determination method shown in the first embodiment. FIG. 6 is a block diagram of a new special failure determination unit for coping with ()). The failure determination unit in the electronic circuit device includes a special short-time measurement counter 901, a special long-time measurement counter 902, a reset signal sending unit 903, and a cycle (UT: Uni).
que Time) monitoring section 904 and special comparing section 905 are provided. The special comparison unit 905 includes a special short-time measurement counter 901, a special long-time measurement counter 902, a reset signal transmission unit 903, and a period (UT: Unique Time) monitoring unit 9.
04, and a processing system device 906 such as a processor, and a reset signal sending unit 903 is connected to a special short-time measurement counter 901 and a special long-time measurement counter 902. The special short-time measurement counter 901 is a counter used for short-time measurement. When the short-time measurement counter receives a failure detection signal and receives a count-up, the special short-time measurement counter 901 is used.
The counter value held by 1 (USCV: Unique Short cycle Co
USCV = USCV + 1, and the calculated USCV is compared with the special comparison unit 905 at the same time.
Has the function of notifying the user. The special short-time measurement counter 901 has a function of clearing the held counter value to “0” by receiving a reset signal from the reset signal sending unit 903. The special long-time measurement counter 902 is a counter used for long-time measurement. When the long-time measurement counter receives a failure detection signal and receives a count-up, the special long-time measurement counter 902 is used. Has the function of calculating ULCV = ULCV + 1 with respect to the counter value (ULCV: Unique Long cycle Counter Value) held therein, and at the same time, notifying the special comparison unit 905 of the calculated ULCV. Also, a special long-time measurement counter 902
Has a function of clearing the held counter value to “0” by receiving a reset signal from the reset signal sending unit 903. The reset signal sending unit 903 has a function of sending a reset signal to the special short-time measurement counter 901 and the special long-time measurement counter 902 when receiving a reset signal sending instruction from the special comparing unit 905. Things. The cycle (UT: Unique Time) monitoring unit 904 has a function of instructing the special comparison unit 905 that the UT cycle has elapsed each time the UT has elapsed. When the special comparison unit 905 receives the USCV from the special short-time measurement counter 901 or receives the ULCV from the special long-time measurement counter 902, the function f
(USCV, ULCV, TVS) is calculated. Function f
(USCV, ULCV, TVS)

(Equation 1) And the calculated function f (USCV, ULCV, TV
If U) is positive, the fault measured by both counters is determined to be a true fault, and the occurrence of the fault is notified to a processing system device 906 such as a processor. Alternatively, when ULCV is received, the function f
(USCV, ULCV, TVU) is calculated. When a notification that the UT cycle has elapsed is received from the cycle (UT: Unique Time) monitoring unit 904, the reset signal sending unit 903 is instructed to send a reset signal.

FIG. 9 shows a case where both the short-time fault judging unit and the long-time fault judging unit shown in the first embodiment are provided with a special comparing unit even if the fault cannot be judged as a true fault. FIG. 4 is a conceptual diagram in a case where it can be determined that a failure occurs. If the failure detection unit detects the failure twice in succession several times, the counter value 1002 of the short-time measurement counter adds “1”, further adds “1”, and continuously Since a failure is detected only twice, a predetermined value (T
VS) is repeatedly cleared to "0" without exceeding 1004. On the other hand, the counter value 1001 of the long-time measurement counter counts up within the range of the long-time period (T), and is set to a predetermined value (TV).
L) Since the period (T) elapses without exceeding 1003, it is repeatedly cleared to “0”. Further, the special comparison unit weights the counter value for nSCV + mLCV (n, m is the counter value for the short period and the long period) every time the counter value 1001 or 1002 counts up within the range of the period (UT). Integer to get
Since “nSCV + mLCV” 1005 exceeds a predetermined value (TVU) 1006, a fault detected within the period (UT) is determined as a true fault, and the occurrence of the fault is determined by a processor or the like. To the processing system device. As shown in the present embodiment, a failure in a mode in which a failure detected by both the short-time failure determination unit and the long-time failure determination unit cannot be determined to be a true failure, that is, a large number of data failures, etc. It is possible to identify and determine even a failure mode in which an error of about a bit occurs, and to notify a processing system device such as a processor that the failure has occurred.

(Fourth Embodiment) FIG. 10 is a diagram showing a specified value (TV) used in the first to third embodiments during operation of the electronic circuit device.
S, TVL, and TVU). In the electronic circuit device, the short-time failure determination unit includes:
A short-time comparison section 803 is provided, a long-time failure determination section is provided with a long-time comparison section 804, and a special failure determination section is provided with a special comparison section 805. Short-time comparison unit 803, long-time comparison unit 804, special comparison unit 805
Is connected to a processing system device 802 such as a processor, and the processing system device 802 such as a processor is connected to a workstation 801. 801 such as a workstation
It has a function of issuing a command for changing the TVS, TVL, or TVU to the processing system device 802 such as a processor by a key operation by a maintenance person or a user. Processing system device 802 such as a processor
Means TVS, TV from the workstation etc. 801
When a command for changing L or TVU is received, whether the command is issued to the short-time comparison unit 803, the long-time comparison unit 804, or a special comparison A determination is made as to whether the signal has been issued to the unit 805, and a specified value setting signal for setting a corresponding value (TVS, TVL, or TVU) to a corresponding comparison unit (any of 803 to 805). TV using
It has a function of issuing S, TVL, or TVU. The short-time comparison unit 803 has a function of receiving the issued TVS using a specified value setting signal from a processing system device 802 such as a processor, and setting the received TVS in a register in the short-time comparison unit 803. is there. The long-time comparison unit 804 has a function of receiving the issued TVL using a specified value setting signal from a processing system device 802 such as a processor, and setting the received TVL in a register in the long-time comparison unit 804. is there. The special comparison unit 805 has a function of receiving the issued TVU using a specified value setting signal from a processing system device 802 such as a processor, and setting the received TVU in a register in the special comparison unit 805. During operation of the electronic circuit device, TVS, TV
When the L or TVU needs to be changed, the maintenance person or the user issues a command for changing the workstation or the like 801, and the processing system device 802 such as a processor that receives the command issues the command. Is performed, and the processing result is reset in a register in the comparison unit (any of 803 to 805) to which the command is applied. Therefore, the maintenance person or the user can set the specified value (T
When the necessity of changing VS, TVL, and TVU is recognized, a new specified value (TVS, TVL, TVU) can be reset in the comparison unit by operating a key on a workstation or the like.

(Fifth Embodiment) In the fourth embodiment, a maintenance person or a user sets a specified value (TVS, TVL, TV).
Recognizing the necessity of changing U), the case where the maintenance person or the user changes the specified value has been described. In the present embodiment, a processing system device such as a processor determines a specified value (TVS,
The case where the necessity of changing the TVL, TVU) is recognized, and the processing system device changes the specified value will be described. Based on values obtained by parameterizing the failure rate, use environment, and operation time for the electronic circuit device, a processing system device such as a processor calculates optimal failure determination specified values (TVS, TVL, TVU) and sets specified values. Using the signal, a new specified value is reset in the corresponding comparison unit. Therefore, while the electronic circuit device is in operation, the optimum specified value can be programmably reset to the state of the electronic circuit device by the processing system device such as the processor.

[0020]

As described above, according to the present invention,
Just by providing a long-term failure determination unit with a simple configuration, it is possible to perform appropriate failure determination for failures where bit errors etc. occur intermittently in electronic circuits as well as failures that occur fixedly. It is possible to notify the failure information to a processing system device such as a processor. In addition, a failure in which the failure determination unit cannot determine a failure detected by the failure detection unit as a true failure (a several-bit error that occurs during data transfer or the like).
Even when a failure occurs, by correlating the counter values of the short-time measurement counter and the long-time measurement counter in the failure determination unit, it is possible to notify a processing system device such as a processor that the failure has occurred. It is possible. Furthermore, when it becomes necessary to change the specified value of the failure determination during operation of the electronic circuit device, the specified value can be programmably changed and reset.

[Brief description of the drawings]

FIG. 1 is a block diagram of a failure detection unit and a failure determination unit in an electronic circuit device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a failure determination unit provided in a device constituted by a conventional electronic circuit.

FIG. 3 is a conceptual diagram showing a conventional method for counting up the number of failure occurrences when a failure occurs.

FIG. 4 is a conceptual diagram illustrating a case where a failure in which a bit error or the like occurs intermittently is detected and a long-time failure determination unit determines that the failure is a true failure in the first embodiment of the present invention. .

FIG. 5 is a conceptual diagram illustrating a case where a fixed failure has been detected and a short-time failure determination unit determines that the failure is a true failure in the first embodiment of the present invention.

FIG. 6 is a block diagram of the first embodiment of the present invention, in which a fault temporarily generated due to a malfunction due to noise or the like is detected, and both the short-time fault determining unit and the long-time fault determining unit detect the fault; Is a conceptual diagram in a case where it cannot be determined that a true failure has occurred.

FIG. 7 is a block diagram of the second embodiment of the present invention in which the short-time fault determining unit and the long-time fault determining unit have the same component arrangement.

FIG. 8 is a block diagram of a special failure determination unit that determines a failure that cannot be determined as a true failure when a failure detected by both the short-time failure determination unit and the long-time failure determination unit according to the third embodiment of the present invention; It is.

FIG. 9 is a conceptual diagram illustrating a case where a special comparison unit determines that a failure that cannot be determined as a true failure by both the short-time failure determination unit and the long-time failure determination unit according to the third embodiment of the present invention is a true failure; FIG.

FIG. 10 is a block diagram in a case where specified values (TVS, TVL, TVU) for failure determination are changed in a fourth embodiment of the present invention.

[Explanation of symbols]

301 to 30n: failure detection unit, 310: short-time measurement counter, 311: long-time measurement counter, 312: short-time comparison unit, 313: long-time comparison unit, 314, 31
5: reset signal sending unit, 316: cycle (T) monitoring unit,
317: start unit, 318: clock unit, 319: cycle determination circuit unit, 320: processing system device such as a processor.

Continuation of the front page (56) References JP-A-7-141265 (JP, A) JP-A-1-217765 (JP, A) JP-A-6-59920 (JP, A) JP-A-3-48339 (JP) , A) JP-A-4-367944 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/28-11/36

Claims (1)

(57) [Claims] An electronic circuit is provided in a device constituted by an electronic circuit. The electronic circuit includes a fixed failure that occurs fixedly in the electronic circuit, an intermittent failure in which a bit error or the like occurs intermittently, and a malfunction caused by noise or the like. a temporary identification and judging trouble determining circuit transient fault occurring, a failure detecting means for detecting the failure, and a failure determination means for determining the contents of the detected fault, the fault determining means A fault detecting unit for short-term determining the fixed fault, and a fault determining unit for long-term determining the intermittent fault, wherein each of the determining units has a fault detection signal notified from the fault detecting means. A counter for counting the count of the counter, a comparing section for comparing the value counted by the counter with a preset specified value, a reset signal sending section for sending a reset signal for clearing the count value of the counter, A cycle monitoring unit that monitors the counting cycle of the data, and when the value counted by each counter exceeds a preset specified value, only the fixed fault and the intermittent fault are determined to be true faults, and the fault information is determined. A failure determination circuit for notifying a processing device including a processor , wherein the failure determination unit further includes a special failure determination unit , and the special failure determination unit includes a counter of the short-time failure determination unit.
Special short-time meter that receives and counts signals from
Measurement counter and the counter of the long-term failure determination unit.
Special long-time measurement counter that receives and counts counting signals
And the special short time measurement counter and the special long time measurement
Calculates the correlation value of the values counted by the
Special comparison unit that compares the calculated correlation value with a preset specified value
And the special short-time measurement counter and the special long-time measurement
A reset signal to clear the count value of the application counter
Monitor the reset signal sending unit and special failure judgment cycle
A period monitoring unit, wherein the calculated correlation value exceeds a prescribed value set in advance.
The short-time failure determination unit and the long-time failure determination
That occur during data transfer that cannot be determined to be a true failure
A special fault including a bit error is determined to be a true fault, and the
Notifying the processing unit including the processor of the failure information
Characteristic failure judgment circuit.