JP3167842B2 - Network resistor and manufacturing method thereof - Google Patents
Network resistor and manufacturing method thereofInfo
- Publication number
- JP3167842B2 JP3167842B2 JP24754893A JP24754893A JP3167842B2 JP 3167842 B2 JP3167842 B2 JP 3167842B2 JP 24754893 A JP24754893 A JP 24754893A JP 24754893 A JP24754893 A JP 24754893A JP 3167842 B2 JP3167842 B2 JP 3167842B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- metal thin
- hole
- primary
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims description 38
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 239000010409 thin film Substances 0.000 claims description 25
- 238000007639 printing Methods 0.000 claims description 11
- 238000007747 plating Methods 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 230000000873 masking effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 238000001883 metal evaporation Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 20
- 238000004544 sputter deposition Methods 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000005388 borosilicate glass Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Non-Adjustable Resistors (AREA)
- Details Of Resistors (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】この発明は、絶縁基板上に複数の
抵抗体を設けてネットワークを形成しその電極を回路基
板表面に表面実装する表面実装型のネットワーク抵抗器
とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface-mount type network resistor in which a plurality of resistors are provided on an insulating substrate to form a network and its electrodes are surface-mounted on the surface of a circuit board, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来の表面実装型のチップネットワーク
抵抗器は、例えば実開平４−２８４０１号公報に開示さ
れているように、薄い平板状の基板の表面に、複数の抵
抗体層を形成し、その基板の端縁部に電極を形成し、こ
の電極を電子機器の回路基板表面にハンダ付けするよう
に設けられている。2. Description of the Related Art A conventional surface mount type chip network resistor has a structure in which a plurality of resistor layers are formed on the surface of a thin flat substrate as disclosed in, for example, Japanese Utility Model Laid-Open No. 4-28401. An electrode is formed on the edge of the substrate, and the electrode is provided so as to be soldered to the surface of the circuit board of the electronic device.
【０００３】この従来のネットワーク抵抗器の製造方法
は、図６、図７に示すように、スルーホール１が形成さ
れたアルミナ基板を用い、このスルーホール１を横切る
ように分割溝２が設けられた多数個取りの大型基板３
に、先ず上記スルーホール１の周囲及び内部に、銀又は
銀−パラジウム等の導電ペーストを印刷して電極４を形
成する。印刷は、スクリーン印刷により行うものである
が、スルーホール１内に導電ペーストを流し込むために
粘性を１０〜３０％落とした導電性ペーストを用いてい
る。さらに、印刷時に、基板３の裏面側から吸引をかけ
て導体ペーストが確実にスルーホール１内に塗布される
ようにしている。この後、導電ペーストを予備乾燥し、
焼成炉に入れて電極４を焼結させる。そして、電極形成
後、大型基板３を分割溝２に沿って割り、個々のネット
ワーク抵抗器を形成するものである。In this conventional method for manufacturing a network resistor, as shown in FIGS. 6 and 7, an alumina substrate having a through-hole 1 is used, and a dividing groove 2 is provided so as to cross the through-hole 1. Large multi-piece substrate 3
First, a conductive paste such as silver or silver-palladium is printed around and inside the through hole 1 to form the electrode 4. The printing is performed by screen printing. In order to pour the conductive paste into the through hole 1, a conductive paste whose viscosity is reduced by 10 to 30% is used. Further, at the time of printing, suction is performed from the back surface side of the substrate 3 so that the conductive paste is surely applied to the through holes 1. After this, the conductive paste is pre-dried,
The electrode 4 is sintered in a firing furnace. After the electrodes are formed, the large-sized substrate 3 is divided along the dividing grooves 2 to form individual network resistors.
【０００４】[0004]
【発明が解決しようとする課題】上記従来の技術の場
合、図６に示すように、導電ペーストをスルーホール１
の周囲に印刷した際に、電極４の導電ペーストが、分割
溝２内に浸入し、隣接する電極４との間を導通させてし
まうことがあった。また、大型基板３を分割するのは、
電極４の焼成後であり、その分割部分で電極４に欠けや
クラック又は割れが生じるという問題もあった。さら
に、印刷によりスルーホール１内に形成される電極の膜
厚は、均一なものにならず、ばらつきが大きく、ハンダ
の乗りや強度もばらつきが多くなるという問題もあっ
た。In the case of the above-mentioned conventional technique, as shown in FIG.
In some cases, the conductive paste of the electrode 4 penetrates into the dividing groove 2 and conducts with the adjacent electrode 4 when printed around the area. The large substrate 3 is divided into
There is also a problem that the electrode 4 is chipped, cracked or cracked at the divided portion after firing of the electrode 4. Further, the thickness of the electrode formed in the through-hole 1 by printing is not uniform, and there is a problem that the variation is large, and the variation in the riding and strength of the solder increases.
【０００５】この発明は、上記従来の技術に鑑みて成さ
れたもので、簡単な構成で電極間の短絡が生ぜず、製造
が容易で歩留が良く、信頼性も高いネットワーク抵抗器
とその製造方法を提供することを目的とする。The present invention has been made in view of the above-mentioned prior art, and has a simple structure, does not cause a short circuit between electrodes, is easy to manufacture, has a good yield, and has a high reliability. It is intended to provide a manufacturing method.
【０００６】[0006]
【課題を解決するための手段】この発明は、スルーホー
ルを横切るように大型基板を分割して形成され端面に上
記スルーホールによる複数の凹部を有した基板と、この
スルーホールによる凹部の内壁面からわずかに離間して
上記基板表面に印刷形成された複数の一次電極と、この
一次電極間に形成された抵抗体と、上記基板端面で隣接
する上記複数の凹部間の上記基板端面には形成されない
ようにして上記各一次電極から上記凹部にかけて金属蒸
着により形成された金属薄膜電極層と、その金属薄膜電
極層及び上記一次電極の表面に形成されたメッキ層が設
けられているネットワーク抵抗器である。SUMMARY OF THE INVENTION The present invention relates to a substrate formed by dividing a large-sized substrate so as to cross a through-hole and having a plurality of recesses formed by the through-holes on an end face, and an inner wall surface of the recess formed by the through-holes. a plurality of primary electrodes formed by printing on the substrate surface is slightly spaced from, the
Adjacent to the resistor formed between the primary electrodes at the end face of the substrate
Is not formed on the end face of the substrate between the plurality of recesses.
Thus, a metal thin film electrode layer formed by metal vapor deposition from each of the primary electrodes to the recesses, and a plating layer formed on the surface of the metal thin film electrode layer and the primary electrode are provided.
Is a network resistor being eclipsed.
【０００７】またこの発明は、所定の分割溝に沿って複
数のスルーホールが形成された大型基板に、上記分割溝
を避けて上記スルーホールに沿って上記分割溝に接しな
いように上記大型基板表面に一次電極を印刷形成し、こ
の一次電極間に抵抗体を形成し、少なくとも上記スルー
ホールと上記一次電極の一部が露出するとともに上記ス
ルーホール間を遮蔽するようにマスキングして上記スル
ーホール内壁面から上記一次電極にかけて金属蒸着によ
り金属薄膜電極層を形成し、この後上記分割溝に沿って
上記大型基板を個々の基板に分割し、上記一次電極の露
出部分及び金属薄膜電極層にメッキ層を形成するネット
ワーク抵抗器の製造方法である。また、上記マスキング
は、上記スルーホール間を除く上記スルーホール周縁部
を露出させた剥離樹脂を印刷し、この後上記金属薄膜電
極層を形成するものである。Further, according to the present invention, a large-sized substrate having a plurality of through holes formed along a predetermined dividing groove is provided so as to avoid the dividing groove and not to contact the dividing groove along the through hole. primary electrode formed by printing on the surface, this
A resistor is formed between the primary electrodes, and at least a part of the through hole and the primary electrode are exposed and masked so as to shield between the through holes, and metal deposition is performed from the inner wall surface of the through hole to the primary electrode. Forming a metal thin-film electrode layer, and thereafter dividing the large-sized substrate into individual substrates along the division grooves, and forming a plating layer on the exposed portion of the primary electrode and the metal thin-film electrode layer. Is the way. The masking is to print a release resin exposing the periphery of the through-hole except for between the through-holes, and thereafter form the metal thin-film electrode layer.
【０００８】[0008]
【作用】この発明のネットワーク抵抗器とその製造方法
は、大型基板のスルーホールに真空蒸着やスパッタリン
グによって金属薄膜電極層を形成し、電極間の短絡がな
く、電極構造自体にも欠陥がないようにしたものであ
る。According to the network resistor and the method of manufacturing the same of the present invention, a metal thin film electrode layer is formed in a through hole of a large-sized substrate by vacuum evaporation or sputtering, so that there is no short circuit between the electrodes and there is no defect in the electrode structure itself. It was made.
【０００９】[0009]
【実施例】以下この発明の実施例について図面に基づい
て説明する。図１〜図４はこの発明の第一実施例を示す
もので、この実施例のネットワーク抵抗器１０は、セラ
ミックス等の絶縁基板１２の表面に銀−パラジウム等の
導電ペーストを印刷して一次電極１４を形成し、この一
次電極１４間に跨がるように酸化ルテニウム等の抵抗体
１６が印刷形成されている。抵抗体１６の表面には、ホ
ウケイ酸鉛ガラスによるガラスコート１８が形成され、
さらに、抵抗体１６のレーザトリミングの後にホウケイ
酸鉛ガラスによるガラスコート又はエポキシ系樹脂のレ
ジンコートからなるオーバーコート１９が形成されてい
る。オーバーコート１９の表面には、抵抗体１６の抵抗
値等を表示する所定の文字２０が、ホウケイ酸鉛ガラス
又はエポキシ系樹脂等による塗料で印刷形成されてい
る。Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1 to 4 show a first embodiment of the present invention. A network resistor 10 of this embodiment has a primary electrode formed by printing a conductive paste such as silver-palladium on the surface of an insulating substrate 12 such as a ceramic. A resistor 16 such as ruthenium oxide is formed by printing so as to extend between the primary electrodes 14. A glass coat 18 of lead borosilicate glass is formed on the surface of the resistor 16,
Furthermore, after laser trimming of the resistor 16, an overcoat 19 made of a glass coat of lead borosilicate glass or a resin coat of an epoxy resin is formed. On the surface of the overcoat 19, predetermined characters 20 indicating the resistance value and the like of the resistor 16 are formed by printing with paint such as lead borosilicate glass or epoxy resin.
【００１０】基板１２の側面には、スルーホールを分割
して形成された凹部２２が設けられ、この凹部２２に、
真空蒸着又はスパッタリング等の金属蒸着により、ニッ
ケル・クロム及び銅の金属薄膜電極層２４が形成されて
いる。そして、この金属薄膜電極層２４の外表面に、さ
らに保護層としてのニッケルメッキ２６と、その外側
に、ハンダ付けを確実にするためのハンダメッキ２８が
施されている。On the side surface of the substrate 12, a concave portion 22 formed by dividing a through hole is provided.
The metal thin film electrode layer 24 of nickel, chromium, and copper is formed by metal evaporation such as vacuum evaporation or sputtering. The outer surface of the metal thin film electrode layer 24 is further provided with a nickel plating 26 as a protective layer, and on the outside thereof, a solder plating 28 for ensuring soldering.
【００１１】次にこの実施例のネットワーク抵抗器の製
造方法について説明する。この実施例のネットワーク抵
抗器１０は、先ず、所定間隔でスルーホール３０が縦横
に形成され、このスルーホール３０を横切るように分割
溝３２が形成された平板状のセラミックス基板等の大型
基板３４を用い、その表面に、スルーホール３０を囲む
様に縦横に一次電極１４を印刷形成し、焼成する。この
一次電極は、分割溝３２にかからないように印刷され
る。この後、抵抗体１６を互いに対向する一対の一次電
極１４間にまたがるように印刷形成し、焼成する。そし
て、ガラスコート１８の印刷および焼成を行なう。この
後、抵抗体１６をレーザトリミングし、所定の抵抗値に
設定し、オーバーコート１９を印刷し、焼成し、文字２
０の印刷焼成を行う。Next, a method of manufacturing the network resistor according to this embodiment will be described. In the network resistor 10 of this embodiment, first, a large-sized substrate 34 such as a plate-like ceramic substrate in which through holes 30 are formed vertically and horizontally at predetermined intervals and divided grooves 32 are formed to cross the through holes 30 is formed. The primary electrodes 14 are printed and formed on the surface so as to surround the through holes 30 vertically and horizontally and fired. This primary electrode is printed so as not to cover the dividing groove 32. After that, the resistor 16 is formed by printing so as to extend between the pair of primary electrodes 14 facing each other, and is baked. Then, printing and baking of the glass coat 18 are performed. Thereafter, the resistor 16 is laser-trimmed, set to a predetermined resistance value, an overcoat 19 is printed, baked, and
The print baking of 0 is performed.
【００１２】次に、上記大型基板３４に、図４に示すよ
うなマスク３６を装着し、スルーホール３０及びその周
囲の一次電極１４の一部が露出するようにして、スパッ
タリングを行う。スパッタリングによりスルーホール３
０内には、ニッケル・クロム及び銅の金属薄膜電極層２
４が形成される。この後カッター等を用いて大型基板３
４を、分割溝３２に沿って個々の基板１２毎に分割す
る。Next, a mask 36 as shown in FIG. 4 is mounted on the large substrate 34, and sputtering is performed so that the through hole 30 and a part of the primary electrode 14 around the through hole 30 are exposed. Through hole 3 by sputtering
0, a nickel-chromium and copper metal thin-film electrode layer 2
4 are formed. After that, the large substrate 3 is
4 are divided along the division grooves 32 into individual substrates 12.
【００１３】この後、上記一次電極１４及びスルーホー
ル３０による凹部２２の内面の金属薄膜電極２４の表面
に、ニッケルメッキ２６およびハンダメッキ２８を順次
施してこの実施例のネットワーク抵抗器の電極部の形成
が終了する。Thereafter, a nickel plating 26 and a solder plating 28 are sequentially applied to the surface of the metal thin film electrode 24 on the inner surface of the concave portion 22 formed by the primary electrode 14 and the through hole 30 to form an electrode portion of the network resistor of this embodiment. The formation ends.
【００１４】この実施例のネットワーク抵抗器によれ
ば、基板１２の端面に形成された凹部２２に、スパッタ
リング等により金属薄膜電極層２４が形成されているの
で、一次電極１４及び金属薄膜電極層２４が確実に形成
されているとともに、隣り合う電極同士のショートがな
く、製造上の歩留が良く高品質なネットワーク抵抗器を
得ることができる。According to the network resistor of this embodiment, since the metal thin film electrode layer 24 is formed in the recess 22 formed on the end face of the substrate 12 by sputtering or the like, the primary electrode 14 and the metal thin film electrode layer 24 are formed. Are reliably formed, there is no short circuit between adjacent electrodes, and a high-quality network resistor with good manufacturing yield can be obtained.
【００１５】次のこの発明の第二実施例のネットワーク
抵抗器とその製造方法について図５を基にして説明す
る。ここで上述の実施例と同様の部材は同一符号を付し
て説明を省略する。この実施例のネットワーク抵抗器
は、スルーホール３０の内壁面に金属薄膜電極層２４を
形成する際に、所定の箇所のみ露出するように、剥離樹
脂４６をスパッタリングの前に印刷し硬化させる。この
後、マスクを用いず大型基板３４全面にスパッタリング
を行う。スパッタリング後は、水又は有機溶剤によりこ
の剥離樹脂４６を除去し、上記と同様の後の工程に進
む。Next, a network resistor according to a second embodiment of the present invention and a method of manufacturing the same will be described with reference to FIG. Here, the same members as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted. In the network resistor of this embodiment, when forming the metal thin-film electrode layer 24 on the inner wall surface of the through hole 30, the release resin 46 is printed and cured before sputtering so that only a predetermined portion is exposed. Thereafter, sputtering is performed on the entire surface of the large substrate 34 without using a mask. After the sputtering, the release resin 46 is removed with water or an organic solvent, and the process proceeds to a subsequent step similar to the above.
【００１６】この実施例によれば、上記実施例と同様の
効果に加えて、スパッタリング時にマスクからの回り込
みによって無用な箇所に金属薄膜が蒸着することがな
く、確実に基板の所望の箇所にのみ金属薄膜を形成する
ことができるものである。According to this embodiment, in addition to the same effect as in the above embodiment, a metal thin film is not deposited on unnecessary portions due to wraparound from a mask during sputtering, and it is ensured only on a desired portion of a substrate. A metal thin film can be formed.
【００１７】尚、この発明のネットワーク抵抗器とその
製造方法は、スルーホールを利用した電極部分に、蒸着
やスパッタリング等の金属蒸着技術により金属薄膜の電
極層を形成するものであれば良く、蒸着方法や、金属薄
膜の厚さ、スルーホールの径等は任意に設定し得るもの
である。The network resistor and the method of manufacturing the network resistor according to the present invention are not limited as long as an electrode layer of a metal thin film is formed on the electrode portion using a through hole by a metal evaporation technique such as evaporation or sputtering. The method, the thickness of the metal thin film, the diameter of the through hole, and the like can be arbitrarily set.
【００１８】[0018]
【発明の効果】この発明のネットワーク抵抗器は、スル
ーホール部に形成された電極が金属蒸着による金属薄膜
電極層からなり、電極間の短絡が無く、基板分割による
電極の割れ等も生ぜず、高品質な電極構造が得られるも
のである。さらに、金属薄膜電極層にメッキ層を施すこ
とにより、電極部の強度及びハンダ付け性等が向上する
ものである。According to the network resistor of the present invention, the electrodes formed in the through holes are made of a metal thin film electrode layer formed by metal deposition, there is no short circuit between the electrodes, and no cracking of the electrodes due to the division of the substrate occurs. A high-quality electrode structure can be obtained. Further, by applying a plating layer to the metal thin-film electrode layer, the strength and solderability of the electrode portion are improved.
【図１】この発明の第一実施例のネットワーク抵抗器の
斜視図である。FIG. 1 is a perspective view of a network resistor according to a first embodiment of the present invention.
【図２】図１のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】この実施例のネットワーク抵抗器の一製造工程
を示す部分平面図である。FIG. 3 is a partial plan view showing one manufacturing step of the network resistor of this embodiment.
【図４】この実施例のネットワーク抵抗器の一製造工程
を示す部分平面図である。FIG. 4 is a partial plan view showing one manufacturing step of the network resistor of this embodiment.
【図５】この発明の第二実施例のネットワーク抵抗器の
一製造工程における縦断面図である。FIG. 5 is a longitudinal sectional view of one step of manufacturing the network resistor according to the second embodiment of the present invention.
【図６】この発明の従来技術のネットワーク抵抗器の一
製造工程を示す部分平面図である。FIG. 6 is a partial plan view showing one manufacturing step of the conventional network resistor of the present invention.
【図７】この発明の従来技術のネットワーク抵抗器の部
分斜視図である。FIG. 7 is a partial perspective view of a prior art network resistor of the present invention.
１０ ネットワーク抵抗器 １２ 絶縁基板 １４ 一次電極 １６ 抵抗体 ２２ 凹部 ２４ 金属薄膜電極層 ２８ ハンダメッキ DESCRIPTION OF SYMBOLS 10 Network resistor 12 Insulating substrate 14 Primary electrode 16 Resistor 22 Concave part 24 Metal thin film electrode layer 28 Solder plating
フロントページの続き (56)参考文献 実開 平３−59609（ＪＰ，Ｕ) 実開 平１−216502（ＪＰ，Ｕ)Continuation of the front page (56) References JP-A 3-59609 (JP, U) JP-A 1-216502 (JP, U)
Claims (3)
分割して形成され端面に上記スルーホールによる複数の
凹部を有した基板と、このスルーホールによる凹部の内
壁面からわずかに離間して上記基板表面に印刷形成され
た複数の一次電極と、この一次電極間に形成された抵抗
体と、上記基板端面で隣接する上記複数の凹部間の上記
基板端面には形成されないようにして上記各一次電極か
ら上記凹部にかけて金属蒸着により形成された金属薄膜
電極層と、その金属薄膜電極層及び上記一次電極の表面
に形成されたメッキ層が設けられていることを特徴とす
るネットワーク抵抗器。1. A substrate formed by dividing a large-sized substrate so as to cross a through-hole and having a plurality of recesses formed by the through-holes on an end surface, and the substrate being slightly separated from an inner wall surface of the recess formed by the through-holes. Multiple primary electrodes printed on the surface and the resistance formed between the primary electrodes
The body and the plurality of recesses adjacent to each other at the end face of the substrate.
A metal thin film electrode layer formed by metal evaporation from the respective primary electrodes to the recesses so as not to be formed on the end face of the substrate, and a plating layer formed on the surface of the metal thin film electrode layer and the primary electrode are provided. A network resistor.
ルが形成された大型基板に、上記分割溝を避けて上記ス
ルーホールに沿って上記分割溝に接しないように上記大
型基板表面に一次電極を印刷形成し、この一次電極間に
抵抗体を形成し、少なくとも上記スルーホールと上記一
次電極の一部が露出するとともに上記スルーホール間を
遮蔽するようにマスキングして上記スルーホール内壁面
から上記一次電極にかけて金属蒸着により金属薄膜電極
層を形成し、この後上記分割溝に沿って上記大型基板を
個々の基板に分割し、上記一次電極の露出部分及び金属
薄膜電極層にメッキ層を形成することを特徴とするネッ
トワーク抵抗器の製造方法。2. A large-sized substrate having a plurality of through holes formed along a predetermined dividing groove is formed on a surface of the large-sized substrate so as to avoid the dividing groove and not contact the dividing groove along the through hole. Electrodes are printed and formed between the primary electrodes
Forming a resistor , masking so that at least a part of the through hole and the primary electrode is exposed and shields between the through holes, and metal thin film electrode layer by metal deposition from the inner wall surface of the through hole to the primary electrode. Forming the large-sized substrate into individual substrates along the dividing groove, and forming a plating layer on the exposed portion of the primary electrode and the metal thin-film electrode layer. Method.
を除く上記スルーホール周縁部を露出させた剥離樹脂を
印刷し、この後上記金属薄膜電極層を形成することを特
徴とする請求項２記載のネットワーク抵抗器の製造方
法。3. The masking method according to claim 2, wherein the masking is performed by printing a release resin exposing the periphery of the through-hole except for between the through-holes, and thereafter forming the metal thin-film electrode layer. Manufacturing method of network resistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24754893A JP3167842B2 (en) | 1993-09-08 | 1993-09-08 | Network resistor and manufacturing method thereof |
| JP26036498A JP3561635B2 (en) | 1993-09-08 | 1998-09-14 | Network resistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24754893A JP3167842B2 (en) | 1993-09-08 | 1993-09-08 | Network resistor and manufacturing method thereof |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26036498A Division JP3561635B2 (en) | 1993-09-08 | 1998-09-14 | Network resistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0778701A JPH0778701A (en) | 1995-03-20 |
| JP3167842B2 true JP3167842B2 (en) | 2001-05-21 |
Family
ID=17165138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24754893A Expired - Lifetime JP3167842B2 (en) | 1993-09-08 | 1993-09-08 | Network resistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3167842B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10189318A (en) * | 1996-12-27 | 1998-07-21 | Hokuriku Electric Ind Co Ltd | Manufacture of network resistor |
| JP4077854B2 (en) * | 2006-08-29 | 2008-04-23 | 京セラ株式会社 | Electronic components |
| WO2015033645A1 (en) * | 2013-09-06 | 2015-03-12 | 株式会社アスカネット | Method for fabrication of photo-control panel comprising photo-reflector parts which are positioned in parallel |
-
1993
- 1993-09-08 JP JP24754893A patent/JP3167842B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0778701A (en) | 1995-03-20 |
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