JP3164918B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a low power consumption output circuit in a gate array.

[0002]

2. Description of the Related Art A BiCMOS output circuit in which a bipolar transistor and a MOS transistor are mixed on the same substrate in a circuit format of a gate array output circuit has both the high speed of the bipolar transistor and the low power consumption of the MOS transistor. It is widely used as a circuit type.

FIG. 7 shows an example of a BiCMOS type output circuit.
In the conventional BiCMOS output circuit, the input stage has an N-channel MO receiving an input signal through an input terminal 1.
S-type field effect transistor (hereinafter referred to as NMOS) N1
, And the NMOS N1 is connected to a power supply via a pull-up resistor R1. In the output stage, NPN transistors Q1 and Q2 with Schottky barrier diodes are vertically connected in two stages, and the first NPN transistors with Schottky barrier diodes are connected.
The PN transistor Q1 is an open collector type output circuit having a collector connected to the output terminal 3. The collector of the second NPN transistor with a Schottky barrier diode Q2 is connected to a power supply via a resistor R2, and to the ground potential via an emitter resistor R3. An input terminal of a circuit connected to the next stage of the circuit shown in FIG. 7 is connected to a power supply via a resistor R5. Here, the resistance R5 is set to a value of several tens KΩ in order to suppress power consumption.

When a high-level data signal is input to the input terminal 1, the NMOS N1 is conductive, and each of the first NPN transistor Q1 with a Schottky barrier diode and the second NPN transistor Q2 with a Schottky barrier diode is turned on. The output terminal 3 becomes non-conductive, and rises to the power supply potential Vcc by the resistor R5. Input terminal 1
When a low-level data signal is input to the
N1 is non-conductive, NPN transistors Q1 and NP
N-transistor Q2 is rendered conductive, and a low level is output to output terminal 3.

[0005]

SUMMARY OF THE INVENTION The above-mentioned conventional BiC
In the MOS type output circuit, a steady current flows through an open collector type first NPN transistor with a Schottky barrier diode connected to the output terminal and a second NPN transistor with a Schottky barrier diode connected to the preceding stage. . This is to supply the drive current when there is a current load at the output terminal, and to provide the NP with the first and second Schottky barrier diodes.
This is for preventing the first and second NPN transistors with a Schottky barrier diode from falling into collector saturation by making the N transistor conductive, but the first NPN transistor with a Schottky barrier diode Q1 connected to the output terminal is There is a problem that power is consumed other than when performing the switching operation.

[0006]

A semiconductor integrated circuit according to the present invention has a first bipolar transistor having an emitter connected to ground potential and a collector connected to an output terminal, and an emitter connected to the base and the first of the first bipolar transistor. 1
A second bipolar transistor having a base connected to the ground potential via a second resistor, a base connected to a positive potential power supply via a third resistor, and a collector connected to the positive potential power supply via a third resistor; Are connected via a fourth resistor having a smaller resistance value than the third resistor between the collector of the first power supply and the positive power supply.
A first field effect transistor receiving a synchronized signal;
The second is connected between the base and the ground potential of the bipolar transistor, said system and a second field effect transistor that controls the on / off of the receiving input signal to the gate electrode and the second bipolar transistor Black
First bipolar transistor in synchronization with the clock signal
There is a semiconductor integrated circuit for a switching operation, before
A timing in which the first bipolar transistor can be switched by a signal synchronized with the system clock signal.
At the time of timing, the first field effect transistor is turned on, and the control is performed so that the first field effect transistor is turned off at a time other than when the switching is possible.

[0007]

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, which is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention, a semiconductor integrated circuit according to the first embodiment of the present invention has a first Schottky barrier of an open collector type. A second Schottky barrier diode N is provided before the diode-connected NPN transistor Q1.
A resistor R is connected between the collector of the PN transistor Q2 and the power supply.
2 and a resistor R4 are connected in parallel, and a P-channel MOS field effect transistor (hereinafter referred to as a PMOS) PMOS P1 whose conduction is controlled by a signal having the same phase as the system clock signal is provided between the resistor R4 and the power supply. PMOS
The gate terminal of P1 is connected to input terminal 2 and this input
The terminal 2 is provided with a pulse generation circuit including a signal delay circuit having the circuit configuration shown in FIG. In addition, NPN
An N-channel MOS field-effect transistor is provided at a stage preceding the star Q2.
Transistor (hereinafter referred to as NMOS) NMOS N1;
The gate of the NMOS N1 is connected to the input terminal 1.
Further, a resistor is provided between the power supply Vcc and the source of the NMOS N1.
It has an anti-R1 and the end point of the resistor R1 is an NPN transistor Q
2 is connected to the base . The input terminal of a circuit connected to the next stage of the circuit shown in FIG. 1 is connected to a power supply via a resistor R5. Here, the resistance R5 is set to a value of several tens KΩ in order to suppress power consumption. The circuit operation by the above circuit configuration will be described with reference to FIG. 2. When a high-level data signal IN is input to the input terminal 1,
NMOS N1 is conducting, NPN transistor Q1 and
The NPN transistor Q2 is turned off, and the output OUT of the output terminal 3 rises to the power supply voltage Vcc by the resistor R5. When the low-level data signal IN is input to the input terminal 1, the NMOS N1 is turned off and the NPN
The transistor Q1 and the NPN transistor Q2 are turned on, and the output OUT of the output terminal 3 outputs a low level.

Referring to FIGS. 5 and 6, a pulse generation circuit for generating a signal input to terminal 11 supplies a system clock ck to first flip-flop FF1 via first signal delay circuit D1. Input and output signal q1
Is output with a signal delay t1. The system clock ck is supplied to the second flip-flop FF2 through the first signal delay circuit D1 and the second signal delay circuit D2.
And its output q2 is accompanied by a signal delay t2. The output q2 of the second flip-flop FF2 is passed through the NOT element 4 and the output q2 of the first flip-flop FF2 is NOT
The data is input to the data of the first flip-flop through the element 4. The output q1 of the first flip-flop FF1 and the output q2 of the second flip-flop FF2 are exclusive-NO
An output CKOUT of the system clock passing through the R element 5 is generated.

At this time, the sections TD and TW can be designed as follows by the signal delay circuits D1 and D2, respectively.

TD = D1 + D2 TW = (D1 + D2 + t2 + t4)-(D1 + t1 + t
3) = D2 + (t4−t3) Here, since the flip-flops FF1 and FF2 use the same flip-flop arranged close to each other, it can be considered that the signal delays t1 and t2 are equal. According to the above equation, by setting the signal delays d1 and d2 of the signal delay circuits D1 and D2 to appropriate values, the system clock signal C
A signal synchronized with K and subjected to duty conversion can be generated.

With the above-described circuit configuration, the signal delays d1 and d2 of the signal delay circuits D1 and D2 are set such that the PMOS P1 is turned off when the potential of the output signal at the terminal 3 is constant, and the PMOS P1 is turned on when the potential changes. I do. As a result, the current flowing through the second transistor with a Schottky barrier diode Q2 before and after the output signal falls, that is, in the TW section, is determined by the resistors R2 and R4, and after the output signal OUT is stabilized at a low level, ie, After the passage of the section TW, it is determined only by the resistance R2. Therefore, for example, the resistance value of the resistor R2 is changed to the first Schottky barrier diode-added NPN transistor Q.
By setting the resistance value of the resistor R4 to a value sufficiently large (several tens of KΩ) so that 1 does not saturate and setting the resistance value of the resistor R4 sufficiently smaller than the resistance value of the resistor R2 (several KΩ), the operation speed is not impaired. The power consumption, in particular, the steady-state current can be reduced in a time region where the output signal OUT is at a low level.

FIG. 3 shows a semiconductor integrated circuit according to a reference example of the present invention. In this reference example , a second NPN transistor with Schottky barrier diode Q2 is connected in front of the first NPN transistor with Schottky barrier diode Q1 of the open collector type. Second NPN transistor Q2 with Schottky barrier diode
NMOS in series with a resistor R3 connected to the emitter of
N2 is provided. The input terminal of a circuit connected to the next stage is connected to a power supply via a resistor R5. Here, the resistance R5 is set to a value of several tens KΩ in order to suppress power consumption. The circuit operation is the same as that of the first embodiment shown in FIG.
Since the operation is the same as that of the MOSP1, the description is omitted for simplicity only. Therefore, when the output signal is at a constant low level, no current flows through the resistor R3, no output current flows, and power consumption in a time region where the output signal is at a constant low level can be reduced.

[0015]

As described above, according to the present invention, since the steady current can be controlled based on the cycle of the system clock signal, the present invention has the effect of reducing power consumption during system driving.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment shown in FIG.

FIG. 3 is a circuit diagram of a reference example of the present invention.

FIG. 4 is a timing chart for explaining the operation of the reference example shown in FIG. 3;

FIG. 5 is a circuit diagram of a system clock generation circuit according to the first embodiment and a reference example of the present invention.

FIG. 6 is a timing chart illustrating the operation of the system clock generation circuit shown in FIG.

FIG. 7 is a circuit diagram of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1, 2, 11 input terminal 3, 6 output terminal 4 NOT element 5 exclusive NOR element Q1, Q2 NPN with Schottky barrier diode
Transistors N1, N2 N-channel MOS-type FET P1 P-channel MOS-type FET R1, R2, R3, R4, R5 Resistance D1, D2 Signal delay circuit FF1, FF2 flip-flop Δpw Conventional output circuit and output circuit according to the present invention D1 The signal delay of the first signal delay circuit D1 d2 The signal delay of the second signal delay circuit D2 t0 The signal delay of the NOT element t1 The signal delay inside the first flip-flop FF1 t2 The second flip-flop Signal delay inside FF2 t3 Signal delay of exclusive NOR element 5 Vcc power supply

Claims (1)

(57) [Claims] A first bipolar transistor having an emitter connected to ground potential and a collector connected to an output terminal;
An emitter is connected to the ground potential via a base of the first bipolar transistor and a first resistor, and a base is connected to a positive potential power supply via a second resistor and a collector via a third resistor. A second bipolar transistor, connected between the collector of the second bipolar transistor and the positive power supply via a fourth resistor having a resistance smaller than the third resistor , and synchronized with the system clock signal at the gate electrode; A first field-effect transistor receiving a signal, a second field-effect transistor connected between the base of the second bipolar transistor and the ground potential, and receiving an input signal at a gate electrode to control on / off of the second bipolar transistor; said sheet and a second field effect transistor
Synchronized with the stem clock signal, the first bipolar
A semiconductor integrated circuit in which a transistor performs a switching operation , wherein the first bipolar transistor performs switching by a signal synchronized with the system clock signal.
The first field-effect transistor is turned on at a time when the switching is possible.
A semiconductor integrated circuit, wherein the first field-effect transistor is controlled so as to be in a non-conducting state at times other than the first period.