JP3162190B2 - Active matrix type liquid crystal display device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal display device and a driving method thereof, and more particularly to an active matrix liquid crystal display device which suppresses generation of smear and improves display quality of the active matrix liquid crystal display device. Liquid crystal display device and a driving method thereof.

[0002]

2. Description of the Related Art In general, an active matrix type liquid crystal display device has been recently developed to be portable because of its light weight and low power consumption characteristics as well as a relatively compact display device. It has been used for display units of various electronic devices including electronic devices.

FIG. 8 is a block diagram showing an example of a circuit configuration of such a known active matrix type liquid crystal display device.

In FIG. 8, reference numeral 50 denotes a matrix substrate;
1 is a scanning line, 52 is a signal line, 53 is a thin film transistor (TFT), 54 is a liquid crystal cell, 55 is a scanning drive circuit, 56 is a signal drive circuit, 57 is a polarity inversion circuit,
8 is a signal input terminal to which the image signal Data is input, 59
Is a synchronization signal input terminal to which the horizontal synchronization signal Hsync is input, and 60 is a synchronization signal input terminal to which the vertical synchronization signal Vsync is input.

The matrix substrate 50 has a large number of parallel scanning lines 51, a large number of parallel signal lines 52 orthogonal to each scanning line 51, and an intersection of each of the scanning lines 51 and each of the signal lines 52. And a circuit portion including the TFT 53 and the liquid crystal cell 54 forms one pixel. Each scanning line 5
1, a scanning drive circuit 55 is connected to each signal line 52, and a signal drive circuit 56 is connected to each signal line 52. The input of the scan drive circuit 55 is connected to a horizontal signal input terminal 59. The signal side drive circuit 56 has one input connected to the display signal input terminal 58 and the other input connected to the polarity inversion circuit 5.
7 are connected to the vertical signal input terminals 50, respectively.

FIG. 9 is a partial configuration diagram showing one pixel portion in the known active matrix type liquid crystal display device shown in FIG. 8, and FIG. 10 drives the one pixel portion shown in FIG. FIG. 4 is a signal waveform diagram showing a supply timing of a drive signal.

In FIG. 9, reference numeral 61 denotes a stray capacitance between the drain and the source of the TFT 83, and other components that are the same as those shown in FIG.

The TFT 53 has its gate connected to the scanning line 51, its drain connected to the signal line 52, its source connected to the liquid crystal cell 54, and the liquid crystal cell 5.
The other end of 4 is grounded.

Further, in FIG. 10, Data image signal, V _G is the scan signal (gate-on voltage) of the positive polarity supplied to the scan line 51 to be supplied to the signal side driving circuit 56 of FIG. 4, Vd is a signal line 52 is a display signal (drain voltage) supplied to 52. Note that, from time t ₀ to time t ₁
, A second period from time t ₁ to time t _2, and a third period from time t ₂ to time t ₃ are selection periods (1H) of one scan line, respectively. For each selection time (1H) of each scanning line, the image signal Data,
Gate-on voltage V _G, the drain voltage Vd is configured to both be updated.

Here, the operation of the known active matrix type liquid crystal display device shown in FIG. 9 will be described with reference to FIG.

First, the second liquid crystal cell 54 is selected.
During the period, the horizontal synchronizing signal Hsy
When a positive polarity of the gate-on voltage V _G synchronized with nc is supplied to the scan line 51, TFT 53 of the gate-on voltage V _G is applied to the gate it is turned on. At the same time, during the second period, a negative drain voltage Vd is supplied to the drain of the TFT 53 from the signal side driving circuit 56 via the signal line 52, and the negative drain voltage Vd is supplied to the liquid crystal cell through the TFT 53. 54 is applied. Then, the second time period has elapsed, when the voltage state between both electrodes of the liquid crystal cell 54 is sufficiently stable, the application of the gate-on voltage V _G is stopped, with it TFT5
3 is turned off, the electrode on the TFT 53 side of the liquid crystal cell 54 is electrically isolated, and the negative drain voltage V
A voltage corresponding to the magnitude of d is written into the liquid crystal cell 54. The voltage written in the liquid crystal cell 54 is
The liquid crystal cell 54 is accumulated and held in a capacitance existing between the two electrodes, and is maintained between the two electrodes until the liquid crystal cell 54 is selected again, so that a liquid crystal display with stable luminance can be performed in the liquid crystal cell 54. Done.

In the third period following the second period, a scanning line (not shown) next to the scanning line 51 is provided.
In the above, the same operation as the above-described operation performed in the liquid crystal cell 54 is performed, and further, in a next period following the third period, a scan line (not shown) two scan lines ahead of the scan line 51 is provided. The operation similar to the operation performed in liquid crystal cell 54 described above is performed.
The operation performed in the above-described liquid crystal cell 54 is performed in all the liquid crystal cells. As a result, a required liquid crystal display image that changes every moment can be formed on the entire screen of the matrix substrate 50 shown in FIG. .

In this case, each time one frame elapses,
Since the polarity of the drain voltage Vd applied to each signal line 52 is inverted in the polarity inversion circuit 57 in synchronization with the vertical synchronization signal Vsync, or the polarity is not inverted, each of the liquid crystal cells 54 The DC component is not accumulated and superimposed, the deterioration of the liquid crystal material in the liquid crystal cell 54 is prevented, and a high quality display can always be realized.

Further, this TFT-driven active matrix type liquid crystal display device has an advantage that it is not necessary to consider the duty ratio much even when the number of pixels, that is, the display capacity is increased. If a color filter is provided for each pixel and the applied voltage is controlled, halftone display is possible, so that it can be applied to a wide range of applications such as a high definition full color display device. It is possible.

[0015]

The above-mentioned active matrix type liquid crystal display device has the above-mentioned various advantages, but also has a problem that smear as described below occurs.

FIG. 11 is an operation explanatory diagram showing a voltage state stored and held between the two electrodes of the liquid crystal cell, which is shown with the time considerably shortened as compared with FIG.

In FIG. 11, VS1 indicates a voltage state between both electrodes of the liquid crystal cell 54 in which smear is reduced, and VS2 indicates a voltage state between both electrodes of the liquid crystal cell 54 in which smear is not significantly reduced.

Here, each time the liquid crystal cell 54 is selected, that is, each time the TFT 53 is turned on, the drain voltage Vd at that time is applied, and then it is selected again. Up to this point, the voltage corresponding to the magnitude of the drain voltage Vd is accumulated and held as described above. However, in the actual case, since the floating capacitance 61 exists between the drain and the source of the TFT 53, Cell 5
The fourth electrode on the TFT 53 side is not completely insulated when the TFT 53 is turned off. That is, T
Even when the FT 53 is off, each drain voltage Vd applied to the signal line 52 is divided by the floating capacitance 61 and the capacitance existing between both electrodes of the liquid crystal cell 54, and the divided voltage of each drain voltage Vd is divided. Is superimposed as a voltage fluctuation ΔVs on the storage and holding voltage between the two electrodes of the liquid crystal cell 54, so that the storage and holding voltage always fluctuates in a small width as shown in the voltage state VS2 of FIG.

In this case, the normal driving method (frame) in which the polarity of the drain voltage Vd is the same throughout one frame.
In the inversion driving method), when displaying white where the drain voltage Vd is relatively small, the voltage fluctuation ΔVs in the vertical line direction of the screen becomes small, and the drain voltage Vd
When the black color becomes relatively large, the voltage fluctuation ΔVs in the vertical line direction of the screen increases, so that the voltage fluctuation ΔVs changes depending on the density state of the display image. For this reason, the frame inversion driving method has a problem that brightness unevenness called smear occurs in the vertical direction of the screen depending on the type of display image, and this deteriorates display quality.

In order to eliminate such a problem, it is already known that a driving method (line inversion driving method) in which the polarity of the drain voltage Vd is inverted every selection time (1H) of one scanning line is effective. I'm going. That is, in this line inversion driving method, the polarity of the drain voltage Vd is inverted every selection time (1H) of one scanning line, and a voltage having a different polarity for each scanning line is applied to the liquid crystal cell 54 constituting each pixel. According to this line inversion driving method, the liquid crystal cell 5 is connected via the stray capacitance 61.
Voltage variation ΔV superimposed on the accumulation holding voltage between both electrodes of No. 4
Since the polarity of s is inverted every scanning line, as shown in the voltage state VS1 of FIG.
The ratio of the voltage fluctuation ΔVs in the frame is smaller than that in the frame inversion driving method, and the smear in the vertical direction of the screen is reduced.
Deterioration of display quality is also reduced.

However, also in the line inversion driving method, when the display color is increased by regularly arranging dots as in the dither method, or when the shading is repeated for each scanning line. In some cases, the sum of the voltage fluctuations ΔVs does not become zero, and the effect of canceling the voltage fluctuations ΔVs in the line inversion driving method may be lost.

As described above, in the conventional driving method,
In any of the driving methods, there remains a problem that smear occurs in the vertical direction of the screen in accordance with the display pattern, thereby deteriorating the display image quality.

An object of the present invention is to eliminate the above-mentioned problems, and an object of the present invention is to provide an active matrix type liquid crystal display device which does not cause smear and has good display quality regardless of the display image in any state. And a driving method thereof.

[0024]

In order to achieve the above-mentioned object, the present invention is directed to a plurality of scanning lines arranged in parallel, a plurality of signal lines arranged in parallel at right angles to the scanning lines, and a plurality of scanning lines and signal lines. In a method for driving an active matrix liquid crystal display device including a matrix substrate including a thin film transistor and a liquid crystal cell arranged at each intersection, and a scanning side driving circuit and a signal side driving circuit,
The display signal supplied to each signal line at each selection time of one scanning line is the one immediately before the selection time of the one scanning line.
A polarity inversion signal of the scan line of the selected time supplied display signal, the Ri Do and a display signal supplied to the subsequent said one scanning line selection time that the polarity inversion signal of the display signal
The signal indicates the phase of the display signal for each scanning line.
Phase shifts the scan signal supplied to the scan line.
When one scan line is selected
Comprising a first means Ru der what polarity is reversed between every.

Further, in order to achieve the above object, the present invention provides a method for producing a plurality of scanning lines arranged in parallel, a large number of signal lines arranged in parallel perpendicular to the scanning lines, and an intersection of each scanning line and each signal line. A matrix substrate having a thin film transistor and a liquid crystal cell respectively disposed thereon, a scanning side driving circuit for receiving a horizontal synchronization signal and sequentially supplying a scanning signal to each of the scanning lines, receiving an image signal and a polarity inversion setting signal, A signal side driving circuit for sequentially supplying a display signal to a signal line, a polarity inversion circuit for supplying the polarity inversion setting signal to the signal side driving circuit in response to a horizontal and vertical synchronization signal, and a phase and horizontal synchronization of an image signal Signal phase
; And a phase adjustment circuit for relatively adjusting the door, the display signal supplied to each signal line for every selection time of each one scanning line, one scanning line immediately before the one scanning line selection time includes a polarity inversion signal of the supplied display signal to the selected time, the first means consisting of a display signal supplied to the subsequent said one scanning line selection time it.

[0026]

According to the first and second means, during the selection time (1H) of each one scanning line, between the two electrodes of the liquid crystal cell within the selection time (1H) of the immediately preceding one scanning line. A cancel voltage for canceling the voltage fluctuation superimposed on the storage holding voltage is superimposed on the storage holding voltage between both electrodes of the liquid crystal cell. As a result, no matter what the displayed image is, no voltage fluctuation is continuously superimposed on the storage and holding voltage between the two electrodes of the liquid crystal cell. And the image quality of the displayed image is not degraded.

According to the first and second means,
At each selection time (1H) of one scanning line, the drain voltage obtained during the selection time (1H) of the immediately preceding one scanning line is used as a cancellation voltage after reversing the polarity, and is used as the cancellation time of the one scanning line (1H). Since the voltage is applied to the signal line at the same time, the polarity of the drain voltage is not inverted within the same selection time (1H) of one scanning line, and the load of writing the TFT on the liquid crystal cell is reduced. Therefore, the present invention can be applied to a high definition panel having a large number of scanning lines or an active matrix type liquid crystal display device having a high frame frequency.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a first embodiment of the active matrix type liquid crystal display device according to the present invention.

In FIG. 1, 1 is a matrix substrate, 2 is a scanning line, 3 is a signal line, 4 is a thin film transistor (TFT), 5 is a liquid crystal cell, 6 is a scanning side driving circuit, 7 is a signal side driving circuit, and 8 is a signal side driving circuit. A polarity inverting circuit, 9 a phase adjusting circuit, 10 a signal input terminal for inputting an image signal Data, 11 a sync signal input terminal for inputting a horizontal sync signal Hsync, and 12 a sync signal input for inputting a vertical sync signal. Terminal.

The matrix substrate 1 has a number of parallel scanning lines 2, a number of parallel signal lines 3 orthogonal to each scanning line 2, and an intersection of each of the scanning lines 2 and each of the signal lines 3. TFTs respectively arranged in
4 and a liquid crystal cell 5, and a circuit portion including each TFT 4 and the liquid crystal cell 5 forms one pixel. A scanning drive circuit 6 is connected to each scan line 2, a signal drive circuit 7 is connected to each signal line 3, and an input of the scan drive circuit 6 is connected to a synchronization signal input terminal 11. . The signal-side drive circuit 7 has one input connected to the display signal input terminal 10 via the phase adjustment circuit 9 and the other input connected to the output of the polarity inversion circuit 8. One input of the polarity inversion circuit 8 is connected to the synchronization signal input terminal 11, and the other input is connected to the synchronization signal input terminal 12.

FIG. 2 is a signal waveform diagram showing drive signal supply timings used in the driving method of the active matrix type liquid crystal display device according to the present invention.

In FIG. 2, Data is an image signal supplied to one input of the signal side drive circuit 7 of FIG. 1, and V _G1 is 1
The positive scan signal (gate-on voltage) supplied to the i-th scan line 2, V _Gi is the positive scan signal (gate-on voltage) supplied to the i-th scan line 2, and Vd is supplied to the signal line 3. Display signal (drain voltage). Note that the period from time t ₀ to time t ₁ , the period from time t _i-1 to time t _i , and the time t
Period from _i to time t _{i + 1} , time t _{i + 1} to time t
The period up to _{i + 2} is the selection time (1H) of one scan line.

[0034] Then, the in each period, the first gate-on voltage (scanning signal) V 1 th supply timing of the image signal D1 1 scan line selection time for _G1 (1
H), and is delayed by half the time (１ ／ · H) of H), and all other image signals, for example, (i−1) th, i
-Th, i + 1-th image signal Di-1, Di, Di + 1
Are also supplied at the (i−1) -th, i-th, and i +
The first gate-on voltage V _Gi-1 (not shown), V _Gi ,
VG _{i + 1} (not shown) is delayed by ・ · H. Further, as for the drain voltage (display signal) Vd, for example, the signal 13-
1 _i is a signal obtained by inverting the polarity of the (i−1) -th image signal Di−1, and the signal 13-2 _i applied in the i-th second half period is based on the i-th image signal Di. And the other drain voltage Vd
Are all the same.

Next, FIG. 3 is an operation explanatory diagram showing a voltage state stored and held between both electrodes of the liquid crystal cell 5, and the time is considerably shortened as compared with FIG.

Here, the operation of the first embodiment shown in FIG. 1 will be described with reference to a signal waveform diagram shown in FIG. 2 and an operation explanatory diagram of FIG.

First, the operation of the components composed of the matrix substrate 1, the scanning side drive circuit 6 and the signal side drive circuit 7 is the same as the operation of the above-mentioned conventional active matrix type liquid crystal display device. The description of the operation of the part is omitted, and the characteristic operation of the first embodiment will be described below.

Next, in the first embodiment, the image signal Data applied to the signal input terminal 10 is converted by the phase adjustment circuit 9 into a time (1 / 2.H) which is half the selection time (1H) of one scanning line. The horizontal synchronization signal Hsync and the synchronization signal input terminal 12 which are delayed and supplied to one input of the signal side drive circuit 7 and applied to the synchronization signal input terminal 11
Is characterized in that a polarity inversion instruction signal is generated in the polarity inversion circuit 8 based on the vertical synchronization signal Vsync applied to the other side and supplied to the other input of the signal side driving circuit 7. At this time, the signal-side driving circuit 7 receives the input image signal Da based on the input image signal Data delayed by ・ · H and the polarity inversion instruction signal.
A drain voltage (display signal) Vd delayed by 1 / 2.H with respect to ta is formed, and the first half period of the drain voltage (display signal) delayed by 1 / 2.H remains unchanged. In the latter half period of the drain voltage (display signal) delayed by 2 · H, the phase is inverted and transmitted to the corresponding signal line 3.

To describe this point in detail, for example,
Focusing on the selection time (1H) of the i-th one scan line, the signal applied in the first half period is the i-th one scan line.
The (i-1) -th 1 immediately before the scanning line selection time (1H)
Inverted drain voltage (cancel voltage) obtained by inverting the polarity of the drain voltage 13-2 _i-1 based on the (i-1) th image signal Di-1 applied to the signal line 3 during the latter half of the scan line selection time (1H). ) 13-1 is _i, followed the signal applied to the second half period, the i-th one scanning line selection period (1H) drain voltage based on the i-th image signal Di to be applied to (a write voltage ) 13-2
_i is the selection time of the other one scan line (1H)
The signals applied in the first half period and the second half period are exactly the same as in the case described above.

Further, for example, the inverted drain voltage (cancel voltage) 13-1 _i, the drain is applied to its second half period applied in the first half period of the i-th one scanning line selection period (1H) Voltage (write voltage) 1
3-2 _i has the same polarity (both are positive in the example shown), and the drain voltages 13-1 _i , 13-2 _i applied during the selection time (1H) of the i-th one scan line are ,
The drain voltages 13-1 _i-1 , 13-2 _i-1 , 13-1 _{i + 1} , 13 applied during the selection time (1H) of the (i-1) -th and (i + 1) -th one scanning line before and after that. -2
_{i + 1} has a different polarity (positive polarity and negative polarity in the illustrated example).

By the way, the storage and holding voltage between both electrodes of each liquid crystal cell 5 includes the selection time (1
H), the drain voltage applied in the latter half period, for example, 13-2 _i-1 is superimposed through the drain-source floating capacitance (not shown) of the corresponding TFT 4, and as shown in FIG. Slight voltage fluctuation Δ
Vs is generated, and this voltage fluctuation ΔVs is caused by the respective drain voltages applied during the first half period of the selection time (1H) of one scanning line immediately after the selection time (1H) of the respective one scanning line. (Writing voltage), for example, the inverted drain voltage (cancellation voltage) of 13-2 _i-1 , for example, 13-1 _i , so that it is immediately canceled, and as a result, the selection time (1H) of all one scanning line is obtained. , The time integration value of the voltage change ΔVs becomes zero, and the accumulation holding voltage is kept constant.

As described above, according to the first embodiment,
The drain voltage (writing voltage) applied in the latter half of the selection time (1H) of one scanning line, for example, 13-2 _i-1
The voltage fluctuation ΔVs of the accumulation holding voltage based on
Inverted drain voltage (cancel voltage) applied during the first half of the scan line selection time (1H), for example, 13-1
_{Since i} can be completely canceled, the vertical smear of the screen can be prevented from occurring regardless of the display pattern, and the display image can be prevented from deteriorating.

FIG. 4 is a block diagram showing the configuration of an active matrix type liquid crystal display device according to a second embodiment of the present invention.

In FIG. 4, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

The second embodiment is different from the first embodiment.
The difference from the first embodiment is that the phase adjustment circuit 9 is connected between the signal input terminal 10 and one input of the signal side drive circuit 7 in the first embodiment described above. In the second embodiment, only the point that the phase adjustment circuit 9 is connected between the synchronization signal input terminal 11 and the input of the scanning side driving circuit 6 is the same. Absent.

As for the operation of the second embodiment, the first embodiment uses the phase adjusting circuit 9 to
Adjusts the phase of the image signal Data is supplied to the signal input terminal 10, to the scanning signal (gate voltage) V _G of those that operate to delay the image signal Data only 1/2 · H In the second embodiment, the phase of the horizontal synchronizing signal Hsync supplied to the synchronizing signal input terminal 11 is adjusted by using the phase adjusting circuit 9, and as a result, the scanning signal (gate voltage) is adjusted. the image signal Data relative to V _G is a difference in a point which operates to delay only 1/2 · H, but for the remaining operations, the second and the first embodiment described above Since there is no difference from the second embodiment, further description of the operation of the second embodiment will be omitted.

Also in the second embodiment, the first embodiment
It is possible to obtain the same effect as obtained in the embodiment of the present invention, and it is possible to obtain a high quality display image with no vertical smear on the screen.

FIG. 5 is a block diagram showing a configuration of a third embodiment of the active matrix type liquid crystal display device according to the present invention, which is an example in which AC driving means is used together.

In FIG. 5, 7 'is a second signal side drive circuit, 14 is an AC counter substrate voltage generation circuit.
The same components as those shown in FIG. 1 are denoted by the same reference numerals.

The third embodiment is different from the first embodiment.
The difference from this embodiment is that the first embodiment is different from the first embodiment in that each signal line 3 is connected to one signal-side driving circuit 7 and the other end of each liquid crystal cell 5 is grounded. On the other hand, in the third embodiment, each signal line 3 corresponding to the first and second signal-side drive circuits 7 and 7 'is connected, and the other end of each liquid crystal cell 5 is connected. The only difference is that it is configured to be connected to the AC counter substrate voltage generation circuit 14, and there is no difference in the other points in terms of the configuration.

The operation of the third embodiment is different from that of the first embodiment in that the display signal (drain voltage) Vd is supplied from one signal side drive circuit 7. On the other hand, in the third embodiment, the first and second signal side drive circuits 7, 7 'cooperate with each other on each signal line 3.
Specifically, for example, each odd-numbered signal line 3 is
And the even-numbered signal lines 3 operate so that the display signal (drain voltage) Vd is supplied from the second signal-side drive circuit 7 '. In this embodiment, the opposite substrate voltage Vcom, which is inverted every selection time (1H) of one scan line, is supplied from the AC opposite substrate voltage generation circuit 14 to the other end (opposite electrode) of each liquid crystal cell 5. 5 is changed every selection time (1H) of the one scanning line, whereas the first embodiment does not supply the counter substrate voltage Vcom, and each liquid crystal cell 5 in that the voltage between the two electrodes is not changed for each selection time (1H) of the one scanning line.
Since there is no operational difference between this embodiment and the first embodiment, further description of the operation of the third embodiment will be omitted.

Also in the third embodiment, the first embodiment
It is possible to obtain the same effect as obtained in the embodiment of
A high quality display image without vertical smear on the screen can be obtained. In addition, by supplying the counter substrate voltage Vcom to each liquid crystal cell 5, the drain voltage (display signal) Vd applied to the drain of each TFT 4 can be reduced, which is required for each TFT 4. Since the writing ability can be reduced, the selection time (1H) of one scan line can be reduced, and a high-definition display screen can be realized.

FIG. 6 is a block diagram showing the structure of a fourth embodiment of the active matrix type liquid crystal display device according to the present invention.

In FIG. 6, reference numeral 15 denotes a level enhancement circuit (n
1 and the same components as those shown in FIG. 1 are denoted by the same reference numerals.

The fourth embodiment is different from the first embodiment.
The difference from this embodiment is that the output of the phase adjustment circuit 9 is directly connected to one input of the signal-side driving circuit 7 in the first embodiment, whereas the fourth embodiment is different from the first embodiment. The only difference is that the output of the phase adjustment circuit 9 is connected to one input of the signal-side drive circuit 7 via the level enhancement circuit (n-multiplication circuit) 15, and the other points There is no structural difference between this embodiment and the first embodiment.

FIG. 7 is a signal waveform diagram showing the supply timing of the drive signal used in the fourth embodiment.

In FIG. 7, Data is an image signal supplied to one input of the signal side driving circuit 7, V _Gi is a positive scanning signal (gate-on voltage) supplied to the i-th scanning line 2, and Vd is This is a display signal (drain voltage) supplied to the signal line 3. The period from time t _i-1, shown in Figure 7 until the time t _i, the time from the time t _i t
The period up to _{i + 1} and the period from time t _{i + 1} to time t _{i + 2} are the selection time (1H) of one scanning line.

In each of the above periods, for example, the supply timing of the i-th image signal Di with respect to the i-th gate-on voltage (scan signal) V _{Gi corresponds} to the selection time (1
H) less than half of time t), and all other image signals, eg, i−1, i,
The (i + 1) -th, i-th, and (i + 1) -th gate-on voltages V _{Gi -1} (not shown), V _Gi , and VG are also supplied to the (i + 1) -th image signals Di-1, Di, and Di + 1, respectively.
It is also delayed by t from _{i + 1} (not shown). Further, regarding the drain voltage (display signal) Vd, for example, the signal 16-1 applied during the i-th initial period is used.
_i inverts the polarity of the (i-1) th image signal Di-1;
And a signal obtained by multiplying the level by n, and a signal 16-2 applied in a period after the i-th.
_i is a signal obtained based on the i-th image signal Di, and the same applies to other drain voltages Vd.

The operation of the fourth embodiment differs from that of the first embodiment in that the image signal D
data is delayed by ・ · H, whereby the cancel voltage is applied in the first half of the selection time (1H) of each scanning line, and the write voltage is applied in the second half of the selection period (1H).
The fourth embodiment is different from the phase adjustment circuit 9 in that the image signal D
data is delayed by a time t shorter than １ ／ · H,
Further, the level is multiplied by n (where n> 1) in the level enhancement circuit (n multiplication circuit) 15, whereby the level is multiplied by n during the beginning of the selection time (1H) of each scan line. There is a difference in that the operation is such that a cancel voltage and a write voltage are applied to the corresponding liquid crystal cell 5 in a subsequent period.

That is, in the fourth embodiment, FIG.
As shown in (1), when attention is paid to the selection time (1H) of each one scanning line, for example, the selection time (1H) of one scanning line to which the i-th gate-on voltage V _Gi is supplied, the beginning from the beginning to time t. Is applied to the signal line 3 during the latter half of the (i-1) th scan line selection time (1H) immediately before the i-th one scan line selection time (1H). The polarity of the drain voltage (writing voltage) 16-2 _i-1 based on the ( _i-1 ) th image signal Di-1 is inverted, and the inverted drain voltage (cancelling voltage) 16-1 _i whose level is multiplied by n is used. The signal applied in the subsequent period is a drain voltage (writing voltage) 16- based on the i-th image signal Di to be applied during the selection time (1H) of the i-th one scanning line.
2 _i and the selection time of the other one scan line (1
The signals applied in the first period and the subsequent period of H) are exactly the same as in the case described above. In this case, if the multiple n is selected to be relatively large, the time t is selected to be short correspondingly. Conversely, if the multiple n is selected to be relatively large, the time t is preferably selected to be short correspondingly. , In general, n · t
So that the product of is approximately constant.

Further, there is no difference between the remaining operations of the fourth embodiment and the above-described first embodiment, and therefore, there is no further difference between the operations of the fourth embodiment. Is omitted.

In the fourth embodiment as well, the first
, The voltage variation Δ of the storage and hold voltage based on the corresponding write voltage, for example, 16-2 _i
Vs can be canceled by a cancel voltage, for example, 16-1 _{i + 1} , and the time integration of these voltage fluctuations ΔVs can be made zero, so that a high quality display image without vertical smear on the screen can be obtained. It has the effect that it can be obtained. In general, a corresponding write voltage, for example, 16-2 _i and a cancel voltage, for example, 16-1 _{i + 1}
Is desirably set to zero, but it goes without saying that it is not always required to be zero as long as the time integrated value decreases.

In the fourth embodiment, to construct the level enhancement circuit (n-multiplication circuit) 15, for example, a means for shifting the bits of the image signal Data or a look-up table using a read only memory (ROM) is used. A control circuit for controlling the period during which the cancel voltage is generated includes, for example, an analog switch and a resistor array controlled by a one-shot circuit and an output of a look-up table. May be used.

[0064]

As described above, according to the present invention,
In the latter half of the selection time (1H) of one scanning line, the voltage fluctuation ΔVs of the storage and holding voltage between both electrodes of each liquid crystal cell 5 based on the drain voltage Vd supplied from the signal line 3 to each liquid crystal cell 5 is calculated as described above. In the first half of the selection time (1H) of one scanning line immediately after the selection time (1H) of one scanning line, canceling is performed by the cancellation voltage supplied to each liquid crystal cell 5 from the signal line 3 as well. The time integration of the voltage fluctuation ΔVs can be made substantially zero, and there is an effect that a high quality display image can be obtained with no vertical smear on the screen in any display pattern.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the active matrix type liquid crystal display device according to the present invention.

FIG. 2 is a signal waveform diagram showing drive signal supply timings used in the method of driving an active matrix liquid crystal display device according to the present invention.

FIG. 3 is an operation explanatory diagram showing a voltage state stored and held between both electrodes of a liquid crystal cell.

FIG. 4 is a block diagram showing a configuration of a second embodiment of the active matrix type liquid crystal display device according to the present invention.

FIG. 5 is a block diagram showing a configuration of a third embodiment of the active matrix type liquid crystal display device according to the present invention.

FIG. 6 is a block diagram showing a configuration of an active matrix type liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 7 is a signal waveform diagram showing a supply timing of a drive signal used in a fourth embodiment.

FIG. 8 is a block diagram showing an example of a circuit configuration of a known active matrix type liquid crystal display device.

FIG. 9 is a partial configuration diagram showing one pixel portion in a known active matrix type liquid crystal display device.

FIG. 10 is a signal waveform diagram showing a supply timing of a drive signal for driving a portion of one pixel shown in FIG. 9;

11 is an operation explanatory diagram showing a voltage state stored and held between both electrodes of the liquid crystal cell shown in FIG. 9;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Matrix substrate 2 Scan line 3 Signal line 4 Thin film transistor (TFT) 5 Liquid crystal cell 6 Scan side drive circuit 7, 7 'Signal side drive circuit 8 Polarity inversion circuit 9 Phase adjustment circuit 10 Signal input terminal to which image signal Data is inputted 11 Synchronization signal input terminal to which horizontal synchronization signal Hsync is input 12 Synchronization signal input terminal to which vertical synchronization signal is input 14 Opposite substrate voltage generation circuit 15 Level enhancement circuit (n multiplication circuit)

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masuyuki Ota 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. Hitachi Research Laboratory (56) References JP-A-5-303077 (JP, A) JP-A-5-305 257123 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G02F 1/133 550 G09G 3/36

Claims (7)

(57) [Claims] A matrix substrate including a plurality of scanning lines arranged in parallel, a plurality of signal lines arranged in parallel perpendicular to the scanning lines, thin film transistors and liquid crystal cells respectively arranged at intersections of the scanning lines and the signal lines; A driving method of an active matrix type liquid crystal display device having a scanning side driving circuit and a signal side driving circuit,
The display signal supplied to each signal line at each selection time of one scanning line is the one immediately before the selection time of the one scanning line.
A polarity inversion signal of the scan line of the selected time supplied display signal, the Ri Do and a display signal supplied to the subsequent said one scanning line selection time that the polarity inversion signal of the display signal
The signal indicates the phase of the display signal for each scanning line.
Phase shifts the scan signal supplied to the scan line.
When one scan line is selected
The driving method of an active matrix type liquid crystal display device according to claim der Rukoto what polarity is reversed between every. 2. A scanning signal supplied to the scanning line.
The phase shift of the display signal with respect to the one scan line
2. The method according to claim 1 , wherein the selection time is selected to be substantially half of the selection time . 3. The polarity inversion signal of the display signal is a polarity inversion signal.
Is greater than the display signal level before the
Is shorter than the duration of the subsequent display signal
2. The method for driving an active matrix type liquid crystal display device according to claim 1, wherein: 4. A plurality of scanning lines arranged in parallel, said scanning
A large number of signal lines in a parallel arrangement orthogonal to the lines,
It is arranged at the intersection of the scanning line and each of the signal lines.
With thin film transistor and liquid crystal cell
Receiving horizontal synchronizing signal with substrate
A scanning side driving circuit for supplying a scanning signal;
And the display signal is sequentially transmitted to each of the signal lines.
Signal-side drive circuit for supplying signals and horizontal and vertical synchronization signals
The polarity inversion setting signal in response to the signal side driving circuit
Polarity inversion circuit to supply the image signal phase and horizontal synchronization
A phase adjustment circuit for relatively adjusting the phase of the signal.
And, supplied to each signal line for each inter-channel selection 択時 each one scanning line
The display signal to be output is the selection time of the one scan line.
Of the display signal supplied during the selection time of the immediately preceding scan line
When the polarity inversion signal and the subsequent one scan line are selected
And a display signal supplied therebetween.
Active matrix type liquid crystal display device. 5. The method according to claim 1, wherein the matrix substrate further comprises one scan.
AC opposite substrate voltage whose polarity is reversed every line selection time
Is connected to each liquid crystal cell.
5. The activator according to claim 4, wherein
B matrix liquid crystal display device. 6. An image signal is supplied to an input side of the signal side drive circuit.
Level to increase the signal level n times (however, n> 1)
5. The method according to claim 4, wherein an amplifying circuit is connected.
Active matrix liquid crystal display device of the mounting. 7. A level enhancement coefficient of the level enhancement circuit,
The amount of phase shift of the phase adjustment circuit is determined by the level of the image signal.
Bell multiple n and application time t of polarity inversion signal in display signal
Are selected so that the product n · t of
Active matrix liquid crystal display device according to claim 6, wherein the that.