JP3160930B2 - Readout circuit of semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read circuit of a semiconductor memory device, in particular, first selection means for selectively reading data stored in a plurality of storage means, and data read by the selection means. First information holding means for holding, transfer means for transferring data held in the first information holding means in synchronization with an external clock, and second information holding means for holding data from the transfer means And a second selecting means for selectively outputting data held in the second information holding means to an output port.

[0002]

2. Description of the Related Art Generally, an image memory is a matrix-like memory cell group (for example, DRAM) which can be randomly accessed.
Or an SRAM memory array) and a serial register that can be serially accessed, and a read circuit as an interface between them has a circuit configuration as shown in FIG. 7, for example.

On the screen, SA is a sense amplifier that amplifies data read from a memory cell to a bit line BL. The data from the memory cell amplified by the sense amplifier SA is supplied to a column selector Q that receives column select signals C ₀ , C ₁ ,.
c, Qc,..., the first information holding means F. F. D. The information holding means F. F. D is a 1-bit register composed of, for example, a flip-flop. This first information holding means F. F. The data stored in D is
In synchronization with an external clock, specifically, via a MOS transistor Qt switched by a transfer signal T, the second information holding means F. F. Transferred to S. Second information holding means F. F. S is a 1-bit register composed of, for example, a flip-flop, and the data stored in the register is read out to a data bus via Y selectors Qy, Qy,. It is.

In this format, a register of one bit is arranged for a plurality (n) of bit pairs forming one block BLK. Then, there are m blocks, and m bits of registers are arranged corresponding to the m blocks to form an m-bit serial register. Note that m is 4, for example.

[0005]

By the way, in the read circuit of the semiconductor memory device (image memory) as shown in FIG. 7, the output side of the column selectors Qc, Qc,. The output side of D)
It is difficult to obtain the required driving capability with a small sense amplifier SA. That is, n, for example 128 or 25
Since a column decoder for 6 bits is connected to one line, the parasitic capacitance of the line is inevitably increased. When a line having a large parasitic capacitance is driven by one small sense amplifier SA, a gate of a column selector is formed. The level of the output line of the column selector depends on whether the signal switches from “0” to “1” or the signal switches from “1” to “0” depending on whether the MOS transistor is an n-channel type or a p-channel type. It takes time to change. As a result, there is a problem in that a sufficient operation margin for transfer cannot be obtained, and the information reading time becomes long. Specifically, since the gate of the column selector is normally formed of an n-channel MOS transistor Qc, "1"
The operation margin when transferring (“H”) is poor. That is,
It is quick to switch from “1” to “0”, but it takes time to switch from “0” to “1”. However, if the column selector is formed of CMOS, this is not the case, but if so, the layout is difficult and high integration is hindered.

The present invention has been made to solve such a problem. In a semiconductor memory device such as an image memory, an operation caused by a large parasitic capacitance on the output side of a selecting means such as a column decoder is provided. It is an object of the present invention to prevent the margin from being reduced and to shorten the information reading time.

[0007]

A reading circuit of a semiconductor memory device according to the present invention comprises a first selecting means for selectively reading data stored in a plurality of storage means, and a reading means for reading data by the first selecting means. Buffer circuit for buffering the output data, first information holding means for holding data output from the buffer circuit, and transferring the data held in the first information holding means in synchronization with an external clock. Transfer means, second information holding means for holding data from the transfer means, second selection means for selectively outputting data held in the second information holding means to a data bus, Presetting means for presetting a line from which data is read by the first selecting means.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a reading circuit of a semiconductor memory device according to the present invention; FIG. 1 is a circuit diagram showing a first embodiment of a read circuit of a semiconductor memory device according to the present invention, and FIG. 2 is a time chart for explaining main operations thereof. In the drawing, SA is a sense amplifier, Qc,
Qc,... Are MOS transistors constituting a column selector which is the first selection means. F. D is first information holding means for storing data from the column selector, and is formed of, for example, a flip-flop to form a 1-bit register. Qt is the first information holding means F. F. D
A MOS transistor for transferring data stored in
F. F. S is the first information holding means F. F. D to MOS
The second information holding means for storing the data transferred via the transistor Qt, Qy is a Y selector (row decoder)
, And is controlled by the Y select signal Y to control the second information holding means F. F. The data stored in S is transmitted to the data bus.

Qp is a p-channel type preset MOS transistor which is turned on when a preset signal is received, and presets (precharges) the output line of the column selector to a "high" level. The difference between the present embodiment and the conventional example shown in FIG. 7 is that the present embodiment has the preset MOS transistor Qp.

Next, main operations will be described with reference to a time chart shown in FIG. The transfer request signal TREQ is "high"
Changes from “low” to “low”, the preset signal PRE arrives in synchronism therewith and the preset MOS transistor Q
p is turned on, and the output line of the column selector, that is, the first information holding means F.P. F. The input side of D is charged "high". When the charging is completed, the preset signal P
RE disappears, and the preset MOS transistor Qp turns off. Then, for example, 12
Data of the memory cells designated by the word signal are simultaneously read out to bit lines BL of 6 or 256 columns, and amplified by the sense amplifier SA. When the data has been read out to the bit line, a column select signal C is input, and one of the column-selected data is transferred from the bit line to the first information holding means F. F. It is transferred to the input terminal of D, where it is latched. The data is supplied to the second information holding means F. by the MOS transistor Qt.
F. The data is transferred by S, latched, and output to the data bus by the Y selector Qy.

According to the read circuit of the present semiconductor memory device, the output line of the column selector, that is, the first information holding means F. before the start of data transfer. F. Since the input terminal of D is preset, there is no danger that the operation margin is lost when "1" is transferred. That is, when "1" is transferred, the signal of that level is transferred as "1" in the precharged state, and when "0" is transferred, the signal is pulled down by the sense amplifier SA to "0". "0" is transferred, but the pull-down is fast because the column gate is an n-channel MOS transistor. Therefore, high-speed transfer can be performed. 2 of FIG.
The dotted line indicates the first information holding means F.1 in the case where "1" is transferred in the conventional example in order to compare the case of the present embodiment with the case of the conventional example. F. This shows a change in the level on the input side of D, and it can be seen that the present embodiment has a larger operation margin.

FIG. 3 is a circuit diagram showing a second embodiment of the read circuit of the semiconductor memory device according to the present invention, and FIG. 4 is a time chart thereof. The readout circuit of the present semiconductor memory device is one in which the present invention is applied to a readout circuit of a semiconductor memory device having two read ports, and the first information holding means F. per one bit of a serial register. F. D and second information holding means F. F. The number of S is two each. There are two MOS transistors Qt as transfer means and two MOS transistors Qy forming a Y selector.

The output signal of the column selector is transmitted to two first information holding means F. F. D1 and D2, the output of the column selector and the first information holding means F. F. Information distribution MOS transistors Qd, Qd controlled by distribution signals D1, D2 are provided between D1 and D2. Of course, it has a preset MOS transistor Qp and receives a preset signal before transfer to precharge the output line of the column selector.
Is not different from the readout circuit of the semiconductor memory device shown in FIG.

There is essentially no difference in the operation shown in FIG. 4, and only when the transfer request signal TReg is "low" (memory active period), the distribution signal D becomes "high".
The only difference is that there is an operation in which the distribution MOS transistor Qd related to distribution is turned on.

FIG. 5 is a circuit diagram showing a third embodiment of the read circuit of the semiconductor memory device according to the present invention, and FIG. 6 is a time chart thereof. This embodiment is different from the column selector and the first information holding means F.1 of the second embodiment shown in FIG. F. By providing a buffer circuit between D1 and D2 and substantially separating the buffer circuit, the load on the output side of the column selector is reduced, and higher speed can be achieved. However, there is no particular difference from the other embodiments in other points.

Each information holding means F. F. Is, for example, 2
It consists of a flip-flop that combines two inverters. In that case, the inverter for transmitting a signal is constituted by a large MOS transistor, and the inverter for positive feedback is an MO having a smaller gate length and a larger gate length.
It is preferable to use an S transistor. Further, the information holding means F. F. D and F. F. S may have a phase matching MOS transistor on the output side of the inverter that transmits the signal, in addition to the two inverters. Also, if the gate of the column selector is pchMO
In the case of an S transistor, it takes a long time to transfer “0”, so that the preset is not a charge but a discharge. Therefore, it can be said that the present invention can be applied to a case where the gate forming the first selecting means is an n-channel MOS transistor or a p-channel MOS transistor.

[0017]

According to the first aspect of the present invention, there is provided a read circuit for a semiconductor memory device, wherein first read means for selectively reading data stored in a plurality of storage means, and data read by the first select means. A buffer circuit for buffering the data, first information holding means for holding data output from the buffer circuit, and transfer means for transferring the data held in the first information holding means in synchronization with an external clock. A second information holding means for holding data from the transfer means, a second selection means for selectively outputting data held in the second information holding means to a data bus, Presetting means for presetting a line from which data is read by the selecting means. Therefore, according to the read circuit of the semiconductor memory device of the present invention, since the preset means is provided, it is possible to preset (precharge or predischarge) the output side of the first information holding means before reading the signal. Can,
As a result, it is possible to prevent a decrease in operation margin due to a large parasitic capacitance and not only to shorten the operation time, but also to provide a buffer provided between the first selecting means and the first information holding means. The circuit makes it possible to substantially separate the first selecting means from the first information holding means, thereby reducing the load applied to the output side of the first selecting means. As a result, the speed can be further increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a read circuit of a semiconductor memory device of the present invention.

FIG. 2 is a time chart for explaining a main operation of the first embodiment of the read circuit of the semiconductor memory device of the present invention;

FIG. 3 is a circuit diagram showing a second embodiment of the read circuit of the semiconductor memory device of the present invention.

FIG. 4 is a time chart for explaining main operations of a second embodiment of the read circuit of the semiconductor memory device of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the read circuit of the semiconductor memory device of the present invention.

FIG. 6 is a time chart for explaining a main operation of a third embodiment of the read circuit of the semiconductor memory device according to the present invention;

FIG. 7 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 Qc First selection means F. F. D. First information holding means Qt transfer means F. F. S second information holding means Qy second selecting means Qp presetting means

Claims (1)

(57) [Claims] First selecting means for selectively reading data stored in claim 1 a plurality of storage means, the data read out by said first selecting means buffer
Buffer circuit for storing data output from the buffer circuit .
Information transfer means for transferring data held in the first information hold means in synchronization with an external clock; second information hold means for holding data from the transfer means; A second selection means for selectively outputting the data held in the second information holding means onto a data bus; and a preset means for presetting a line from which data is read by the first selection means. Read circuit of semiconductor memory device characterized by the above-mentioned.