JP3157122B2 - Method for ion implantation into silicon carbide and silicon carbide semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of implanting ions into silicon carbide and a semiconductor device manufactured using the method.

[0002]

2. Description of the Related Art In recent years, SiC (silicon carbide) has attracted attention as an electronic material for high-temperature operation devices, large power devices, high breakdown voltage devices, and the like. FIG. 14 is a schematic sectional view showing an example of a conventional MESFET (metal semiconductor field effect transistor) using SiC.

In FIG. 14, a p-type isolation layer 42 and an n-type active layer 43 are sequentially formed on an n-type SiC substrate 41 by an epitaxial growth method. An n ⁺ contact layer is formed on the n-type active layer 43 by an epitaxial growth method, and a central region (gate electrode forming region) is removed by etching. Thus, n ⁺ contact layers 45a and 45b are formed at a predetermined interval. n
A gate electrode 46 is formed on the active layer 43, and a source electrode 47 and a drain electrode 48 are formed on the n ⁺ contact layers 45a and 45b, respectively.

[0004] In the MESFET of FIG.
7 and the drain electrode 48, n ⁺
A current flows in the n-type active layer 43 via the contact layers 45a and 45b. In this case, since the n ⁺ contact layers 45a and 45b are provided on the n-type active layer 43, the current cannot flow completely parallel to the layers in the n-type active layer 43 as shown by the dashed arrows. . Therefore, MESFE
It is difficult to improve the performance such as the mutual conductance (gm) of T.

[0005]

Therefore, it has been studied to selectively form an n ⁺ contact layer in an n-type active layer using an ion implantation method. FIG. 15 shows a MESFET having an n ⁺ contact layer formed by an ion implantation method.
FIG. 4 is a schematic cross-sectional view showing an example of the first embodiment.

In FIG. 15, a p-type isolation layer 52 and an n-type active layer 53 are sequentially formed on an n-type SiC substrate 51 by an epitaxial growth method. In the n-type active layer 53, n ⁺ contact layers 55a and 55b are formed at predetermined intervals by ion implantation. A gate electrode 56 is formed on n-type active layer 53, and n ⁺ contact layer 55
Source electrode 57 and drain electrode 58 are formed on a and 55b, respectively.

In the MESFET of FIG. 15, when a voltage is applied between the source electrode 57 and the drain electrode 58, a current flows in the n-type active layer 53 via the n ⁺ contact layers 55a and 55b. In this case, since the n ⁺ contact layers 55a and 55b are provided in the n-type active layer 53, current can flow in the n-type active layer 53 in parallel with the layers, as indicated by the dashed arrows. Therefore, MESFE
It is possible to improve the performance such as the mutual conductance (gm) of T.

In the MESFET of FIG. 15, in order to further improve the performance such as mutual conductance, n ⁺
It is necessary to make the impurity concentration (carrier concentration) of the contact layers 55a and 55b uniform in the depth direction.

Conventionally, a multiple ion implantation method has been known as a method for uniformly implanting an impurity element into a crystal material in a depth direction. The multiple ion implantation method is a method in which an impurity element is ion-implanted while changing an acceleration energy and an implantation amount.

FIG. 16 is a view showing a method of ion-implanting an impurity element into a SiC substrate by a multiple ion implantation method.
In FIG. 16, a mask 62 made of SiO ₂ having a thickness of 3000 ° is formed on a SiC substrate 61, and nitrogen ions (N ⁺ ) are implanted as impurity elements at an acceleration energy of, for example, 30 keV, and then nitrogen ions are accelerated by 40 keV. By ion implantation with energy, an n ⁺ ion implantation layer 63 is formed.

FIG. 17 is a diagram showing the concentration distribution in the depth direction of the impurity element ion-implanted into the SiC substrate 61 by the multiple ion implantation method of FIG. As shown in FIG. 17, the impurity element implanted at an acceleration energy of 30 keV is distributed in a shallow region, and the impurity element implanted at an acceleration energy of 40 keV is distributed in a deep region. Thereby, the concentration distribution of the impurity element becomes substantially flat in the depth direction as a whole.

However, when the acceleration energy increases, the concentration distribution of the implanted impurity element expands in the depth direction. As a result, the implanted impurity element is
May penetrate into the SiC substrate 61.
In order to prevent this, the thickness of the mask 62 is set to 5000
ÅIt is necessary to make it bigger.

However, depending on the material of the mask 62, it may be difficult to form the mask 62 thick on the SiC substrate 61. When the mask 62 is formed thick, the mask 62
Due to the difference in thermal expansion coefficient between the SiC substrate 61 and the SiC substrate 61, the SiC substrate 61 may be warped or the mask 62 may be peeled off during the manufacturing process. Therefore, it is difficult to form a thick mask 62 on SiC substrate 61.

Further, when the acceleration energy of the impurity element is increased, crystal defects are generated up to a deep region of the SiC substrate 61, and the total number of crystal defects is increased. Therefore, it is necessary to raise the ion implantation temperature (substrate temperature) in order to suppress crystal defects and to perform annealing at a high temperature of about 1500 ° C. in order to recover crystallinity. As a result, the amount of energy required for manufacturing the FET increases, and the manufacturing cost increases.

An object of the present invention is to provide an ion implantation method capable of implanting an impurity element into silicon carbide uniformly at a low implantation temperature in a depth direction with few crystal defects.

Another object of the present invention is to provide a silicon carbide semiconductor device which can be manufactured at a relatively low temperature and has few defects.

[0017]

According to a first aspect of the present invention, there is provided a method for ion-implanting silicon carbide into silicon carbide, the method comprising: adding impurity elements to silicon carbide along a direction parallel to a predetermined arrangement direction of constituent elements of silicon carbide; And an impurity element is ion-implanted into silicon carbide along a direction inclined at a predetermined angle from the alignment direction.

According to the ion implantation method of the present invention, when the impurity element is ion-implanted along a direction inclined at a predetermined angle from the arrangement direction of the constituent elements of silicon carbide, the impurity element collides with the constituent element of silicon carbide. Because the probability is high,
The impurity element is implanted in a shallow region of silicon carbide. On the other hand, when the impurity element is ion-implanted in a direction parallel to the alignment direction of the constituent elements of the silicon carbide, the probability that the impurity element collides with the constituent element of the silicon carbide is reduced. Implanted into the region. In this case, the impurity element is implanted at a low acceleration energy into the deep region without colliding with the constituent elements of silicon carbide, so that the number of crystal defects due to the implantation of the impurity element is small. As a result, the impurity element is implanted at a relatively low temperature in the depth direction of silicon carbide almost uniformly and with few crystal defects.
In addition, the crystallinity can be restored and the implanted impurity element can be electrically activated at a relatively low temperature.

In particular, it is preferable that ion implantation along a direction parallel to the alignment direction and ion implantation along a direction inclined at a predetermined angle from the alignment direction are performed with substantially the same acceleration energy.

In this case, since the impurity element is implanted from the surface to the deep region in silicon carbide without increasing the acceleration energy, the number of crystal defects is reduced.

Further, the impurity element is preferably nitrogen or boron. In this case, since nitrogen or boron has a smaller mass than silicon which is a constituent element of silicon carbide, the impurity element can be almost uniformly and reproducibly injected into silicon carbide with low acceleration energy.

A direction parallel to the alignment direction is a channeling direction, and a direction inclined by a predetermined angle from the alignment direction is a random direction. In this case, at the time of ion implantation in the channeling direction, the probability that the impurity element collides with the constituent elements of silicon carbide is reduced, and the impurity element is implanted into a relatively deep region. At the time of ion implantation in the random direction, the impurity element is carbonized. The probability of colliding with the constituent elements of silicon increases, and the impurity element is implanted into a relatively shallow region. Thereby, the impurity element is implanted almost uniformly in the depth direction.

It is preferable to perform ion implantation along a direction parallel to the alignment direction and ion implantation along a direction inclined at a predetermined angle from the alignment direction while maintaining the silicon carbide at a temperature of 500 ° C. or more and 800 ° C. or less. . In this case, generation of crystal defects is suppressed, and resistance of the ion-implanted silicon carbide is reduced.

According to a second aspect of the present invention, in the semiconductor device, the impurity element is ion-implanted into the silicon carbide along a direction parallel to the predetermined alignment direction of the constituent elements of the silicon carbide, and a direction inclined at a predetermined angle from the alignment direction. Along with a silicon carbide ion-implanted layer.

In this case, the ion implantation layer is formed at a relatively low implantation temperature and with few crystal defects. Therefore, defects of the semiconductor device are reduced, and good characteristics are obtained.

[0026]

FIG. 1 is a schematic sectional view for explaining an ion implantation method according to an embodiment of the present invention.

In FIG. 1, an n-type 6H-SiC substrate 11
A mask 12 made of SiO ₂ having a thickness of 3000 ° is formed on the (0001) Si surface, and nitrogen (N) is ion-implanted as an impurity element. As the ion implantation conditions, the acceleration energy of nitrogen ions (N ⁺ ) was set to 30 keV,
The dose is 3 × 10 ¹⁵ cm ^-2 (maximum impurity concentration is about 9 ×
20 ²⁰ cm ⁻³ ), and the substrate temperature (ion implantation temperature) is 700 ° C. In this case, ion implantation in a direction inclined by 7 ° from a direction perpendicular to the (0001) Si plane (hereinafter referred to as random implantation) and ion implantation in a direction perpendicular to the (0001) Si plane (hereinafter referred to as channeling implantation) I do.

After the ion implantation, the mask 12 is removed and 11
The impurity element implanted by heat treatment at 50 ° C. for 3 minutes is electrically activated and crystallinity is recovered. This allows
An n ⁺ ion implantation layer 13 is formed. In this case, the carrier concentration of the n ⁺ ion implantation layer 13 is 1 × 10 ¹⁹ cm ⁻³ , and the sheet resistance is 1 kΩ / □.

The SiC substrate 1 is formed by the ion implantation method shown in FIG.
The concentration distribution (profile) in the depth direction of the impurity element ion-implanted in No. 1 was measured by SIMS (secondary ion mass spectrometry). The result is shown in FIG.

The peak of the concentration distribution of the impurity element implanted by random implantation at an implantation angle of 7 ° is in a region of 0.1 μm in depth from the surface of the SiC substrate 11, and the impurity implanted by channeling implantation at an implantation angle of 0 °. The peak of the concentration distribution of the element is in a region at a depth of 0.15 μm from the surface of the SiC substrate 11. As described above, when the random implantation and the channeling implantation are used together, the impurity element is implanted to a depth about 1.5 times that of the random implantation. In this case, the tail of the concentration distribution due to the 0 ° channeling injection does not exceed a depth of 0.3 μm.

Since the mask 12 made of SiO ₂ is amorphous, the concentration distribution of the impurity element implanted into the mask 12 is almost the same as the concentration distribution by random implantation at 7 °. That is, the depth of the impurity element implanted into mask 12 is sufficiently shallower than 3000 °. Therefore, according to the ion implantation method of the present embodiment, the film thickness of 3000
It is possible to form the n ⁺ ion implanted layer 13 with few crystal defects by using the mask 12 made of SiO ₂ .

The concentration distribution of the impurity element in the depth direction by random implantation can be obtained by the following formula (Gaussian distribution).

[0033]

(Equation 1) In the above formula, N (x) represents an impurity concentration [number / cm ² ] at a depth x, dose represents an implantation amount [number / cm ² ] of an impurity element, Rp represents a peak position of a concentration distribution, ΔRp represents the spread of the concentration distribution (see FIG. 3).

The peak position Rp of the concentration distribution and the spread ΔRp of the concentration distribution can be obtained by calculation from the type of ion and the acceleration energy. For example, acceleration energy 30k
When implanting N ⁺ into SiC at eV, Rp = 545
[Å], ΔRp = 214 [Å], and when injecting into SiO ₂ , Rp = 657 [Å], ΔRp = 255 [Å]
Becomes

Next, the current-voltage characteristics of the n ⁺ ion-implanted layer obtained by the ion implantation method of the present invention were measured. FIG.
FIG. 3 is a schematic cross-sectional view showing the structure of an evaluation sample used for measuring current-voltage characteristics.

As shown in FIG. 4, the carrier concentration is 1 × 10
^A carrier concentration of 7 is formed on a p-type SiC substrate 21 of ¹⁸ cm ^-3.
A p-type epitaxial layer 22 of × 10 ¹⁵ cm ^-3 is formed. N is ion-implanted into the p-type epitaxial layer 22 by the above-described random implantation and channeling implantation to form an n ⁺ ion implantation layer 23.

The ion implantation temperature is set to 500 ° C., 600 ° C., 7
A plurality of samples were prepared by changing the temperature to 00 ° C, 800 ° C, and 900 ° C. Then, at 1150 ° C. in an Ar atmosphere, 3
The annealing was performed for minutes. Four electrodes 24 made of Ni having a diameter of 110 μm are formed on the n ⁺ ion-implanted layer 23 at a pitch of 3 μm.
It was formed at 00 μm.

As shown in FIG. 5, a voltage V was applied between the two electrodes 24 of the sample manufactured by the above method, and a current I was measured. FIG. 6 shows the measurement results of the current-voltage characteristics. Ohmic characteristics were obtained in a sample manufactured at an ion implantation temperature of 500 ° C to 900 ° C. Note that FIG. 6 shows the measurement results of samples typically manufactured at ion implantation temperatures of 700 ° C., 800 ° C., and 900 ° C.

Next, in the above sample, the sheet resistance Rs of the n ⁺ ion-implanted layer 23 was measured by the method shown in FIG. 5, and the contact resistance Rc was measured by the method shown in FIG.

The sheet resistance Rs is calculated by the following equation.

[0041]

(Equation 2) The contact resistance Rc is calculated by the following equation.

[0042]

(Equation 3) In the above equation, A is the electrode area [cm ² ], Iad is the current [A] between the two electrodes a and d on both sides, S is the electrode pitch [cm], and φ is the electrode diameter [cm].

FIG. 8 shows the measurement results of the sheet resistance Rs and the contact resistance Rc of the n ⁺ ion implantation layer 23.

FIG. 8 shows that the values of the sheet resistance Rs are almost equal in the range of the ion implantation temperature of 500 to 800 ° C., and particularly the lowest at the ion implantation temperature of 700 ° C. Also,
The value of the contact resistance Rc is set between 500 and 8 for the ion implantation temperature.
In each case, a small value of 1.7 kΩ / □ or less was obtained in the range of 00 ° C. As described above, the sheet resistance Rs and the contact resistance Rc of the n ⁺ ion implantation layer 23 manufactured at the low ion implantation temperature of 500 to 800 ° C. are low.

When the ion implantation method of the present invention is used, crystal defects are reduced by about 10 to 20% as compared with the case of using the conventional multiple ion implantation method, the annealing temperature is reduced, and the electrical activation of impurity elements is performed. The rate is improved.

FIGS. 9 to 11 are schematic sectional views showing a method for manufacturing a MESFET using the ion implantation method of the present invention.

In FIG. 9, the n-type 6H-SiC substrate 1
Is 3.5 from the (0001) Si plane in the [1 1 -20] direction.
° It has a crystal growth surface inclined. The carrier concentration of the n-type 6H—SiC substrate 1 is 3.9 × 10 ¹⁷ cm ⁻³ . On this n-type 6H-SiC substrate 1, a p-type separation layer 2 having a thickness of 5 μm and an n-type active layer 3 having a thickness of 0.3 μm are formed by epitaxial growth. The carrier concentration of the p-type isolation layer 2 is 7.0 × 10 ¹⁵ cm ⁻³ , and the carrier concentration of the n-type active layer 3 is 1.7 × 10 ¹⁷ cm ⁻³ .

Next, as shown in FIG.
A mask 4 made of SiO ₂ having a thickness of 3000 ° and a length of 15 μm is formed thereon. Then, N is ion-implanted as an impurity element into the n-type active layer 3 by random implantation at 7 ° to form n ⁺ contact layers 5a and 5b. As the ion implantation conditions, the acceleration energy is 30 keV, and the dose is 5 × 10 ¹⁵ cm ⁻² . The implantation depth is about 0.1 μm and the maximum impurity concentration is about 9 × 10 ²⁰ cm.
It is ^-3 .

Further, as shown in FIG. 11, N-type as an impurity element is
Is ion-implanted. As for the ion implantation conditions, the acceleration energy is set to 30 keV and the dose is set to 5 × 10 ¹⁵ cm ⁻² as in the case of the random implantation of 7 °. Then A
Anneal at 1150 ° C. for 3 minutes in an r atmosphere. In this case, the carrier concentration is about 10 ¹⁹ cm ⁻³ . Thus, n ⁺ contact layers 5a and 5b having a depth of about 0.2 μm are formed.

Next, as shown in FIG.
To form the gate electrode 6 of the gate length 2μm and a gate width 300μm of Au that n-type to the active layer 3 and the Schottky contact above, n ⁺ contact layer 5a, 5b
A source electrode 7 and a drain electrode 8 made of Ni which are in ohmic contact with the n ⁺ contact layers 5a and 5b are formed thereon. In order to alloy Ni, a heat treatment is performed at 950 ° C. for 30 seconds in an Ar atmosphere.

Then, the n ⁺ contact layers 5a and 5b, the n-type active layer 3 and the p-type isolation layer 2 in the element isolation region are subjected to RIE.
Etching is performed by a dry etching technique such as a (reactive ion etching) method.

The drain current (Id) -source-drain voltage (Vds) of the MESFET manufactured by the above method.
The properties were measured. FIG. 13 shows the measurement results. MES
The channel depth of the FET is about 0.3 μm. This ME
The transconductance (gm) of the SFET is 10 mS / m
m (calculated value 12 mS / mm) and the conventional (about 7 mS / m
m).

As described above, in the MESFET manufactured by the ion implantation method of the present invention, the current can flow uniformly not only in a region near the surface but also in a deep region in the n-type active layer 3, so that the mutual conductance and the like can be reduced. The properties are improved.

In the above embodiment, the ion implantation method of the present invention is used for forming the contact layers for the source electrode and the drain electrode of the MESFET. For the formation of a contact layer for the semiconductor device and the formation of another ion-implanted layer.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an ion implantation method according to an embodiment of the present invention.

FIG. 2 is a diagram showing a measurement result of a concentration distribution in a depth direction of an impurity element ion-implanted into an n-type SiC substrate by the ion implantation method of FIG.

FIG. 3 is a diagram for explaining a method of calculating a concentration distribution in the depth direction of an impurity element by random implantation.

FIG. 4 is a schematic cross-sectional view showing a structure of an evaluation sample used for measuring current-voltage characteristics of an n ⁺ ion implantation layer.

FIG. 5 is a diagram for explaining a method for measuring current-voltage characteristics of an n ⁺ ion-implanted layer.

FIG. 6 is a diagram showing a measurement result of a current-voltage characteristic of an n ⁺ ion implantation layer.

FIG. 7 is a diagram for explaining a method of calculating a contact resistance of an n ⁺ ion implantation layer.

FIG. 8 is a diagram showing a measurement result of the ion implantation temperature dependence of the sheet resistance and the contact resistance of the n ⁺ ion implantation layer.

FIG. 9 shows a MESFET using the ion implantation method of the present invention.
FIG. 5 is a first step cross-sectional view showing the method for manufacturing the same.

FIG. 10 shows a MESFE using the ion implantation method of the present invention.
FIG. 11 is a second process sectional view illustrating the method of manufacturing T;

FIG. 11 shows a MESFE using the ion implantation method of the present invention.
FIG. 13 is a third process sectional view illustrating the method of manufacturing T;

FIG. 12 shows a MESFE using the ion implantation method of the present invention.
FIG. 14 is a fourth process sectional view illustrating the method of manufacturing T;

FIG. 13 shows a MESFE manufactured by the method shown in FIGS.
FIG. 6 is a diagram showing a drain current-source-drain voltage characteristic of T.

FIG. 14 shows n ⁺ formed by an epitaxial growth method.
It is a typical sectional view of the conventional MESFET which has a contact layer.

FIG. 15 is a schematic cross-sectional view of a MESFET having an n ⁺ contact layer formed by an ion implantation method.

FIG. 16 is a schematic cross-sectional view for explaining a multiple ion implantation method.

FIG. 17 is a diagram showing a concentration distribution in the depth direction of an impurity element ion-implanted into a SiC substrate by a multiple ion implantation method.

[Explanation of symbols]

Reference Signs List 1 n-type 6H-SiC substrate 2 p-type separation layer 3 n-type active layer 4 mask 5 n ⁺ contact layer 6 gate electrode 7 source electrode 8 drain electrode 11 n-type 6H-SiC substrate 12 mask 13 n ⁺ ion implantation layer 21 p -Type SiC substrate 22 p-type epitaxial layer 23 n ⁺ ion-implanted layer 24 electrode

Claims (6)

(57) [Claims] An impurity element is ion-implanted into the silicon carbide along a direction parallel to a predetermined alignment direction of constituent elements of the silicon carbide, and the silicon carbide is along a direction inclined at a predetermined angle from the alignment direction. Implanting the impurity element into the silicon carbide. 2. The method according to claim 1, wherein the ion implantation along the direction parallel to the alignment direction and the ion implantation along the direction inclined at the predetermined angle from the alignment direction are performed at substantially the same acceleration energy. For ion implantation into silicon carbide. 3. The method according to claim 1, wherein the impurity element is nitrogen or boron. 4. The silicon carbide according to claim 1, wherein the direction parallel to the alignment direction is a channeling direction, and the direction inclined by the predetermined angle from the alignment direction is a random direction. Ion implantation method 5. The method according to claim 1, wherein the silicon carbide is at least 500.degree.
The ion implantation along the direction parallel to the alignment direction and the ion implantation along the direction inclined at the predetermined angle from the alignment direction while maintaining at the following temperature. The method for implanting ions into silicon carbide according to any one of the above. 6. The impurity element is ion-implanted into the silicon carbide layer along a direction parallel to a predetermined alignment direction of the constituent elements of the silicon carbide layer, and the impurity element is formed along a direction inclined at a predetermined angle from the alignment direction. A silicon carbide semiconductor device, comprising: an ion implantation layer formed by ion implantation of an impurity element.