JP3156327B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display data control device suitable for displaying a large amount of high-speed display data on a liquid crystal display panel, such as a personal computer or a workstation.

[0002]

2. Description of the Related Art As a conventional technique for displaying display data of a personal computer, a work station or the like on a liquid crystal panel, the configuration and latch timing of the display data are described in Hitachi LCD Driver LSI Data Book pages 661 and 662. Hereinafter, description will be made with reference to FIGS. 2, 3, 4, and 12.

FIG. 2 is a block diagram of a liquid crystal display data control device according to the prior art. Reference numeral 1 denotes a display data generating means for generating display data of 6a and a synchronization signal of 7a such as a personal computer or a work station; apparatus,
8 is a signal drive driver, 4 is a liquid crystal display data control device 1
Numeral 0 is control signal generating means for generating a 7d synchronization signal for controlling the signal driving driver 8, and 2 converts input display data 6a into display data in a format along the input interface of the signal driving driver 8. Data conversion means.

FIG. 3 is a system configuration diagram for driving a color liquid crystal panel having a total of 1920 pixels, each of which has 640 horizontal R, G, and B pixels, and 480 vertical pixels. . The signal drive drivers 8a and 8b are HD66310 manufactured by Hitachi, and the number of outputs is 160 as described in the Hitachi LCD driver LSI data book.
4-pixel data parallel input, maximum operating frequency 15 MHz. Therefore, 8a for simultaneously driving the pixels in the horizontal direction
6 and 8b are required respectively. Reference numeral 11 denotes a scanning driver.

FIG. 4 shows the data conversion means 2 shown in FIG.
The input display data 6a is serialized into the output display data 6d.
FIG. 4 is a diagram illustrating timing for performing parallel data conversion.

FIG. 12 shows a signal driver 8 shown in FIG.
It is a figure showing the connection state of a.

Next, returning to FIG. 2, the operation of the present system configuration will be described. The R, G, and B three-pixel parallel display data 6a generated by the display data generation means 1 is transmitted to control signals 7a,
As shown in FIG. 4, serial / parallel conversion is performed by the data conversion means 2 in synchronization with 7b and 7d, and the upper and lower four pixels along the input format of the signal drive drivers 8a and 8b, for a total of eight pixels Convert to output data. Input 3
Eight cycles of R, G, B data of a pixel are converted into four cycles of eight pixel data having a cycle twice as long as the input data. Next, the operation of sequentially latching the eight pixel output data in the signal driver will be described with reference to FIG. EI
O1 is an input of a chip enable signal, EIO2 is an output of a chip enable signal.
O1 is cascade-connected, and the signal driver of the subsequent stage is activated by the EIO2 signal of the preceding stage. The six signal driving drivers 8a are provided with an input chip enable signal EIO.
When 1 is enabled, 4 pixels of display data are stored internally.
The display data for a total of 160 pixels is fetched 0 times, and the output chip enable signal EIO2 to the next stage is enabled. Further, the six signal drive drivers 8b are similarly connected and perform the same operation. As described above, the display data is sequentially latched by the signal driving driver, and the display data for one line is latched by the signal driving drivers 8a and 8b.
One line is simultaneously output to the liquid crystal panel 12 and displayed. Therefore, in this configuration, the display data for one line, that is, the upper and lower six signal driver drivers 8a and 8b are transferred in parallel with four pixel drivers and six signal driver drivers in series.

As described above, in the example of the prior art, the output data period is twice as long as the input data period. Therefore, the maximum operating frequency 15 of the signal driver 8a, 8b
The maximum frequency of the input data is 30 MHz with respect to MHz.
z. At this time, the frame frequency which is a frequency for scanning one screen of the liquid crystal panel is a maximum of about 97 Hz (= 30 MHz).
z ÷ 640 ÷ 480).

However, the panel resolution tends to be higher today, and a high-definition color liquid crystal panel having a total of 3360 pixels, 1120 horizontal pixels for each of R, G and B, and a total of 780 vertical pixels has been conventionally used. In the case of displaying by technology, eleven signal drive drivers are required for each of the upper and lower drivers. At this time,
When one line of display data is transferred in series with 11 signal driver drivers in parallel with four pixels, the frame frequency drops to about 34 Hz in order to satisfy the maximum operating frequency of 15 MHz of the signal driver driver. 6
In the current liquid crystal panel where 0 Hz or more is required,
There is a problem that flicker occurs and display quality is deteriorated.

[0010]

In the above prior art, the display data is transferred in accordance with the operation speed of the signal driver of the liquid crystal display panel. Therefore, when the display resolution increases and the display data increases, the display data is correspondingly increased. There has been a problem that the frame frequency of the liquid crystal display panel becomes slow and flicker tends to occur.

An object of the present invention is to reduce the frame frequency of a liquid crystal display panel at a low operation speed of a signal driver even if the display resolution of the liquid crystal display panel is increased and the display data is increased and the transfer speed of the display data is increased. To maintain good display quality.

[0012]

As a means for solving the above-mentioned problems, a liquid crystal display data control device includes a control means for generating liquid crystal display data and a control signal. Two storage units having a storage capacity are provided, and each of the storage units has a storage area of L (<
M) means for dividing and inputting display data to each storage area in order, and displaying the display data stored in each storage means to L
Means for simultaneously reading from one area, and when one of the two storage means performs the write operation of the display data for one horizontal line, the other storage means performs the read operation of the display data of the previous line. Control means and a switching means for switching the data bus read from the two storage means. Alternatively, the control means for generating the liquid crystal display data and the control signal is provided with two storage means having a storage capacity for display data driven by L (<M) signal driver drivers, and each of the storage means Means for dividing an area into L and sequentially writing input display data to each storage area, and means for simultaneously reading out display data stored in each storage means from the L areas, wherein one of the two storage means When performing the write operation of the display data driven by one signal driver, the other storage means
There are provided control means for controlling a read operation of display data driven by the signal drive drivers and switching means for switching data buses read from the two storage means. Alternatively, in addition to the above means, a data time division control means for time division of display data to the signal driver is provided.

[0013]

According to the above means, it is possible to simultaneously drive the L signal driver drivers, and to reduce the display data transfer speed to the signal driver without changing the display data transfer speed for one line. be able to. In other words, even if the display resolution of the liquid crystal display panel increases and the amount of display data increases, and the transfer speed of the display data increases,
The frame frequency of the liquid crystal display panel can be increased at a low operation speed of the signal driving driver, and good display quality can be maintained.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A storage means having a storage capacity for two lines is provided.
FIGS. 1, 5, 6, 7, and 13 for the first embodiment.
This will be described with reference to FIG.

FIG. 1 is a block diagram showing one embodiment of the present invention.
Is display signal generating means for generating the display data of 7a and the synchronization signal of 7a, 8 is a signal driver, 10 is the display data of 6d and 6d of display data for driving the signal driver 8 from the display data of 6a and the synchronization signal of 7a. This is a liquid crystal display data control device that generates a synchronization signal. 6a, 6b, 6c, 6
d is display data, and 7a, 7b, 7c and 7d are synchronization control signals. 2a and 2b are data conversion means, and 3 is a memory. Reference numeral 4 denotes a control signal 7b from the synchronization signal 7a to the data conversion means 2a, 2b and the memory control means 5.
And a control signal generating means for generating a synchronizing signal 7d for the signal driver 8; and 5, a memory control means for generating a control signal 7c for controlling reading / writing of the memory 3.

FIG. 5 is a detailed block diagram of the memory control means 5, and 52 is a control signal generation means for generating a control signal from the control signal 7b. 55a and 55b are control signals generated by the control signal generation means 52. 50 is a control signal 55
A memory read address generating means for generating a memory read address from a, a memory write address generating means 51 for generating a memory write address from the control signal 55a, and 56a and 56b a memory read address and a memory write address. 53 and 54 are selecting means for selecting a memory read address 56a and a memory write address 56b by a control signal 55b. Reference numerals 30 and 31 denote memories for storing the display data 6b, which control the read / write operation by the control signal 7c, and output the read data as the display data 6c.

FIG. 6 is a system configuration diagram for driving a high-definition color liquid crystal panel having 12 horizontal pixels of 1120 pixels each for R, G, and B, for a total of 3360 pixels, and having 780 vertical pixels. Reference numerals 8a and 8b denote signal driver drivers for converting the synchronization signal 7d and the display data 6d into a liquid crystal driving voltage and outputting the same.
60 lines, 4-pixel data parallel input, maximum operating frequency 15M
Hz. Therefore, 11 pieces for {8a} ({3360 {2}
160) and 8b each require 11 pieces ({3360 ÷ 2 ÷ 160)). Further, the signal driving drivers 8a and 8b
Driver numbers 1, 2, 3, 4, 5, 6, 7, 8, 9, and 1
The display data buses 0 and 11 are common. That is, the present system configuration is configured to simultaneously transfer display data to the four driver groups. 11 is the synchronization signal 7
This is a scanning drive driver that generates a vertical scanning signal from d and drives the liquid crystal panel 12.

FIG. 7 is a diagram showing the read / write timing of the memory, and FIG. 13 is a diagram showing the connection state of the signal driver 8a shown in FIG.

Returning to FIG. 1, the operation of the present embodiment for simultaneously transferring display data to the upper and lower four signal drive drivers will be described. The display data 6a of the R, G, and B three pixels parallel generated by the display data generating means 1 is transmitted to the control signal 7b.
In parallel with the above, serial / parallel conversion is performed by the data conversion means 2a, and the data is converted into parallel 8-pixel display data 6b. Here, the reason why the display data is converted into eight pixels in parallel is because the input interface of the upper and lower signal drive drivers 8a and 8b is four pixels each, so that continuous display data is controlled every eight pixels. Then, as shown in FIG. 7, the display data 6b is written in the memory A30 and the memory B31 one line at a time, alternately for every eight pixels. The memory A30 and the memory B31 are respectively divided into four areas corresponding to the four driver groups (driver numbers 1, 2, 3 and 4, 5, 6, and 7, 8, 9, and 10, 11). The display data is written into the area of the signal driver to be operated. Then, the display data written in the memory A30 and the memory B31 are sequentially read from the four areas alternately in the next line to be written, and become the display data 6c as shown in FIG. The display data 6c is stored in the data conversion unit 2b.
The four upper and lower drivers (driver numbers 1, 4, 7,
10 and 2, 5, 8, 11 and 3, 6, 9), the display data is converted into display data 6d of 32 pixels in parallel so that the display data can be transferred simultaneously for each four pixels. Then, the panel drive control signal 7
The display data 6d is transferred to the signal driver 8 in synchronization with the signal d.

Next, the operation of sequentially latching the 32-pixel output data in the signal driver will be described with reference to FIG. EIO1 is an input of a chip enable signal,
EIO2 is an output of a chip enable signal. When the input chip enable signal EIO1 is enabled, 4 is output internally.
The display data of the pixel is taken 40 times, and the display data of a total of 160 pixels is taken in, and the output chip enable signal EI to the next stage is taken.
O2 is enabled. In the signal driver 8a,
The driver numbers 1, 4, 7, and 10 have the same EIO1, and the driver numbers 1, 2, 3, 4, 5, 6, 7, 8, 9, and 1
EIO2 of the preceding stage of 0 and 11 and EIO1 of the succeeding stage are cascaded, and the signal driver of the subsequent stage is activated by the EIO2 signal of the preceding stage. The eleven signal drive drivers 8b are similarly connected, and perform the same operation.

By the connection and operation of such a signal driver, the following display data transfer is performed. First, the display data 6d is simultaneously transferred to the signal drive drivers of driver numbers 1, 4, 7, and 10, and after 160 pixels have been transferred to each signal driver, the driver numbers 2 and
Display data 6 is simultaneously supplied to 5, 8 and 11 signal driver drivers.
When the transfer of 160 pixels to each signal driver is completed, the display data 6d is simultaneously transferred to the signal drive drivers of driver numbers 3, 6, and 9, and when the transfer of 160 pixels is completed to each signal driver, one line is transferred. The data transfer for the minute ends. The operation for one line is repeated in the same manner. As described above, the display data 6d is sequentially latched by the signal drive driver, and when the signal drive drivers 8a and 8b latch the display data for one line, the display data is output to the liquid crystal panel 12 for one line and displayed. Therefore, in this configuration, 1
For the line, that is, 11 signal drive drivers 8 each for upper and lower
The display data for a and 8b can be transferred in series with three signal drive drivers in parallel with four pixels.

Next, in the first embodiment, the storage capacity for one line, that is, 22 drivers is used. However, the second embodiment having two storage means having the storage capacity for eight drivers for one line or less. 1, 5, 8, 9, and 14 for the embodiment.
This will be described with reference to FIG. The block configuration of this embodiment is the same as that of the first embodiment and is shown in FIGS.

FIG. 8 is a system configuration diagram for driving a high-definition color liquid crystal panel having 12 horizontal pixels of 1120 pixels each for R, G and B, that is, a total of 3360 pixels, and having 780 vertical pixels. Reference numerals 8a and 8b denote signal driver drivers for converting the synchronization signal 7d and the display data 6d into a liquid crystal driving voltage and outputting the same.
60 lines, 4-pixel data parallel input, maximum operating frequency 15M
Hz. Therefore, 11 pieces for {8a} ({3360 {2}
160) and 8b each require 11 pieces ({3360 ÷ 2 ÷ 160)). Further, the signal driving drivers 8a and 8b
Driver numbers 1, 5, 9 and 2, 6, 10, 3, 7, 11
And the display data buses 4 and 8 are common. That is, the present system configuration is configured to simultaneously transfer display data to the four driver groups. 11 is the synchronization signal 7
This is a scanning drive driver that generates a vertical scanning signal from d and drives the liquid crystal panel 12.

FIG. 9 is a diagram showing the read / write timing of the memory, and FIG. 14 is a diagram showing the connection state of the signal driver 8a shown in FIG.

Next, the operation of the present embodiment for simultaneously transferring display data to the upper and lower four signal driver drivers will be described. The operation of converting the display data into the parallel 8-pixel display data 6b shown in FIGS. 1 and 5 is the same as in the first embodiment. Then, as shown in FIG. 9, the memory A30 and the memory B31 correspond to four driver groups (driver numbers 1, 5, 9, 2, 6, 10, 3, 7, 11, 11, and 8). Each is divided into four regions. Then, the display data 6b is stored in the area of the corresponding signal driver.
Driver numbers 1, 2, 3, 4 and 5, 6, 7,
8 and 9, 10, and 11 alternately in the memory A 30 and the memory B 31 in units of driver groups.
Write for each or three. First, the display data of the signal driver of the driver numbers 1, 2, 3, and 4 is written into the memory A30, and then the driver numbers 5, 6, and 6 are written.
The display data of the signal driving drivers 7 and 8 are stored in the memory A31.
At the same time, and during this period, driver numbers 1, 2, 2,
The display data of the signal driving drivers 3 and 4 are stored in the memory A30.
Are sequentially read from the four areas. Next, driver numbers 9 and 1
The display data of the 0, 11 signal driver is stored in the memory A3.
0, and at the same time, during this period, the driver numbers 5,
Display data of 6, 7, 8 signal drive drivers are stored in memory A
31 are sequentially read from the four areas, and when this is completed, the display data of the signal driver of the driver numbers 9, 10, and 11 is sequentially read from the four areas of the memory A30. The operation for one line is repeated in the same manner. That is,
Each of the memories A30 and B31 requires a storage capacity of a total of 16 for eight signal driver drivers. The display data 6c alternately read from the memory A30 and the memory B31 is converted by the data conversion means 2b into four upper and lower drivers (driver numbers 1, 2, 3, 4 and 5, 6, 7, 8, 9, 10, 10). In 11), the display data is converted into display data 6d of 32 pixels in parallel so that display data can be transferred simultaneously for each of four pixels. Then, the display data 6d is transferred to the signal driver 8 in synchronization with the panel drive control signal 7d.

Next, the operation of sequentially latching the 32-pixel output data in the signal driver will be described with reference to FIG. EIO1 is an input of a chip enable signal,
EIO2 is an output of a chip enable signal. When the input chip enable signal EIO1 is enabled, 4 is output internally.
The display data of the pixel is taken 40 times, and the display data of a total of 160 pixels is taken in and the output chip enable signal EI to the next stage is taken.
O2 is enabled. In the signal driver 8a,
The EIO1 of the driver numbers 1, 2, 3, and 4 is common.
Then, EIO2 of driver number 4 is replaced with driver number 5,
The cascade connection is made to the EIO1 of 6, 7, and 8, and the signal drive drivers of the driver numbers 5, 6, 7, and 8 are activated by the EIO2 of the driver number 4. Similarly, the EIO2 of the driver number 8 is cascade-connected to the EIO1 of the driver numbers 9, 10, and 11, and the EIO2 of the driver number 8 activates the signal driver of the driver numbers 9, 10, and 11. The eleven signal drive drivers 8b are similarly connected, and perform the same operation.

The following display data transfer is performed by such connection and operation of the signal driver. First, the display data 6d is simultaneously transferred to the signal drive drivers of driver numbers 1, 2, 3, and 4, and after 160 pixels have been transferred to each signal driver, the driver numbers 5, 6, and 6 are next transferred.
The display data 6d is simultaneously transferred to the signal drivers 7 and 8, and after 160 pixels have been transferred to each of the signal drivers, the display data 6d is simultaneously transferred to the signal drivers of the driver numbers 9, 10, and 11 simultaneously. When the transfer of 160 pixels to each signal driver is completed, the data transfer for one line is completed. The operation for one line is repeated in the same manner. As described above, the display data 6d is sequentially latched by the signal drive driver, and when the signal drive drivers 8a and 8b latch the display data for one line, the display data is output to the liquid crystal panel 12 for one line and displayed. Therefore, in this configuration, one line, that is, eleven upper and lower signal drive drivers 8 are provided.
The display data for a and 8b can be transferred in series with three signal drive drivers in parallel with four pixels.

Next, a third embodiment in which the number of output data buses of the second embodiment is halved will be described with reference to FIGS. 5, 9, 10, 11, 15, and 16. FIG. .

FIGS. 5 and 15 are block diagrams of the present embodiment. In FIG. 15, reference numeral 20 denotes data time division control means for performing time division control on the display data 6a, and reference numeral 6e denotes time division display data. .

FIG. 10 shows that the number of twelve horizontal pixels is R, G, B.
A system configuration diagram for driving a high-definition color liquid crystal panel having 1360 pixels each having a total of 3360 pixels and having 780 vertical pixels, and 8a and 8b are synchronizing signals 7d
And a signal driver for converting display data 6e into a liquid crystal driving voltage and outputting the same. Hitachi HD66310, 160 output lines, 4-pixel data parallel input, maximum operating frequency 15
MHz. Therefore, 11 in 8a ({3360} 2
$ 160), 11 for 8b ($ 3360/2160)
Each is required. Also, the signal driving drivers 8a, 8b
Are the driver numbers 1, 2, 5, 6, 9, 10 and 3, 4,
The display data buses 7, 8, and 11 are common. That is,
This system configuration is configured to simultaneously transfer time-division display data to the two driver groups. 1
Reference numeral 1 denotes a scanning drive driver that generates a vertical scanning signal from the synchronization signal 7d and drives the liquid crystal panel 12.

FIG. 9 is a diagram showing the read / write timing of the memory, and FIG. 11 is a diagram showing the latch timing of the time-division display data of the signal driving driver.
11 is a diagram showing a connection state of the signal driving driver 8a shown in FIG.

Next, the operation of this embodiment for simultaneously transferring display data to the upper and lower four signal driver drivers will be described. The display data shown in FIG. 5, FIG. 9, and FIG.
The operation of converting into the display data 6d of two pixels is the same as in the second embodiment. Then, the display data 6d of 32 pixels in parallel
Is further converted into time-division display data 6e by the data time-division control means 20. The data time division control and the data latch timing of the signal driver will be described with reference to FIG. The data latch clocks are provided with φ1 and φ2 which are 180 ° out of phase with each other, and φ1 is connected to an odd-numbered signal driver and φ2 is connected to an even-numbered driver. The odd-numbered driver data and the even-numbered driver data are transferred to the display data bus in a time-sharing manner at a half cycle of the data latch clock. The odd-numbered driver data is the data latch clock φ1, and the even-numbered driver data is the data latch clock φ2. Latch at the falling edge of. That is, by performing the time-division control to halve the display data cycle while keeping the operating frequency of the signal driver, the display data bus can be shared and the number of buses can be reduced. Then, the display data 6e thus time-divisionally controlled is transferred to the signal driver 8 in synchronization with the panel drive control signal 7d.

Next, the operation of sequentially latching the 32-pixel output data in the signal driver will be described with reference to FIG. EIO1 is an input of a chip enable signal,
EIO2 is an output of a chip enable signal. When the input chip enable signal EIO1 is enabled, 4 is output internally.
The display data of the pixel is taken 40 times, and the display data of a total of 160 pixels is taken in, and the output chip enable signal EI to the next stage is taken.
O2 is enabled. In the signal driver 8a,
The EIO1 of the driver numbers 1, 2, 3, and 4 is common.
Then, EIO2 of driver number 3 is replaced with driver number 5,
7 is cascaded to EIO1 and driver number 3 is connected to EIO1.
The signal drive drivers of driver numbers 5 and 7 are activated by IO2. Similarly, EIO2 of driver number 4 is cascaded to EIO1 of driver numbers 6 and 8, signal driver of driver numbers 6 and 8 is activated by EIO2 of driver number 4, and EIO2 of driver number 7 is replaced with driver numbers 9 and 8. 11 is connected in cascade to EIO1 of driver number, the signal drive drivers of driver numbers 9 and 11 are started by EIO2 of driver number 7, EIO2 of driver number 8 is cascaded to EIO1 of driver number 10, and the driver is driven by EIO2 of driver number 8. The signal driver of No. 10 is started. The eleven signal drive drivers 8b are similarly connected, and perform the same operation.

The following display data transfer is performed by the connection and operation of the signal driver. First, the display data 6e is simultaneously transferred to the signal driving drivers of the driver numbers 1, 2, 3, and 4, and after 160 pixels have been transferred to each signal driver, the driver numbers 5, 6, and 6 are next transferred.
When the display data 6e is simultaneously transferred to the signal drivers 7 and 8 and the transfer of 160 pixels to each signal driver is completed,
Next, the display data 6e is simultaneously transferred to the signal drive drivers of driver numbers 9, 10, and 11, and 1 is sent to each signal driver.
When the transfer of 60 pixels is completed, the data transfer for one line is completed. The operation for one line is repeated in the same manner. As described above, the display data 6e is sequentially latched by the signal driver, and when one line of display data 6e is latched by the signal drivers 8a and 8b, one line is simultaneously output to the liquid crystal panel 12 for display. Therefore, in this configuration, one line, that is, eleven upper and lower signal drive drivers 8 are provided.
The display data for a and 8b can be transferred in series with three signal drive drivers in parallel with four pixels.

In the case of the first, second, and third embodiments described above, the operating frequency is 120 MHz with respect to the maximum operating frequency of the signal driver of 15 MHz.
The maximum frame frequency is 137 Hz (= 120 MHz ÷ 1)
120 ÷ 780), and even if the resolution of the panel increases, the frame frequency does not decrease and a good display quality can be obtained.

In the above embodiment, the HD66310 made by Hitachi was used for the signal drive driver.
The present invention can be realized by changing the number of divisions of the signal driver and the configuration of the memory, even if the signal driver uses different interfaces such as the operating frequency and the number of data input pixels.

[0037]

According to the present invention, the L signal driver can be driven simultaneously, and the display data transfer speed to the signal driver can be reduced without changing the display data transfer speed for one line. Even if the display resolution of the display panel is increased and the display data is increased and the display data transfer speed is increased, the operation speed of the low-speed signal driver is satisfied and the frame frequency of the liquid crystal display panel is increased. And good display quality can be maintained. Further, since the transfer speed of display data can be reduced, electromagnetic radiation can also be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional technique.

FIG. 3 is a system configuration diagram according to the related art.

FIG. 4 is a diagram showing display data timing conversion according to the related art.

FIG. 5 is a block diagram of a memory control unit.

FIG. 6 is a system configuration diagram of the first embodiment.

FIG. 7 is a diagram showing read / write timing of the memory according to the first embodiment;

FIG. 8 is a system configuration diagram of a second embodiment.

FIG. 9 is a diagram showing read / write timing of the memory according to the second embodiment.

FIG. 10 is a system configuration diagram of a third embodiment.

FIG. 11 is a diagram illustrating data latch timing of a signal driver.

FIG. 12 is a detailed configuration diagram of a conventional signal driver.

FIG. 13 is a detailed configuration diagram of a signal driver according to the first embodiment.

FIG. 14 is a detailed configuration diagram of a signal driver according to a second embodiment.

FIG. 15 is a block diagram showing a third embodiment.

FIG. 16 is a detailed configuration diagram of a signal driver according to a third embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Display data generation means, 2, 2a, 2b ... Data conversion means, 3, 30, 31 ... Memory, 4 ... Control signal generation means, 5 ... Memory control means, 6a, 6b, 6c, 6d, 6e ... Display data 7a, 7b, 7c, 7d, 55a, 55b ... control signals, 8, 8a, 8b ... signal drive drivers, 10 ... liquid crystal data control device, 11 ... scan drive drivers, 12 ... liquid crystal panels, 20 ... data time division control Means: 50: memory read address generation means, 51: memory write address generation means, 52: control signal generation means, 53, 54: selection means, 56a: memory read address, 56b: memory write address.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tsutomu Furuhashi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Inventor Koji Takahashi 3300 Hayano, Mobara-shi, Chiba (56) References JP-A-1-113793 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/36 G09G 3/20

Claims (8)

(57) [Claims] 1. A liquid crystal drive which inputs display data and a synchronization signal.
Control means for generating liquid crystal display data and control signals for operation
When,One line of liquid crystal display data is input sequentially, and
Convert to working voltage and outputWith multiple signal driver
Composed,Each display pixel part is composed of switching elements and liquid crystal
Active matrix type liquid crystal panel and
A liquid crystal display device comprising: a control unit for generating the liquid crystal display data and a control signal.
Storage capacity of display data capacity for one horizontal line
And divided into multiple storage areasStorage means;  inputDisplay data in each storage areaWriting means; and display data written in the storage means.The plurality of notes
Means for reading from each storage area; Each read display data is converted to a corresponding signal drive.
Means for transferring to a dynamic driver
Liquid crystal display. (2)The liquid crystal display device according to claim 1, The control means records the display data capacity for one horizontal line.
Second storage having a storage capacity and divided into a plurality of storage areas
Means for displaying one of the two storage means
While writing data, display data from the other storage means
A liquid crystal display device for reading data. (3)The liquid crystal display device according to claim 1, The storage capacity of the storage means is the plurality of signal drive drives.
A liquid crystal display device, the number of which is equal to the number of buses. (4)Input display data and synchronization signal, and
Control means for generating liquid crystal display data and control signals for operation
And the liquid crystal display data for one line
Multiple signal drive drivers that convert to operating voltage and output
And each display pixel section With the switching element and the liquid crystal
Active matrix type liquid crystal panel and
A liquid crystal display device comprising Control means for generating the liquid crystal display data and the control signal;
Storage capacity of display data capacity for one horizontal line
And the first and second divided into a plurality of storage areas.
Storage means; Means for writing input display data to each storage area; The display data is stored in one of the first and second storage means.
When writing data, each storage area of the other storage means
Means for reading display data from the Each read display data is converted to a corresponding signal drive.
Means for transferring to a dynamic driver
Liquid crystal display. (5)The liquid crystal display device according to claim 4, The storage capacity of the storage means is the plurality of signal drive drives.
A liquid crystal display device, the number of which is equal to the number of buses. 6.Input display data and synchronization signal, and
Control means for generating liquid crystal display data and control signals for operation
And liquid crystal display data for one line are sequentially input, and the liquid crystal drive
M signal drive drivers (M
Is an integer of 2 or more).
Matrix tie consisting of a liquid crystal element and liquid crystal
Liquid crystal display device comprising a liquid crystal panel of Input display data to M signal driver drivers L (<M)
Divided into groups, each of the L groups
In contrast, the display data for one line is divided into L pieces.
Liquid crystal display device characterized by transferring partial display data
Place. 7.The liquid crystal display device according to claim 6, Of the display data driven by the L signal driver drivers.
Two storage means having a storage capacity are provided;
The means divides the storage area into L parts and stores the display data to be inputted in each part.
Means for writing to the storage area and display data stored in each storage means.
Means for reading data from the L areas.
One of the storage means performs a write operation. The other day
Control means for controlling the storage means to perform a read operation;
Switching between data buses read from two storage units
Switching means provided to drive L signal driver drivers simultaneously
A liquid crystal display device characterized by being made possible. Claim 8.The liquid crystal display device according to claim 7, The storage capacity of each of the storage means is the plurality of signal drives.
Liquid crystal display device characterized by the number of drivers
Place.