JP3154502B2 - Signal amplifier circuit and semiconductor memory device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit for a signal on a data bus line of a memory mainly using a field effect transistor (MIS transistor such as a MOS transistor) such as a DRAM and an SRAM. The data bus mentioned here is not narrowly defined as a long wire for transmitting a signal on a bit line from a memory cell array to a peripheral circuit, but is broadly defined as a portion connecting between a column selection gate and a bit line difference voltage amplifying unit. belongs to.

Since the signal on the data bus of the memory is very small, a circuit for amplifying the signal with high gain and converting the signal to a digital level is required. For this reason, a differential pair using a current mirror is used for the amplifier circuit.

[0003]

2. Description of the Related Art FIG. 2 shows a conventional circuit. The circuit shown is
It has a data bus load circuit 1 and a data bus amplifier 2
You. Where Q₁, Q_TwoIs the load on the data buses DB and DBX
An n-channel MOS transistor forming an element,
Diode connected, power supply V_CCnear
Memory cell array when reading.
Transistor (not shown) in the sense amplifier SA on the negative side
Is the transistor Q_a, Q _bOf the memory cell MC through
Data bus voltage is reduced toward ground level based on data
This is V_CCTrying to pull up
I do. This driving force and load Q₁, Q_TwoCurrent supply capacity
The data read voltage that appears on the data bus is determined by the
This is a minute value of about 0.5 V or less. De
The reason for limiting the data bus voltage in this way is that
The next time you read the data at another address,
If both data are reversed, the data bus voltage will be reversed.
This is because the smaller the amplitude, the higher the speed.
You.

Since the voltage amplitude of the data bus is small,
A circuit with a large voltage amplification factor is required to amplify
You. By the way, MOS transistors are bipolar transistors
Unlike the star, gm is low and high amplification rate is difficult to obtain,
MOS differential circuit using current mirror for load is relatively
High gain is obtained. p channel MOS transistor Q ₇
And Q₈, Q₉And Q_TenConstitutes the current mirror, and the voltage
Amplifying drive transistor Q_ThreeAnd Q_Four, Q_FiveAnd Q₆Is
Rent mirror Q₇And Q₈, Q₉And Q_TenThe load as differential
Amplify. Two differential amplifier circuits are provided in parallel.
Force OUT₁, OUT_TwoTo Q_Four, Q_FiveGet from the drain of
That's why. Q_ThreeAnd Q_Four, Q_FiveAnd Q₆Form a differential pair
Therefore, complementary output can be obtained with only one differential pair,
This complementary output has poor symmetry (Q_Three, Q₆Side or mosquito
To extract the gate voltage of the rent mirror, the reverse Q_Four, Q_Five
The amplitude is smaller and distorted than the side).
It is better to take the output from the opposite side using two differential pairs
Good.

[0005] transistor Q ₁₁ is a switch for cutting flowing through the circuit unless it is necessary, phi _EN clock when the high operating differential pair circuit becomes inoperative when the low level. C ₁ and C ₂ are parasitic capacitances of the output circuit. Y indicates a column selection signal, and WL indicates a word line.

[0006]

In the conventional current mirror load type amplifying circuit, since the voltage amplitude of the data bus is limited and is at most 500 mV, a large current of about 100 .mu.A to 200 .mu.A flows through the amplifying MOS transistor. The gm of the transistor is increased and used. For this reason, power consumption is large, and when many amplifier circuits are operated in parallel at the same time, there is a problem that a large IR drop occurs in a power supply or a ground wiring.

In the conventional circuit, the load elements Q ₁ and Q ₂ function to suppress the amplitude of the data bus, and the current flowing therethrough is useless. The amplifying sections Q _{3 to} Q ₁₀ output the suppressed data. Since it is a voltage amplifier (voltage input, voltage output) for amplifying the voltage amplitude of the bus, an element having a large gm is required. However, there is a problem that the MOSFET is not originally optimal for this purpose.

It is an object of the present invention to improve this point and to provide an amplifier circuit for a data bus signal which can obtain a high gain and consume less current.

[0009]

As shown in FIG. 1A, in the present invention, a pair of complementary signal lines DB and DBX are connected to first and second current mirror circuits 11 (Q ₂₁ , Q ₂₂ ) and 12. (Q
Through _24, Q ₂₅₎ one of the transistors Q _21, Q ₂₅ of the connection to the power supply V _CC. The third transistors Q ₂₂ and Q ₂₄ of these current mirror circuits, which are output terminals,
Connected to the current mirror 13 (Q ₂₃ , Q ₂₆ )
T is from this connection and from the transistor Q ₂₂ , Q ₂₃ side,
Alternatively, as shown in FIG. 1 (B), it is taken out from the transistors Q ₂₄ and Q ₂₆ .

[0010]

According to this circuit configuration, current consumption can be reduced. That complementary signal lines DB, DBX current by the current mirror Q ₂₁ and Q _22, Q ₂₄ and Q _25, (which is converted into the current by the gm ratio k) Q _22, Q becomes a current of _24, this current mirror Q _23, since the same current by Q ₂₆ is pulling the difference becomes the output current OUT.

[0011] Thus, the complementary signal line DB, but k times the difference between the DBX of the current is the output OUT, the current of the now complementary signal line DB is I, the current of the DBX is set to 0, the current of Q ₂₂ is kI, current of Q ₂₄ is 0, the current mirror Q _26, Q
The current of ₂₃ becomes zero. Therefore, kI goes to the output OUT. Further when the current of DBX is I, the current of the DB is to 0, the current of Q ₂₄ is KI, Q _26, current Q ₂₃ also KI, Q ₂₂
Becomes zero. As described above, in these cases, in this amplifier circuit, no current constantly flows from the power supply V _CC to the ground, and all the currents become input / output currents, so that the current consumption is small.

The gain is also large. This is the complementary signal line side
Capacity C_Three, C_FourAnd output side capacitance C ₁, C_TwoDepending on the ratio of
And the latter is much smaller, so k = 1
The output voltage changes much faster and has a large amplitude.
You. This is further increased if k> 1.

[0013]

FIG. 1 shows a first embodiment of the present invention. In the figure, p-channel MOS transistors Q ₂₁ and Q ₂₂ , Q
₂₄ and Q ₂₅ respectively constitute the current mirror circuit 11,
Sources and drains of one of the transistors Q ₂₁ and Q ₂₅ are connected to a power supply V _CC and data buses DB and DBX, and the other transistors Q ₂₂ and Q ₂₄ are currents formed by n-channel MOS transistors Q ₂₃ and Q _26. Connect to mirror circuit 13. The data buses DB and DBX are connected to the transistor Q ₂₁
And Q ₂₂ and the gates of Q ₂₄ and Q ₂₅ . Transistors of the current mirror Q _21, Q _25, Q ₂₆ is the gate, but is short-circuited between the drain and the gate of the transistor Q _22, Q _23, drain is a non-shorting, transistor Q ₂₂ of the non-shorted, Q ₂₃ The output OUT is taken out from the interconnection point.
Data buses DB and DBX extend from the memory cell array. C ₃ and C ₄ are parasitic capacitances attached to the data bus, column selection gates of Q _a and Q _b , SA is a sense amplifier and transistors Q _c , Q _d , It has a flip-flop consisting of Q _f, Q _g, the transistors Q _e and Q _h (the x means inversion) clock phi _s and phi _sx connecting the flip-flop between the power supply when is on. Also,
Reference numeral 14 denotes a next stage CMOS converter having transistors Q _i and Q _j .

[0014] Since the transistor Q ₂₁ and Q ₂₂ in this circuit is a current mirror circuit 11, when the Q ₂₁ and Q ₂₂ are the transistors having the same performance, current equal to the drain current of Q ₂₁ flows to Q _22. Current flowing through the transistor Q _21, the sense amplifier SA or circuit corresponding thereto in the cell array is a current for driving the data bus. For example, the data bus D connected to the transistor Q ₂₁
It is assumed that there is read data in a direction in which the voltage on the B side is reduced. In this case current I flows toward the drain of the transistor Q ₂₁ in the cell array. Current I is turned on by the column selection signal Y transistors Q _a, one Q _b of Q _b
Through to ground. As described above, the sense amplifier is generally a flip-flop, and the bit lines (BL, BL
X) One is turned on and the other is turned off by the potential, and is pulled down to ground and pulled up to V _CC . The column gates (Q _a , Q
_The data selected in _b ) is added to the data buses DB and DBX to determine the potential of the data bus. In this example, the pull-down side of the sense amplifier SA is connected to the data bus DB, and the pull-up side is connected to the data bus DBX.

Transistor Q_{twenty one}When current I flows through
_{twenty two}Is Q_{twenty one}Transistor to configure the current mirror with
TA Q_{twenty two}To Q_{twenty one}The same current is going to flow. Data bus
On the DBX side, the inside of the sense amplifier SA is at the power supply level.
Current does not flow. Even if it flows, high sense amplifier
Transient situation before level-side node is high enough
Only. Therefore, the transistor Q_{twenty five}Current flows through
And therefore transistor Q_{twenty four}No current flows. this
By transistor Q₂₆Since no current flows through
And the transistor Q forming a current mirror_{twenty three}Also off
It is a state. As a result, the transistor Q turned on_{twenty two}Through
Transistor Q_{twenty two}Drain potential is V _CCRise to the side
You.

The current flowing through the transistor Q _22, the transistor Q ₂₃ is turned off, the output OUT side becomes zero eventually if capacitive load. Therefore, this circuit has very few consuming electrodes unlike the conventional current mirror. Since the conventional circuit is a differential amplifier, one of the drive transistor for example Q ₄ in FIG. 2 is the other transistor Q ₃ also off turned on, Q ₇ toward the power supply V _CC to ground →
There is a through current via Q ₃ → Q ₁₁ . This consumes wasted power.

[0017] Now, (when k = 1) a current equal to the current I in the transistor Q ₂₂ flows, which charges the next stage of the input capacitor C _1. If the input capacitance C ₁ is thus completed discharged, the transistor Q ₂₂ current no longer flows. The current I flowing through the data bus DB is the sense amplifier SA
Is the current that drives the data bus, and an equal current charges the load capacitance C ₁ , and since the data bus parasitic capacitances C ₃ and C ₄ are generally much larger than the amplifier input capacitance C ₁ , If the change in the drain voltage of the transistor Q ₂₂ is fast with respect to the voltage change. For example, it is assumed that the capacitance C _{4 of the} data bus is 1 pF. Next stage capacitor C ₁ is approximately 0.07PF (assuming a gate oxide film thickness 10 nm, the gate size 1 [mu] m × 20 [mu] m as the next stage 14). Therefore a _{C 4 / C 1 = 14.3,} ( change in the output OUT) drain voltage variation of the transistor Q ₂₂ to the data bus changes at a rate of 14.3 times.

[0018] Of course, we'll change the gm ratio of the transistor Q ₂₁ and Q _22, since the current that is proportional to the gm ratio rather than the same current as the data bus flows through the Q _22, further multiplied by the gm ratio to capacity ratio of the The thing becomes the change of the output OUT. In this way, the present circuit also enables high-speed, large-amplitude operation.

This amplifier circuit is a current amplifier circuit using MOS transistors. An output current k times the input current i is generated. When k = 1, current amplification is not performed.
If input capacitance> output capacitance, a voltage gain is obtained.

FIG. 3 shows a second embodiment of the present invention. FIG.
In FIG. 3, a differential output is obtained, and a differential amplifier can be easily connected to the next stage. P-channel MOS transistor Q ₂₁ in this circuit is the current mirror configuration with the transistor Q ₂₂ and Q _27. Thus current proportional to the current flowing through the transistor Q ₂₁ flows through the transistor Q _22, Q _27.
The same applies to the relationship between the p-channel MOS transistors Q ₂₅ , Q ₂₄ and Q ₂₈ , and the current proportional to the current flowing through Q ₂₅ is Q _24
Flow to ₂₈ . Current of the transistor Q ₂₁ is a data bus DB
Is a current, the current of the transistor Q ₂₅ is a data bus D
BX current. DB and DBX are in a differential relationship, and Q
_22, since the current of Q ₂₈ is proportional to the current of Q _21, Q _25, Q
The currents at ₂₂ and Q ₂₄ are in a differential relationship, and so are the currents at Q ₂₇ and Q ₂₈ . Current mirror Q output of the Q ₂₂ and Q ₂₈
And ₂₃ and is received by Q ₂₆ Q ₂₈ side output (DBX side) OUT _2, since the output OUT ₁ to Q ₂₇ side (DB side), OU
T ₁ and OUT ₂ are differential outputs. Incidentally, Q ₃₁ to Q ₃₄ is a switch transistor for deactivating the circuit. This work is equivalent to Q ₁₁ in FIG. 2, it is sufficient to the phi _EN to a low level when even signal appears on the data bus is the circuit does not need to perform an amplifying operation. When φ _EN is at a high level, Q _{31 to} Q ₃₄ conduct, so that the circuit function follows the operation principle of FIG.

FIG. 4A shows a data bus signal amplifying circuit CSA (Current Sensing Amplifier) according to the present invention used in an experiment.
FIG. 4B shows a conventional data bus signal amplifier circuit VSA (Voltage Sensing Amplifier) used in the experiment.
Is shown. All circuits take out outputs via RS flip-flops. The conventional data bus signal amplifying circuit obtains a necessary gain by connecting two stages of data bus amplifiers 2 in series.

FIG. 5A shows the input / output delay time t _d in the configuration of FIGS. 4A and 4B. The data bus amplifier circuit CSA of the present invention always operates faster than the conventional circuit VSA.

FIG. 5B shows the relationship between the power supply voltage V _CC and the DC current flowing through the data bus amplifier circuits CSA and VSA in the standby mode (when no current flows on the data buses DB and DBX) and in the full sensing mode. Show the relationship. From FIG. 5B, in the standby mode, no current flows through the data bus amplifier circuit CSA of the present invention. On the other hand, in the conventional data bus amplifier circuit VSA, a certain amount of current always flows in the standby mode. This is shown in FIG.
This is because the transistors Q ₁ and Q _{2 shown} are on in the standby mode, and the gate-source voltages of the transistors Q _{3 to} Q ₆ are higher than the potentials of the data buses DB and DBX. On the other hand, the bias voltage of the transistor Q ₂₂ in the present invention is close to its threshold voltage.

Next, a semiconductor memory device according to a third embodiment of the present invention will be described with reference to FIG. The illustrated semiconductor memory device includes a memory cell array 31, a sense amplifier 3
2. Write gate 33, read gate 34, row decoder 35, column decoder 36, write amplifier 37, clock generator 38, RS flip-flop 39, latch circuit (output buffer) 40, inverter 41, timing generator 42, and data bus The signal amplification circuit 100 is provided. Row decoder 35 decodes the external address and outputs at least one
One word line WL is selected. The column decoder 36 decodes the external address and outputs at least one set of bit lines BL,
Select BLX. The sense amplifier 32 has a bit line BL,
The potential difference between the BLXs is amplified, one is pulled up in the V _CC direction, and the other is pulled down in the ground direction.

The read gate 34 has transistors 34a,
34b, 34c and 34d. Transistor 34
The gates of c and 34d are connected to a column selection line CL extending from the column decoder 36. As described later, the transistors 34c and 34d are turned on for a predetermined period in response to a column selection signal supplied via a selection line CL. The gates of transistors 34a and 34b are connected to data buses DB and D
BX and the source is transistor 34
c and 34d, respectively. The sources of the transistors 34c and 34d are grounded.

The data bus signal amplifying circuit 100 has the following
Except for this, it is the same as that of FIG. The difference is that the tiger
Transistor Q₃₅, Q₃₆Is V_CCWire and transistor Q_{twenty one}, Q_{twenty five}
And are provided between them. From inverter 41
Clock signal φ_EN1Is the transistor Q₃₅, Q₃₆No
Given to the party. The two complementary outputs of the amplifier circuit 100 are
Latched by the latch circuit 40 via the flip-flop 39
And read data D _OUTIs output as Transi
Star Q₆₄, Q₆₅Is OUT at reset₁, OUT_TwoNo electricity
It is provided for stabilizing the position.

The write amplifier 37 receives the input data D _IN and controls a write gate 33 having transistors 33a and 33b. That is, the write gate 33 drives the bit lines BL, BLX accordance write data D _in.
The clock generator 38 outputs a write enable signal WEX (X
Means a low active signal) and the above φ
_A clock signal φ _EN2 which is 180 ° out of phase with _EN1 is output. The clock signal φ _EN2 is transistor Q ₃₁ ~
It is applied to the gate of Q _34. The timing generator 42 receives a row address strobe signal RASX (X means a row active signal (RAS bar)) and a column address strobe signal CASX (same as above) from an external device, and generates various timing (clock) signals. For example, timing signals supplied to the sense amplifier 32, the row decoder 35, and the column decoder 36 are generated by the timing generator 42.

Next, the operation of the semiconductor memory device shown in FIG. 6 will be described with reference to the timing section of FIG. 7. The operation shown in FIG. 7 is a read modified write operation. The row address strobe signal RA falls, and the memory device fetches the address data applied to the address input pin into the chip as a row address at that time, and selects the word line WL by the operation of the row decoder 35. Word line WL at time t
Start to rise to ₁ . On the other hand, after a predetermined time elapses after the row address strobe signal RASX falls, an internal circuit is switched by a timer circuit (not shown) in the chip so that data on the address input pin is regarded as a column address. Thus the column address is taken into the column decoder 36, a column selecting line CL corresponding to this address is driven at time t _2. When the column selection transistors 34c and 34d conduct in this manner, the bit line B
34c, 3 by the memory cell output signal on L, BLX
4d are in a conductive state, so that the data buses DB and D
The potential of BX instantaneously drops. That is, the data bus D
A current flows through both B and DBX.

The signal amplifier circuit 100 of the present invention functions to amplify the difference current between the input terminals. Therefore, DB, DBX
Current flows with the transistor 34 from the amplifier 100 side.
a, even when the flow towards 34b, whereby the output terminal out ₁ if there is a slight difference, out ₂ of the voltage changes. In FIG. 7, the potential on the DB side drops more because "0" data is read. In other words, the internal resistance of the transistor 34b is lower than that of the transistor 34a (the gate voltage is relatively low). High) situation.

The sense amplifier to the time t ₃ is driven. Then, the potential of BL goes to ground, and BLX goes to V _CC .
When the potential of BL falls below the threshold value of the transistor 34a, the transistor 34a is cut off, and the current of the data bus connected to the transistor 34a stops flowing. Therefore, from time t _3, the voltage of data bus DBX is at the original level of V _CC −
V _TH (P) (V _CC is power supply voltage, V _TH (P) is PMOS
Threshold voltage).

[0031] The column select gate 34c at time t _4,
When 34d is turned off, the current on the data bus DB side stops flowing, so that the potential of DB goes to V _CC -V _TH (P).

The output current of the amplifier 100 is controlled according to the current difference of the data bus. The output voltage is not affected by the common mode current of the input terminal. However, when the common-mode current flows, current flows through all the transistors in the amplifier 100. Since the gain of the MOS transistor is larger when a certain amount of current flows, DB, DB,
The fact that current flows on both the DBX side is advantageous for speeding up.

Thereafter, the write enable signal WEX becomes active. In response to this, the clocks φ _EN1 , φ
_EN2 is inverted and the data bus signal amplifying circuit 100
Is deactivated. Also, the write enable signal WEX
Becomes active, the write amplifier 37 causes the bit line B via the write gate 33 _in accordance with the input data Din.
L and BLX are controlled. Thereafter, the write enable signal is turned off. At the same time, row address strobe signal RA
SX and the column address strobe signal CASX are also turned off. Then, the selected word line is released from the state, and the sense amplifier 32 is turned off.

The DRAM device having the data bus signal amplifier circuit 100 described above consumes higher speed and lower power consumption than the conventional device. In addition, since the data bus signal amplifying circuit 100 is miniaturized, the DRAM device can be miniaturized as compared with the conventional device. Further, by using the read gate 34 of FIG. 6, the size of the sense amplifier 32 can be reduced. Read gate 34 is connected to data buses DB, DBX and bit line BL,
Do not connect BLX directly. The configuration of the read gate 34 is as follows.
Different from the gate of Figure 1 including transistors Q _a, a Q _b (A). That is, the sense amplifier 32 in FIG. 6 does not need to drive the data buses DB and DBX. Sense amplifier 3
2 controls only the transistors 34c and 34d of the read gate 34. Therefore, the sense amplifier 32 can be configured with a transistor smaller than a conventional transistor.

FIG. 8 shows a first modification of the configuration of FIG. The data bus signal amplifying circuit 100A of FIG. 8 replaces the data bus signal amplifying circuit of FIG. The amplifier circuit 100A is obtained by removing the transistor Q ₃₁ to Q ₃₆ from the amplifier circuit 100 of FIG. 6. The amplification operation is the same. Instead of the transistor Q ₃₁ to Q _36, which is removal of these, the transistors Q _37, Q ₃₈ are provided. Transistor Q ₃₇ is provided in the data bus in the DB, the transistor Q ₃₈ is provided in the data bus in the DBX. The clock φ _EN1 is _supplied to the gates of the transistors Q ₃₇ and Q ₃₈ . When the write enable signal WEX is in an active state, the clock φ _EN1 is at a high level, and the data bus signal amplifying circuit 100A operates the data buses DB and DBX.
Disconnected from The configuration of FIG. 8 is simpler than the configuration of FIG.

FIG. 9 shows a second modification of the configuration shown in FIG.
The configuration of FIG. 9 is obtained by adding transistors Q ₃₉ and Q ₄₀ of the configuration of FIG. Drain and gate of the transistor Q ₃₉ is connected to the data bus DB, drain and gate of the transistor Q ₄₀ is connected to the data bus DBX.

FIG. 10A is used in the DRAM device of FIG.
Transistor Q_{twenty one}Drain voltage (V_D) Vs Dre
In current (I_D4) is a graph showing characteristics. Transis
TA Q _{twenty one}Bias point is V_CC-V_th(V_thIs Transis
TA Q_{twenty one}Threshold voltage). Data reading
Output voltage △ V_DBAppears between data buses DB and DBX
And the current ΔI_DIs transistor Q₂₇Flows to

[0038] FIG. 10 (B) is a diagram showing the V _D -I _D characteristic of the transistor Q ₂₁ that is used in the DRAM device shown in FIG. Bias point of the transistor Q ₂₁ by the action of a diode-connected transistor Q _39, V _CC -
It is at a potential lower than _Vth . Transistor Q ₃₇ current I ₁ in the off state is always flows through the transistor Q _21, Q _39. The bias point is in the steep part of the curve V _D -I _D characteristic. For the same data read voltage ΔV _DB between data buses DB and DBX, current _ID flows through transistors Q ₂₁ and Q ₃₉ . FIG. 10 (A), the as can be seen from a comparison of 10 (B), the current △ I _D in the case of FIG. 9 is greater than the current △ I _D in the case of FIG. 8. This means that the data bus signal amplifying circuit 100A
It means that it has a larger gain and operates at high speed.

Next, referring to FIG. 11, a fourth embodiment of the present invention will be described.
A data bus signal amplifier circuit according to an embodiment will be described. FIG.
The data bus signal amplifier circuit 100C shown in FIG.
Polar transistor Q₄₁, Q₄₂, Q₄₄, Q₄₅, Q₄₇as well as
Q₄₈Having. These bipolar transistors are
MOS transistor Q in the described embodiment_{twenty one}, Q_{twenty two},
Q _{twenty four}, Q_{twenty five}, Q₂₇And Q₂₈Is equivalent to Bipolar tiger
The emitter of the transistor is V_CCConnected to power line. Ba
Polar transistor Q₄₁The base and collector
It is connected to Tabus DB. Bipolar transistor
Q₄₂, Q₄₇Is connected to the data bus DB
You. Bipolar transistor Q₄₇The collector is a transi
Star Q₂₉Connected to the drain of a bipolar transistor
TA Q₄₂Is the transistor Q_{twenty three}Connect with the drain
Has been continued. Bipolar transistor Q₄₄, Q₄₅, Q
₄₈Is the bipolar transistor Q₄₁, Q₄₂, Q₄₇Same as
Connected.

[0040] FIG. 12 is a graph of the collector voltage (V _C) versus the collector current (I _C) characteristic of the bipolar transistor Q _41. The bipolar characteristic shown in FIG.
The rise is steeper than the OS characteristics. Therefore, for the same data read voltage, the change in current is large in the direction of the bipolar transistor. Therefore, the data bus amplifier circuit 10
0C is the data bus amplifier circuit 100, 100A, 1
It has a higher driving capability than 00B and is fast. This data bus amplifier circuit 100C can be used in place of the one described above. The configuration in FIG. 1A and the configuration in FIG. 3 can also be configured by bipolar transistors.

Next, referring to FIG. 13, a fifth embodiment of the present invention will be described.
A data bus signal amplifier circuit according to an embodiment will be described. FIG.
The data bus signal amplifier circuit 100D shown in FIG.
Amplifier circuit DT₁~ DT₆Having. Darlington Ann
Circuit DT₁Is the PMOS transistor Q_{twenty one}, Npn buy
Polar transistor Q₅₁And resistance R₁₁Having. PMO
S transistor Q_{twenty one}The drain of a bipolar transistor
TA Q₅₁And its collector is connected to V_CCPower line
It is connected to the. Resistance R₁₁Is a bipolar transistor
Q₅₁Is connected between the emitter and the collector. Bipo
Roller transistor Q₅₁Are connected to the data bus DB
Has been continued. PMOS transistor Q _{twenty one}Drain current
The flow is bipolar transistor Q₅₁And the data
Output to the DB.

As shown in FIG. 14, the Darlington amplifier circuit DT ₁ includes the npn transistor Q shown in FIG.
_It is equivalent to ₄₁ . The Darlington amplifier circuit DT ₁ has P
It has a higher gain than the MOS transistor Q _21. Therefore, by using the Darlington amplifier circuit, the size of the sense amplifier can be further reduced, and the operation speed can be further increased. Figure 15 is a cross-sectional view of the Darlington amplifier circuit DT _1.

Each of the Darlington amplifier circuits DT _{2 to} DT ₆ has the same configuration as the Darlington amplifier circuit DT ₁ .

The Darlington amplifier circuit DT ₁ forms one current mirror circuit with DT _2, and forms another current mirror circuit with DT ₃ . Likewise, Darlington amplifier circuit DT ₆ constitute two current mirror circuits in the DT ₄ and DT _5. The configuration of FIG. 1A or FIG. 3 may be configured by a Darlington amplifier circuit.

[0045]

As described above, since the present data bus signal amplifier circuit is configured to obtain an output current proportional to the input current, a current proportional to the current of the sense amplifier driving the data bus can be obtained. Conventionally, the data bus current was wasted power supply current through the load element, but this is not the case in the present invention. Further, in the circuit of the present invention, the amount of waste current that passes from the power supply to the ground after amplification is extremely small.

Therefore, by using the data bus signal amplifier circuit, a low power consumption, high speed, and small semiconductor memory device can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional data bus signal amplifier circuit.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing an experimental configuration for measuring characteristics of the present invention and a conventional configuration.

FIG. 5 is a graph showing experimental results.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a waveform chart showing the operation of the third embodiment.

FIG. 8 is a circuit diagram showing a first modification of the third embodiment.

FIG. 9 is a circuit diagram showing a second modification of the third embodiment.

FIG. 10 is a graph showing a difference in characteristics between the third embodiment and its second modification.

FIG. 11 is a circuit diagram showing a fourth embodiment of the present invention.

V _C -I _C of the transistor Q ₄₁ shown in FIG. 12 FIG. 11
It is a graph which shows a characteristic.

FIG. 13 is a circuit diagram showing a fifth embodiment of the present invention.

14 is a diagram showing a Darlington amplifier circuit shown in FIG.
It is a circuit diagram showing that it is equivalent to a transistor.

FIG. 15 is a sectional view of the Darlington amplifier circuit shown in FIG.

[Explanation of symbols]

11, 12 and 13 the current mirror circuit OUT, OUT _1, OUT ₂ output 31 memory cell array 32 sense amplifiers 33 write gate 34, line 35 decoder 36 column readout gate decoder 37 write amplifiers 38 clock generator 39 RS flip-flop 40 latch circuit 41 inverter 42 timing generator DT ₁ to DT ₆ Darlington amplifier

Claims (7)

(57) [Claims] 1. A first and a second terminal respectively connected to one and the other of a pair of complementary signal lines and each having two output terminals.
And a third and a fourth current mirror circuit for receiving the outputs of the first and second current mirror circuits, and a complementary output line from the third and fourth current mirror circuits. A signal amplifier circuit characterized in that the signal amplifier circuit is adapted to take out the signal. 2. The method according to claim 1, wherein the first and second current mirror circuits supply a current k times (k> 1) of a current flowing through one of the pair of complementary signal lines to the two output terminals. The signal amplification circuit according to claim 1. 3. The wiring capacity of the pair of complementary signal lines is larger than the wiring capacity of the complementary output line, and the first and second current mirror circuits are equal in current to one of the pair of complementary signal lines. wherein the amount of current 2
2. The signal amplification circuit according to claim 1, wherein the signal is supplied to two output terminals . 4. A transistor for shifting a bias point of the first and second current mirror circuits to a lower potential side between the complementary signal line and a lower potential power supply line. Item 2. The signal amplification circuit according to Item 1. 5. The signal amplification circuit according to claim 1, wherein each of the first and second current mirror circuits has a Darlington amplifier circuit in which a bipolar transistor and a field effect transistor are Darlington-connected. 6. A signal amplifying circuit according to claim 1, a bit line pair for exchanging information with a memory cell, a sense-up for amplifying a potential difference between the bit line pair, and a column. A semiconductor memory device comprising: coupling means for coupling the bit line pair and the complementary signal line in response to a selection signal. 7. The coupling means includes a pair of transistors that are activated in response to the column selection signal and receive a potential of the bit line pair at a gate thereof and amplify a potential difference between the bit line pair. The semiconductor memory device according to claim 6, wherein: