JP3153950B2 - Image compression encoding device and image compression decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image compression / encoding apparatus and an image compression / decoding apparatus which are suitable for use in a digital VTR, a wired or wireless transmission (broadcasting) system, etc., in consideration of error correction.

[0002]

2. Description of the Related Art A conventional image compression / encoding apparatus (see Japanese Patent Publication No. 1-200888) will be described below with reference to FIG. As shown in FIG. 3, a predetermined number of digital image signals (input digital image signals) composed of discrete pixel data sequentially arranged on the time axis are arranged in a matrix in the horizontal and vertical directions of the screen as shown in FIG. A plurality of block signals (main block signals) composed of arranged pixel data
To obtain a main block digital image signal. Here, the main block signal is composed of a predetermined number, for example, 8 × 8 pixel data in the horizontal direction and the vertical direction. FIG. 3 shows a part of the pixel data constituting the screen by circles. In order to distinguish adjacent pixel data, the pixel data is shown by alternate white circles and black circles in the horizontal and vertical directions. .

The main block digital image signal obtained by such time series conversion is supplied from an input terminal 32 to a division processing circuit 33, and each main block signal is divided into a plurality of sub-block signals by a sub-sample configuration. Thus, a sub-blocked digital image signal is obtained. As a method of the division processing by the division processing circuit 33, for example, three types of methods as shown in FIGS. 4 to 6 are possible. In the first division method, eight vertical pixel data columns (each column is composed of eight pixel data) constituting a main block signal composed of 8 × 8 pixel data in FIG. As shown in FIG. 4, a first sub-block signal composed of four odd-numbered columns (consisting of 4 × 8 pixel data in the horizontal and vertical directions) and a fourth sub-block signal composed of four even-numbered columns 2 sub-block signals (consisting of 4 × 8 pixel data in the horizontal and vertical directions).

In the second division method, the 8 × 8 in FIG.
As shown in FIG. 5, eight columns of pixel data in the vertical direction (each column is composed of eight pieces of pixel data) constituting a main block signal composed of four pieces of pixel data are divided into four odd-numbered pixels. A first sub-block signal composed of rows (comprising 4 × 8 pixel data in the horizontal and vertical directions) and a second sub-block signal composed of four even-numbered rows (8 × 8 pixel data in the horizontal and vertical directions) (Comprising four pixel data).

In the third division method, as shown in FIG. 6, 8 × 8 pixel data forming the main block in FIG. 3 are divided into four columns of four odd-numbered pixel data.
A first sub-block signal composed of odd-numbered pixel data (white circles) and a second sub-block signal composed of four odd-numbered pixel data (black circles) in four columns of even-numbered pixel data, respectively. A block signal, a third sub-block signal composed of four even-numbered pixel data (black circles) in each of the four odd-numbered pixel data columns, and a fourth sub-block signal in the four even-numbered pixel data columns It is divided into fourth sub-block signals each consisting of four even-numbered pixel data (white circles).

As described above, the division processing circuit 33
Each main block signal of the main block digital image signal is 2
The sub-blocked digital image signal obtained by being divided into one or four sub-block signals is supplied to an orthogonal transform circuit (two-dimensional discrete cosine transform circuit) 34, and the orthogonal transform process is performed for each main block described above. (Two-dimensional discrete cosine transform processing).

The transform coefficients from the orthogonal transform circuit 34 are supplied to a quantizing circuit (requantizing circuit) 35 where they are quantized (requantized), and then supplied to an encoder 36 for transmission at a predetermined transmission rate. After being modulated into a signal, the signal is supplied from an output terminal 37 to a transmission line.

According to this conventional example, a predetermined number of digital image signals composed of discrete pixel data sequentially arranged on the time axis are arranged in a matrix in the horizontal and vertical directions of the screen. After performing time series conversion so as to be subdivided into a plurality of blocks (main blocks) composed of pixel data, the pixel data constituting each main block is separated into pixel data adjacent in the horizontal or vertical direction, and the After dividing into two or four mutually adjacent sub-block signals composed of pixel data arranged in a matrix by a predetermined number in a horizontal direction and a vertical direction by a sub-sample configuration, orthogonal transformation is performed for each main block signal. Transmitting.

Therefore, even if a bit error occurs in the transmission path of the transmission signal, the transmission signal is subjected to inverse orthogonal transform,
When sub-sample inverse construction is performed, pixel data of a sub-block signal in which all pixel data has an error due to a bit error among two or four adjacent sub-blocks is replaced with pixel data of another adjacent sub-block signal. The error correction (error concealment) can be performed by using the same, and the original digital image signal can be easily restored.

[0010]

Generally, high-efficiency coding such as transform coding such as orthogonal transform and predictive coding has a large amplitude for low-frequency signal components having high sensitivity to human eyes. A digital image signal is encoded and image-compressed so that a transform coefficient (coding coefficient) is obtained and a transform coefficient (coding coefficient) having a small amplitude is obtained for a high-frequency signal component with low sensitivity. It is.

However, in the above-mentioned conventional example, prior to orthogonally transforming the digital image signal, each main block signal of the main blocked digital image signal is converted into a pixel constituting each main block signal of the main blocked digital image signal. The data is separated into pixel data adjacent to each other in the horizontal or vertical direction, and is divided into a plurality of sub-block signals each including a predetermined number of pixel data arranged in a matrix in the horizontal and vertical directions of the screen. However, this will not be fixed again, and the correlation between adjacent pixel data of the blocked digital image signal will be intentionally broken. Therefore, when the sub-blocked digital image signal is orthogonally transformed for each main block signal, a sub-sample configuration is obtained. Low frequency concentration of transform coefficients (coding coefficients) obtained by orthogonal transform compared to orthogonal transform without Reduced, i.e., because the conversion efficiency is reduced, the image quality of the reconstructed digital image signal is lowered.

In view of the above, the present invention converts an input digital image signal into a plurality of main block signals each composed of pixel data arranged in a matrix in a predetermined number in each of the horizontal and vertical directions of the screen. In an image compression encoding apparatus configured to perform image compression encoding on a main block digital image signal obtained by subdivision, a bit error occurs in the image compression encoded signal on a transmission path, and all of the main block signals are configured. Even if the pixel data of error becomes, the original input digital image signal can be restored, and
In particular, when the frame correlation of a main block signal of a main block digital image signal to be subjected to image compression encoding is high, an image compression encoding apparatus capable of avoiding a decrease in compression efficiency and an image compression encoding apparatus thereof The original digital image signal can be restored by compressing and decoding the main block digital image signal subjected to image compression encoding, and the frame correlation of the main block signal of the main block digital image signal subjected to image compression encoding is obtained. When it is high, an image compression / decoding device capable of avoiding a decrease in compression efficiency is proposed.

[0013]

According to a first aspect of the present invention, an input digital image signal is divided into a plurality of pixels each consisting of a plurality of pixel data arranged in a matrix in the horizontal and vertical directions of the screen. Subdivided into main block signals,
Time series conversion circuit 2 for obtaining a main block digital image signal
And the pixel data constituting each main block signal of the main block digital image signal from the time series conversion circuit 2 are separated into pixel data adjacent to each other in the horizontal or vertical direction, and are respectively separated in the horizontal and vertical directions of the screen. A sub-sampling circuit 5 for dividing the image data into a plurality of sub-block signals each consisting of a predetermined number of pixel data arranged in a matrix to obtain a sub-blocked digital image signal; A frame correlation (or field correlation) discriminating circuit FC for discriminating the presence or absence of a frame correlation (or field correlation) and a result of discriminating the presence or absence of a frame correlation (or field correlation) by the frame correlation (or field correlation) discriminating circuit FC. When there is a frame correlation (or a field correlation), a time series conversion circuit Select more of the main block signal,
When there is no frame correlation (or field correlation), a selection means 7 for selecting a sub-block signal from the sub-sampling circuit 5 corresponding to the main block signal to obtain a blocked image signal; An image compression encoding circuit 9 for obtaining an image compression encoded signal by image compression encoding a block digital image signal, and performing error correction encoding on the image compression encoded signal from the image compression encoding circuit 9 to perform error correction. An image compression encoding apparatus comprising: an error correction encoding circuit that obtains an encoded signal.

According to a second aspect of the present invention, the input digital image signal is subdivided into a plurality of main block signals each consisting of pixel data arranged in a matrix in a predetermined number in the horizontal and vertical directions of the screen. The main block signal of the obtained main blocked digital image signal and the pixel data constituting each main block signal of the main blocked digital image signal are separated into pixel data adjacent to each other in the horizontal or vertical direction, and the screen Of the sub-block signals of the sub-blocked digital image signal obtained by dividing into a plurality of sub-block signals composed of pixel data arranged in a matrix by a predetermined number in the horizontal direction and the vertical direction, When there is a frame correlation (or field correlation), the main block signal is selected, and the frame correlation (or field correlation) is selected. When there is no (correlation), a sub-block signal corresponding to the main block signal is selected and error-correction-encoded and image-compression-encoded signal of the block digital image signal is supplied and error-corrected. An error correction circuit 17 for adding an error flag to an error that cannot be corrected by the error correction, and an image compression / decoding circuit for supplying an image compression / encoding signal from the error correction circuit 17 to obtain a block digital image signal 16 and the error of the main block signal in the blocked digital image signal from the image compression / decoding circuit 16 which could not be corrected by the error correction circuit 17 is represented by the corresponding main block signal one frame (or one field) before. A first error correction circuit FC for error correction using
The error correction of the error of the sub-block signal in the block digital image signal from the image compression / decoding circuit 16 which could not be corrected by the error correction circuit 17 is performed using the adjacent sub-block signal corresponding to the sub-block signal. 2 error correction circuit 23 and its second error correction circuit 23
The sub-sample inverse configuration circuit 23 that sub-samples the error-corrected sub-block signal to obtain the original main block signal, and the main block from the first error correction circuit FC and the sub-sample inverse configuration circuit 23 A time-series inverse transform circuit for returning a block digital image signal composed of a synthesized signal to an original input digital image signal.

According to a third aspect of the present invention, in the first aspect,
A shuffling circuit 8 for shuffling the block digital image signal from the selecting means 7 in units of blocks.
Is provided between the selection means 7 and the image compression / encoding circuit 9 in the image compression / encoding apparatus.

According to a fourth aspect of the present invention, in the second aspect,
The block digital image signal of the error correction coding / image compression coding signal is shuffled in units of blocks, and the block digital image signal shuffled in units of blocks from the image compression / decoding circuit 16 is deshuffled. An image compression decoding apparatus characterized in that a deshuffling circuit 22 is provided between the image compression decoding circuit 16 and the first and second error correction circuits 23.

According to a fifth aspect of the present invention, in the first or third aspect of the present invention, the image compression encoding circuit 9 comprises a high-efficiency encoder 10
An image compression encoding apparatus characterized by including:

According to a sixth aspect of the present invention, in the second or fourth aspect of the present invention, the image compression / decoding circuit 16 comprises the high-efficiency decoder 2
1 is an image compression encoding apparatus characterized by including:

According to a seventh aspect of the present invention, in the fifth aspect,
The image compression encoding circuit 9 is an image compression encoding device including a variable length encoder 12.

According to an eighth aspect of the present invention, in the sixth aspect of the present invention,
The image compression / decoding circuit 16 is an image compression / encoding device characterized by including a variable length decoder 19.

[0021]

According to the first aspect of the present invention, an input digital image signal is supplied to the time-series conversion circuit 2 and a predetermined number of pixels are arranged in a matrix in the horizontal and vertical directions of the screen for each screen. It is divided into a plurality of main block signals composed of data to obtain a main block digital image signal. The main block digital image signal is supplied to the sub-sampling circuit 5, and the pixel data forming each main block signal is separated into pixel data adjacent to each other in the horizontal or vertical direction. The image data is divided into a plurality of sub-block signals each composed of pixel data arranged in a matrix in a predetermined number in the vertical direction to obtain a sub-blocked digital image signal. The presence / absence of frame correlation for each main block signal of the main block image signal is determined by the frame correlation determination circuit FC, and the selection means 6 is controlled based on the determination result of the presence / absence of frame correlation. When there is a frame correlation, the main block signal from the time series conversion circuit 2 is selected, and when there is no frame correlation, the sub-block signal corresponding to the main block signal from the sub-sample configuration circuit 5 is selected. A block image signal (main block signal or sub-block diagram) by the selection means 6
Is obtained. The block digital image signal from the selection means 7 is supplied to an image compression / encoding circuit 9 and subjected to image compression / encoding to obtain an image compression / encoded signal. The image compression encoded signal from the image compression encoding circuit 9 is supplied to an error correction encoding circuit 14 to perform error correction encoding to obtain an error correction encoded signal.

According to the second aspect of the present invention, the input digital image signal is converted into a plurality of main block signals each consisting of a predetermined number of pixel data arranged in a matrix in the horizontal and vertical directions of the screen. The main block signal of the main block digital image signal obtained by subdivision and the pixel data constituting each main block signal of the main block digital image signal are separated into pixel data adjacent to each other in the horizontal or vertical direction. Of the sub-block signals of the sub-blocked digital image signal obtained by dividing into a plurality of sub-block signals composed of pixel data arranged in a matrix by a predetermined number in the horizontal direction and the vertical direction of the screen, respectively, If the signal has a frame correlation, the main block signal is selected, and if there is no frame correlation, the main block signal is selected. The error correction coding and image compression coding signals of the sub-block signal is selected by the configured blocked digital image signal corresponding to the item, the error correction circuit 1
7 and corrects the error, and attaches an error flag to the error that could not be corrected by the error correction. The image compression / encoding signal from the error correction circuit 17 is supplied to the image compression / decoding circuit 16 to obtain a block digital image signal. The image compression / decoding circuit 16
The error of the main block signal in the blocked digital image signal, which could not be corrected by the error correction circuit 17, is corrected by the first error correction circuit FC to the corresponding main block signal one frame (or one field) before. Error correction using An error of the sub-block signal in the blocked digital image signal from the image compression / decoding circuit 16 which could not be corrected by the error correction circuit 17 is corrected by a second error using an adjacent sub-block signal corresponding to the sub-block signal. Error correction is performed by the correction circuit 23. The error-corrected sub-block signal from the second error correction circuit 23 is supplied to the sub-sample inverse configuration circuit 23, where the sub-sample is inverse-configured to obtain the original main block signal. First error correction circuit FC and sub-sample inverse configuration circuit 2
3 to the time-series inverse conversion circuit 28,
Return to the original input digital image signal.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a camera-integrated digital VTR will be described below with reference to FIG. First, an image compression encoding apparatus (provided in a recording system of a camera-integrated digital VTR) according to an embodiment will be described with reference to FIG. The analog image signal is supplied from the input terminal Tin to the A / D converter 1 and A / D converted (quantized).
A digital image signal consisting of a plurality of discrete pixel data sequentially arranged on the time axis is obtained.

The digital image signal from the A / D converter 1 is supplied to the time-series conversion circuit 2 and, as in the case of the above-described conventional example, for each screen, as shown in FIG. Time-series conversion is performed so as to be subdivided into a plurality of block signals (main block signals) composed of pixel data arranged in a matrix of a predetermined number, for example, 8 × 8 in the vertical direction,
Obtain the main blocked digital image signal. FIG. 3 shows pixel data constituting a screen by circles. In order to distinguish adjacent pixel data, every other pixel data in the horizontal and vertical directions is represented by white circles and black circles.

The main block digital image signal from the time series conversion circuit 2 is supplied to a sub-sample configuration circuit 5,
A sub-sampled digital image signal is obtained by performing the same sub-sampling configuration processing as the above-described conventional division processing. That is, as the method of the sub-sample configuration processing by the sub-sample configuration circuit 5, for example, three methods as shown in FIGS. In the first processing method, eight vertical pixel data columns (each column is composed of eight pixel data) constituting a main block signal composed of 8 × 8 pixel data in FIG. As shown in FIG. 4, a first sub-block signal consisting of four odd-numbered columns (4 × 8 in the horizontal and vertical directions)
Pixel data) and a second sub-block signal (4 × 8 in the horizontal and vertical directions) composed of four even-numbered columns.
(Comprising pixel data).

In the second processing method, the 8 × 8 in FIG.
As shown in FIG. 5, eight columns of pixel data in the vertical direction (each column is composed of eight pieces of pixel data) constituting a main block signal composed of four pieces of pixel data are divided into four odd-numbered pixels. A first sub-block signal composed of rows (comprising 4 × 8 pixel data in the horizontal and vertical directions) and a second sub-block signal composed of four even-numbered rows (8 × 8 pixel data in the horizontal and vertical directions) (Comprising four pixel data).

In the third processing method, as shown in FIG. 6, the 8 × 8 pixel data constituting the main block signal in FIG. 3 is divided into four of the four odd-numbered pixel data columns. A first sub-block signal composed of odd-numbered pixel data (white circles), and a second sub-block composed of four odd-numbered pixel data (black circles) in four columns of even-numbered pixel data Signal, a third sub-block signal composed of four even-numbered pixel data (black circles) in each of the four odd-numbered pixel data columns, and each of the four even-numbered pixel data columns It is divided into a fourth sub-block signal composed of four even-numbered pixel data (white circles).

A sub-blocked digital image signal obtained by subjecting the main block signal from the sub-sampling circuit 5 to sub-sampling into two or four sub-block signals, and a time-series converted main block from the time-series conversion circuit 2 The converted digital image signal is switched by the changeover switch 6 and supplied to the shuffling circuit 8.

Next, the frame correlation discriminating circuit FC for controlling the switching of the changeover switch 6 will be described. The main-blocked digital image signal from the time-series conversion circuit 2 and the delayed main-blocked digital image signal obtained by delaying the digital image signal by one frame period by the one-frame delay unit 3 are supplied to the absolute difference calculating circuit 4. Then, after the difference absolute value for each pixel data is calculated, the calculated difference absolute value is supplied to the integrator 8, and integration (arithmetic average or load average) for each main block signal is performed. By comparing the integrated value with the reference value, a determination signal for the presence or absence of the frame correlation for each main block signal is obtained.

Then, the changeover switch 6 is switched by the discrimination signal from the frame correlation discriminating circuit FC, and when it is discriminated that there is a frame correlation, the switch is made to the time series conversion circuit 2 to select and output the main block signal. When it is determined that the main block signal has no frame correlation, the changeover switch 6 is switched to the sub-sampling circuit 5 to select a sub-block signal corresponding to the main block signal. By the synthesis of
Obtain a blocked digital image signal.

The block digital image signal from the changeover switch 6 is supplied to a shuffling circuit 8 where shuffling is performed for each block (main block and sub-block), and then the image is compressed and encoded. 9 to be subjected to image compression encoding.

Next, the image compression / encoding circuit 9 will be described. The shuffled digital image signal from the shuffling circuit 8 is supplied to a two-dimensional discrete cosine transform circuit (two-dimensional DCT circuit) 10 for every main block signal composed of 8.times.8 pixel data data or for two or more main block signals. Transform coding is performed for each 8 × 8 pixel data data composed of one or four sub-block signals, and transform coefficient data is output. N × N pixel data in the horizontal and vertical directions of the main block signal of the digital image signal or N × in the horizontal and vertical directions composed of two or four sub-block signals
The transform coefficient data of the two-dimensional discrete cosine transform in the case where the pixel data is composed of N pieces of pixel data is represented by Expression (1-1) of Expression 1. The expression (1-3) is a proviso expression.

[0033]

(Equation 1)

The transform coefficient data from the two-dimensional DCT circuit 10 is supplied to a quantization circuit (requantization circuit) 11,
After being quantized (re-quantized), the quantized transform coefficient data is stored in a variable length coding circuit (VLC coding circuit) 12.
And is subjected to variable-length encoding. The quantization level in the quantization circuit 11 is controlled by the code amount controller 15 such that the higher the transform coefficient of the band, the smaller the quantization level. This code amount controller 15 is controlled by the VLC encoding circuit 15. The reference value of the integrator 7 of the frame correlation discriminating circuit FC is controlled by the code amount controller 15.

The VLC-encoded transform coefficient data from the VLC encoding circuit 12 is supplied to a packing circuit (buffering circuit) 13 where, for example, a 10 DCT block (conversion coefficient data for 8 × 8 pixel data is 1
The data amount is adjusted so that the coefficient data amount becomes constant in the DCT block), and the code amount controller 15 selects the quantization level table selection information data for each of the 10 DCT blocks, the integrator 8 After the additional block configuration selection information data (different information data of the main block and the sub-block based on the presence / absence of frame correlation) and the like are supplied to the transmission unit 14.

The transmission section 14 includes an error correction encoding circuit, a modulation circuit, and the like, and outputs the VL output from the packing circuit 13.
The C-encoded transform coefficient data is error-correction-encoded by the error-correction encoding circuit 14, and the error-correction-encoded and VLC-encoded transform coefficient data is 10D.
The modulation information is modulated together with the selection information data of the quantization level table for each CT block, the block configuration selection information data, and the like by a modulation method suitable for the transmission path (magnetic head-magnetic tape system-magnetic head) and suitable for the transmission path. Is output to the transmission line at the specified transmission rate.

Next, an image compression / decoding apparatus (provided in a reproduction system of a digital VTR) according to the embodiment will be described with reference to FIG. The transmission path (magnetic head-magnetic tape system) is transmitted by the transmission unit 14 of the image compression encoding apparatus of FIG.
Modulated error correction encoding transmitted to the magnetic head)
The LC coded transform coefficient data, the modulated signal of the selection information data of the quantization table for each 10 DCT block, the modulated signal of the block configuration selection information data, and the like are supplied from the transmission path to the reception unit 17 and demodulated. The error correction coding and VL obtained by demodulation
The C-coded transform coefficient data is error-corrected, and the error-corrected VLC-coded transform coefficient data, the VLC-coded transform coefficient error data for which the error could not be corrected, the error flag attached thereto, and the quantum for each 10 DCT block. The selection information data of the conversion table, the block configuration selection information data, and the like are supplied to the depacking circuit 18.

In the depacking circuit 18, based on the output data from the receiving unit 17, error-corrected VLC coded transform coefficient data, VLC coded transform coefficient error data, error flags, and information for selecting a quantization table for each 10DCT block. Data, block configuration selection information data, and the like are separated. The error-corrected VLC encoded transform coefficient data and the VLC encoded transform coefficient error data are supplied to a variable length decoding circuit (VLC decoding circuit) 19, and the error flag is supplied to an error correction control circuit 25. The block configuration selection information data is supplied as block configuration switching information data to a changeover switch 24 and a two-dimensional discrete cosine inverse transform circuit (IDCT circuit) 21, which will be described later.
The selection information data of the quantization table is supplied to an inverse quantization circuit 20 described later.

The error-corrected transform coefficient data and the transform coefficient error data from the VLC decoding circuit 19 are supplied to an inverse quantization circuit 20, where they are inversely quantized based on selection information data of a quantization table. , And supplied to a two-dimensional discrete cosine inverse transform circuit (two-dimensional IDCT circuit) 21.

In the two-dimensional IDCT circuit 21, the transform coefficient data is inversely transformed in accordance with the equation (1-2) based on the block configuration switching information (for the main block signal and the sub-block signal) to form a block. A digital image signal is obtained and supplied to the deshuffling circuit 22.
Deshuffling is performed in block units.

Of the de-shuffled blocked digital image signals from the de-shuffling circuit 22, two or four sub-block signals adjacent to each other are supplied to an error correction / sub-sample inverse configuration circuit 23, and an error correction control circuit is provided. Under the control of 25, error correction is performed on the erroneous pixel data of the sub-block signal, and the sub-block signal is subjected to an inverse sampling process and returned to the main block signal. In this case, the error correction is performed by the adjacent pixel data. However, of the two or four adjacent sub-blocks due to the bit error in the transmission path, the pixel data of the sub-block in which all the pixel data has an error due to the bit error Is error-corrected using the pixel data of another adjacent sub-block.

Error correction / subsample inverse configuration circuit 23
After the error-corrected main block signal and the error-corrected main block signal and the error-free main block signal from the deshuffling circuit 22 are switched by the changeover switch 24 controlled by the block configuration switching information data, It is supplied to an error correction circuit EC.

When the output of the deshuffling circuit 22 is a sub-block signal, the changeover switch 24 outputs an error-corrected main block signal from the error correcting / sub-sampling inverse configuration circuit 23, and outputs the main block signal. Are switched to output the error-corrected main block signal and the error-free main block signal.

The error correction circuit EC comprises a changeover switch 27 controlled by a one-frame delay unit 26 and an error correction control circuit 25. One fixed contact of the changeover switch 27 is supplied with a changeover output from the changeover switch 24. The output from the movable contact of the changeover switch 24 is 1
The output is supplied to the frame delay unit 26, and the output from the one-frame delay unit 26 is supplied to the other fixed contact of the changeover switch 27. In this case, when there is an error in the pixel data of the main block signal from the changeover switch 24, the movable contact of the changeover switch 27 is switched to the one-frame delay unit 26 side, and the main block signal including the erroneous image data is switched. The error is corrected by the main block signal image data one frame before, and when there is no error in the pixel data of the main block signal from the changeover switch 24, the movable contact of the changeover switch 6 is switched to the changeover switch 24 side. The main block signal simply passes through the changeover switch 27.

The error-corrected main block digital image signal from the error correction circuit EC is applied to the time-series inverse conversion circuit 2.
8 and is inversely converted into a digital image signal composed of a plurality of pixel data sequentially arranged on the time axis. This digital image signal is supplied to a D / A converter 29 and converted into an analog signal. The analog image signal is output to the output terminal Tout.

According to the above-mentioned image compression code conversion apparatus, when there is no frame correlation in the main block signal of the main block digital image signal, the main block digital image signal is corrected for error in the image compression decoding apparatus. The main block signal is divided into pixel data constituting each main block signal of the main blocked digital image signal into pixel data adjacent to each other in the horizontal or vertical direction. After dividing into a plurality of sub-block signals composed of pixel data arranged in a matrix by number, the plurality of sub-block signals are supplied to the two-dimensional DCT 10 and subjected to two-dimensional discrete cosine transform. Therefore, in this case, the correlation between adjacent pixel data of the blocked digital image signal is intentionally broken, so that the conversion coefficient (code Of the block digital image signal restored by performing the two-dimensional discrete inverse cosine transform in the two-dimensional IDC circuit 21 of the image compression / decoding device because the low-frequency concentration degree of the conversion coefficient decreases, that is, the conversion efficiency decreases. Drops.

According to the above-described image compression / code conversion apparatus, when the main block signal of the main block digital image signal has a frame correlation, the image compression / decoding apparatus performs 1
Since error correction can be performed using the corresponding main block signal before the frame, the main block signal is directly subjected to two-dimensional DCT.
The signal is supplied to the circuit 10 and subjected to discrete cosine transform.
In this case, since the correlation between adjacent pixel data of the blocked digital image signal is not intentionally broken, the low-frequency concentration of the transform coefficient (coding coefficient) obtained by the orthogonal transform does not decrease. Since the conversion efficiency does not decrease, the image quality does not decrease in the block digital image signal restored by performing the two-dimensional discrete inverse cosine transform in the two-dimensional IDC circuit 21 of the image compression / decoding device.

The frame correlation discriminating circuit FC of the embodiment described above.
May be a field correlation discriminating circuit, and accordingly,
When there is an error in the main block signal, the error correction circuit EC is changed to a circuit that corrects the error using the corresponding main block signal one field before.

The circuit 10 of the image compression encoding apparatus of the above embodiment is not limited to a discrete cosine transform circuit.
Any high-efficiency coding circuit such as a transform coding circuit such as an orthogonal transform circuit, a predictive coding circuit, a vector quantization circuit, or an entropy coding circuit may be used. A highly efficient decoding circuit such as a transform decoding circuit such as an inverse transform circuit, a predictive decoding circuit, a vector inverse quantization circuit, and an entropy decoding circuit is used.

According to the first apparatus (image compression coding apparatus) of the embodiment, the input digital image signal is divided into a predetermined number of pixels arranged in a matrix in the horizontal and vertical directions of the screen for each screen. A time-series conversion circuit 2 that divides the data into a plurality of main block signals composed of data to obtain a main-blocked digital image signal, and pixels that constitute each main block signal of the main-blocked digital image signal from the time-series conversion circuit 2 Separating the data into pixel data adjacent to each other in the horizontal or vertical direction, dividing the data into a plurality of sub-block signals composed of pixel data arranged in a matrix in a predetermined number in the horizontal direction and in the vertical direction on the screen, A sub-sampling circuit 5 for obtaining a sub-blocked digital image signal, and a frame correlation for each main block signal of the main blocked image signal Or frame correlation (or field correlation to determine the presence or absence of a field correlation)) discriminating circuit F
If there is a frame correlation (or a field correlation) based on C and the result of the determination of the presence or absence of the frame correlation (or a field correlation) by the frame correlation (or a field correlation) determination circuit FC, the time series conversion circuit 2 When the main block signal is selected and there is no frame correlation (or field correlation), a selection means 7 for selecting a sub-block signal from the sub-sample configuration circuit 5 corresponding to the main block signal and obtaining a blocked image signal is provided. , Its selection means 7
Image compression coding circuit 9 for obtaining the image compression coded signal by performing image compression coding on the blocked digital image signal
And an error correction coding circuit 14 for obtaining an error correction coded signal by performing error correction coding on the image compression coded signal from the image compression coding circuit 9. can get.

That is, a main block obtained by subdividing an input digital image signal into a plurality of main block signals composed of pixel data arranged in a matrix of a predetermined number in each of the horizontal and vertical directions of the screen for each screen. In an image compression encoding apparatus that performs image compression encoding of a digitalized image signal, a bit error occurs in the image compression encoded signal on a transmission path, and all pixel data constituting the main block signal becomes an error. In addition, the original input digital image signal can be restored, and especially when the frame correlation (or field correlation) of the main block signal of the main block digital image signal to be image-compressed and encoded is high, the compression is performed. It is possible to obtain an image compression encoding device capable of avoiding a decrease in efficiency.

According to the second apparatus (image compression / decoding apparatus) of the embodiment, the input digital image signals are arranged in a predetermined number of pixels in a matrix in the horizontal and vertical directions of the screen for each screen. The main block signal of the main block digital image signal obtained by being divided into a plurality of main block signals composed of data, and the pixel data constituting each main block signal of the main block digital image signal in the horizontal or vertical direction. A sub-blocked digital image signal obtained by dividing into pixel data adjacent to each other and dividing it into a plurality of sub-block signals composed of pixel data arranged in a matrix in a predetermined number in the horizontal and vertical directions of the screen. When the main block signal has a frame correlation (or a field correlation) among the sub-block signals, the main block signal When there is no frame correlation (or field correlation) selected, a sub-block signal corresponding to the main block signal is selected to supply an error correction encoding / image compression encoding signal of a block digital image signal formed. And an error correction circuit 17 for adding an error flag to an error that could not be corrected by the error correction.
7, an image compression / decoding circuit 16 for obtaining a blocked digital image signal by supplying an image compression / encoding signal from the computer 7, and an error correction of a main block signal in the blocked digital image signal from the image compression / decoding circuit 16. A first error correction circuit EC for correcting an error that could not be corrected by the circuit 17 using a corresponding main block signal one frame (or one field) before, and a block from the image compression / decoding circuit 16 A second error correction circuit 2 for correcting an error of the sub-block signal in the digital image signal, which could not be corrected by the error correction circuit 17, by using an adjacent sub-block signal corresponding to the sub-block signal;
3, a sub-sample inverse-configuration circuit 23 that sub-samples the error-corrected sub-block signal from the second error-correction circuit 23 to obtain an original main block signal;
A time series inverse conversion circuit 28 for returning the block digital image signal composed of the synthesized signal of the main block signal from the first error correction circuit EC and the sub-sample inverse configuration circuit 23 to the original input digital image signal. The effect of is obtained.

In other words, the original digital image signal can be restored by compressing and decoding the main block digital image signal that has been image-compressed and encoded by the image compression-encoding device, and the main block image that has been image-compressed and encoded can be restored. When the frame correlation (or field correlation) of the main block signal of the digital image signal is high, it is possible to obtain an image compression / decoding device that can avoid a decrease in compression efficiency.

According to the third apparatus (image compression encoding apparatus) of the embodiment, in the first apparatus of the embodiment, the shuffling of the blocked digital image signal from the selecting means 6 is performed in units of blocks. Since the ring circuit 8 is provided between the selection means 6 and the image compression / encoding circuit 9, in addition to the effect of the first device of the embodiment, the ring circuit 8 is divided from the main block signal by the occurrence of a bit error in the transmission path. There is no possibility that all of the pixel data constituting each of the plurality of adjacent sub-block signals becomes an error, and it becomes impossible to restore the pixel data belonging to the main block signal.

According to the fourth device (image compression / decoding device) of the embodiment, in the second device of the embodiment, the error correction coding / blocking digital image signal of the image compression / coding signal is in units of blocks. A deshuffling circuit 22 for deshuffling a block digital image signal shuffled in units of blocks from the image compression / decoding circuit 16 is provided with an image compression / decoding circuit 16 and first and second Error correction circuit 23
In addition to the effects of the second device of the embodiment, the pixel constituting each of a plurality of adjacent sub-block signals divided from the main block signal due to the occurrence of a bit error in the transmission path is provided. There is no possibility that all the data will be in error and the restoration of the pixel data belonging to the main block signal becomes impossible.

According to the fifth apparatus (image compression encoding apparatus) of the embodiment, in the first or third apparatus of the embodiment,
Since the image compression encoding circuit 9 includes the high efficiency encoder 10, in addition to the effects of the first or third device of the embodiment, the compression efficiency of the digital image signal is extremely increased.

According to the sixth apparatus (image compression / decoding apparatus) of the embodiment, in the second or fourth apparatus of the embodiment,
Since the image compression / decoding circuit 16 includes the high-efficiency decoder 21, in addition to the effect of the second or fourth device of the embodiment, it is possible to reliably restore a digital image signal compressed with high compression efficiency. it can.

According to the seventh apparatus (image compression encoding apparatus) of the embodiment, in the fifth apparatus of the embodiment, since the image compression encoding circuit 9 includes the variable length encoder 12,
In addition to the effects of the device described above, the compression efficiency of the digital image signal is further increased.

According to the eighth apparatus (image compression / decoding apparatus) of the embodiment, in the sixth apparatus of the embodiment, the image compression / decoding circuit 16 includes the variable length decoder 19, In addition to the effect of the sixth device, the digital image signal compressed with higher compression efficiency can be reliably restored.

[0060]

According to the first aspect of the present invention, a predetermined number of input digital image signals are arranged in a matrix in the horizontal and vertical directions of the screen for each screen. A time-series conversion circuit that obtains a main blocked digital image signal by subdividing the main block signal into a plurality of main block signals, and horizontally converts pixel data constituting each main block signal of the main blocked digital image signal from the time series conversion circuit. Alternatively, the image data is divided into pixel data adjacent to each other in the vertical direction, and divided into a plurality of sub-block signals each including a predetermined number of pixel data arranged in a matrix in the horizontal direction and the vertical direction of the screen, and divided into sub-blocks. A sub-sampling circuit for obtaining a digital image signal; and a frame correlation (or field) for each main block signal of the main blocked image signal. Frame correlation (or field correlation) determining circuit for determining the presence or absence of frame correlation (or field correlation) based on the determination result of the presence or absence of frame correlation (or field correlation) by the frame correlation (or field correlation) determining circuit. When there is a field correlation), the main block signal from the time series conversion circuit is selected. When there is no frame correlation (or field correlation), the sub-block signal from the sub-sampling circuit corresponding to the main block signal is selected. Selection means for selecting and obtaining a blocked image signal, image compression coding circuit for obtaining an image compression coded signal by image compression coding the blocked digital image signal from the selection means, and image compression coding circuit for the same Error-correction encoding circuit to obtain an error-correction encoded signal by performing error-correction encoding on the Since having the bets, the following effects can be obtained.

That is, a main block obtained by subdividing an input digital image signal into a plurality of main block signals each consisting of pixel data arranged in a matrix in a predetermined number in the horizontal and vertical directions of the screen for each screen. In an image compression encoding apparatus that performs image compression encoding of a digitalized image signal, a bit error occurs in the image compression encoded signal on a transmission path, and all pixel data constituting the main block signal becomes an error. In addition, the original input digital image signal can be restored, and especially when the frame correlation (or field correlation) of the main block signal of the main block digital image signal to be image-compressed and encoded is high, the compression is performed. It is possible to obtain an image compression encoding device capable of avoiding a decrease in efficiency.

According to the image compression / decoding device of the second aspect of the present invention, the input digital image signal is composed of a predetermined number of pixel data arranged in a matrix in the horizontal and vertical directions of the screen for each screen. The main block signal of the main blocked digital image signal obtained by being divided into a plurality of main block signals and the pixel data forming each main block signal of the main blocked digital image signal are adjacent to each other in the horizontal or vertical direction. Separated into pixel data,
Among the sub-block signals of the sub-blocked digital image signal obtained by dividing into a plurality of sub-block signals composed of pixel data arranged in a matrix by a predetermined number in each of the horizontal direction and the vertical direction of the screen, the main block signal When there is a frame correlation (or field correlation), the main block signal is selected, and when there is no frame correlation (or field correlation), a sub-block signal corresponding to the main block signal is selected to form a block. An error correction circuit that supplies an error correction coding / image compression coding signal of a digital image signal and corrects the error, and adds an error flag to an error that cannot be corrected by the error correction. Image compression / decoding that supplies an image compression / encoding signal to obtain a block digital image signal Path and an error that cannot be corrected by the error correction circuit of the main block signal in the blocked digital image signal from the image compression / decoding circuit using the corresponding main block signal one field before. An error correction circuit of No. 1 and an error that cannot be corrected by the error correction circuit of the sub-block signal in the blocked digital image signal from the image compression / decoding circuit are determined by using an adjacent sub-block signal corresponding to the sub-block signal. A second error correction circuit for performing error correction by sub-sampling; a sub-sample inverse configuration circuit for sub-sample inversely configuring the error-corrected sub-block signal from the second error correction circuit to obtain an original main block signal; Blocked digital image composed of a composite signal of the main block signal from the first error correction circuit and the sub-sample inverse configuration circuit Because it has a sequence inverse converting circuit when returning to the original input digital image signal to issue,
The following effects are obtained.

That is, it is possible to restore the original digital image signal by compressing and decoding the main block digital image signal image-compressed and coded by the image compression coding apparatus, When the frame correlation (or field correlation) of the main block signal of the digital image signal is high, it is possible to obtain an image compression / decoding device that can avoid a decrease in compression efficiency.

According to the third aspect of the present invention, in the first aspect of the present invention, a shuffling circuit for shuffling the block digital image signal from the selecting means in units of blocks is provided. And the image compression encoding circuit, in addition to the effect of the first aspect of the present invention, a plurality of adjacent sub-block signals divided from the main block signal by the occurrence of a bit error in the transmission path are generated. It is unlikely that all of the constituent pixel data will be in error, making it impossible to restore the pixel data belonging to the main block signal.

According to the image compression / decoding apparatus of the fourth aspect of the present invention, in the second aspect of the invention, the block digital image signal of the error correction encoding / image compression encoding signal is shuffled in units of blocks. A deshuffling circuit for deshuffling a block digital image signal shuffled in units of blocks from the image compression / decoding circuit includes an image compression / decoding circuit, and first and second blocks.
And a plurality of adjacent sub-block signals divided from the main block signal by the occurrence of a bit error in the transmission path, in addition to the effect of the second aspect of the present invention. There is no possibility that all the pixel data to be processed will be in error, and it will not be possible to restore the pixel data belonging to the main block signal.

According to the fifth aspect of the present invention, in the first or third aspect of the present invention, since the image compression encoding circuit includes a high-efficiency encoder, the first or third aspect of the present invention is applicable. In addition to the effects of the present invention, the compression efficiency of the digital image signal is significantly increased.

According to the image compression / decoding device of the sixth aspect of the present invention, in the second or fourth aspect of the present invention, since the image compression / decoding circuit includes a high-efficiency decoder, In addition to the effects of the present invention, a digital image signal compressed with high compression efficiency can be reliably restored.

According to the image compression encoding apparatus of the seventh aspect of the present invention, in the fifth aspect of the present invention, since the image compression encoding circuit includes a variable length encoder, the effect of the fifth aspect of the present invention is obtained. Thus, the compression efficiency of the digital image signal is further improved.

According to the image compression / decoding device of the eighth aspect of the present invention, since the image compression / decoding circuit of the sixth aspect of the present invention includes a variable length decoder, the effect of the sixth aspect of the present invention is obtained. Thus, a digital image signal compressed with a higher compression efficiency can be reliably restored.

[Brief description of the drawings]

FIG. 1A is a block diagram showing an embodiment of an image compression encoding apparatus according to the present invention; FIG. 1B is a block diagram showing an embodiment of an image compression decoding apparatus according to the present invention;

FIG. 2 is a block diagram showing a conventional example of an image compression encoding apparatus.

FIG. 3 is a layout diagram of original pixel data for explaining the operation of a conventional example.

FIG. 4 is a layout diagram (1) of pixel data having a sub-sample configuration for explaining the operation of the conventional example.

FIG. 5 is a layout diagram (2) of pixel data having a sub-sample configuration for explaining the operation of the conventional example.

FIG. 6 is a layout diagram of pixel data having a sub-sample configuration for explaining the operation of the conventional example (3).

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 A / D converter 2 Time series conversion circuit FC frame correlation discrimination circuit 3 1 field delay unit 4 Difference absolute value calculation circuit 5 Subsample configuration circuit 6 Changeover switch 7 Integrator 8 Shuffling circuit 9 Image compression encoding circuit 10 Discrete Cosine transformation circuit 11 Quantization circuit 12 Variable length coding circuit 13 Packing circuit 14 Transmitter (error correction coding / modulator etc.) 15 Code amount controller 16 Image compression / decoding circuit 17 Receiver (demodulation / error correction circuit etc.) 18) Depacking circuit 19 Variable length decoder 20 Inverse quantization circuit 21 Discrete cosine inverse transformation circuit 22 Deshuffling circuit 23 Error correction / subsample inverse configuration circuit 24 Changeover switch 25 Error correction control circuit EC Error correction circuit 26 One field delay Container 27 Changeover switch 28 Time series reverse conversion circuit 9 D / A converter

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-240088 (JP, A) JP-A-3-1399083 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 5/91-5/956 H04N 7/24-7/68

Claims (8)

(57) [Claims] An input digital image signal is subdivided into a plurality of main block signals each consisting of pixel data arranged in a matrix in a predetermined number in a horizontal direction and in a vertical direction of the screen for each screen to form a main block. A time-series conversion circuit for obtaining a digital image signal; and separating pixel data constituting each main block signal of the main-blocked digital image signal from the time-series conversion circuit into pixel data adjacent to each other in the horizontal or vertical direction,
A sub-sampling circuit for dividing into a plurality of sub-block signals each consisting of pixel data arranged in a matrix in a predetermined number in a horizontal direction and a predetermined number in a screen direction to obtain a sub-blocked digital image signal; Frame correlation (or field correlation) determining circuit for determining the presence or absence of a frame correlation (or field correlation) for each main block signal of the coded image signal, and a frame correlation (or field correlation) by the frame correlation (or field correlation) determining circuit If there is a frame correlation (or field correlation) based on the determination result of the presence or absence of the main block signal, the main block signal from the time series conversion circuit is selected. If there is no frame correlation (or field correlation), the main block signal is selected. Select the sub-block signal from the sub-sample configuration circuit corresponding to the signal and select Selecting means for obtaining a compressed image signal; an image compression / encoding circuit for image-encoding the blocked digital image signal from the selecting means to obtain an image-compression-coded signal; An image compression encoding apparatus, comprising: an error correction encoding circuit that performs error correction encoding on the image compression encoded signal to obtain an error correction encoded signal. 2. An input digital image signal is obtained by subdividing, for each screen, a plurality of main block signals composed of pixel data arranged in a matrix in a predetermined number in each of a horizontal direction and a vertical direction of the screen. The main block signal of the main blocked digital image signal and the pixel data constituting each main block signal of the main blocked digital image signal are separated into pixel data adjacent to each other in the horizontal or vertical direction, and the horizontal and vertical directions of the screen are separated. Of the sub-block signals of the sub-blocked digital image signal obtained by dividing into a plurality of sub-block signals composed of pixel data arranged in a matrix by a predetermined number in each direction, a frame correlation (or When there is field correlation), the main block signal is selected, and there is no frame correlation (or field correlation). When the sub block signal corresponding to the main block signal is selected, an error correction coding / compression coding signal of the block digital image signal which is formed by selecting the sub block signal is supplied to correct the error. An error correction circuit that adds an error flag to an error that cannot be corrected; an image compression / decoding circuit that supplies the image compression / encoding signal from the error correction circuit to obtain the blocked digital image signal; The error of the main block signal in the blocked digital image signal from the compression / decoding circuit, the error of which could not be corrected by the error correction circuit, is detected by one frame (or 1 frame).
A first error correction circuit for correcting an error using the corresponding main block signal before the field, and an error correction circuit for the sub-block signal in the blocked digital image signal from the image compression / decoding circuit. A second error correction circuit for correcting an error that cannot be corrected using an adjacent sub-block signal corresponding to the sub-block signal, and a sub-block signal having an error correction from the second error correction circuit as a sub-block. A sub-sampled inverse configuration circuit that obtains an original main block signal by performing a sample inverse configuration, and a blocked digital image signal composed of a synthesized signal of the main block signal from the first error correction circuit and the sub-sampled inverse configuration circuit. An image compression / decoding device, comprising: a time-series inverse conversion circuit for returning to an original input digital image signal. 3. The image compression encoding apparatus according to claim 1, further comprising: a shuffling circuit for shuffling the block digital image signal from the selection unit in units of blocks, the shuffling circuit including the selection unit and the image compression code. An image compression encoding apparatus provided between an image compression circuit. 4. The image compression decoding apparatus according to claim 2, wherein the block digital image signal of the error correction coding / image compression coding signal is shuffled in units of blocks. A deshuffling circuit for deshuffling a block digital image signal shuffled on a block-by-block basis from the image compression circuit between the image compression / decoding circuit and the first and second error correction circuits. An image compression decoding apparatus characterized by the above-mentioned. 5. The image compression encoding apparatus according to claim 1, wherein said image compression encoding circuit includes a high-efficiency encoder. 6. The image compression / decoding device according to claim 2, wherein the image compression / decoding circuit includes a high-efficiency decoder. 7. The image compression encoding apparatus according to claim 5, wherein said image compression encoding circuit includes a variable length encoder. 8. The image compression decoding apparatus according to claim 6, wherein said image compression decoding circuit includes a variable length decoder.