JP3152922B2 - Current mirror circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a current mirror circuit.

2. Description of the Related Art Current mirror circuits are well known in MOS (metal oxide semiconductor) analog devices. These are used to convert the power supply to a current sink or vice versa.

A basic current mirror has first and second FETs (field effect transistors), whose sources are connected to one common constant potential, and whose gates are common.
Further, the gate of the first transistor connects to its drain. A current source is connected to the drain of the first transistor, and its output current is taken from the drain load of the second transistor. In this case, the ratio of the output current to the input current is ideally limited by the dimensional ratio of the transistors in the current mirror.

However, the accuracy of the current mirror circuit is actually determined by other factors, especially its output impedance. Ideally, this impedance should be infinite or very large compared to the load connected to the current mirror. In practice, the impedance of conventional current mirror circuits is too small for many applications, for example, high gain amplifiers.

The current mirror circuit can also be applied to generate an output current that is a fixed multiple of one input current or several output currents.

FIG. 1 shows a conventional cascode current mirror,
It comprises a first n-channel transistor 1 having a gate and drain connected and a second n-channel transistor 2 having a gate connected to the gate of the transistor.
It has a transistor pair. A current source for generating the input current Iin is connected to the drain of the first transistor, and its output Iout is a load (not shown) connected to the drain of the second transistor 3.
Taken from The second transistor pair is connected as follows. A third n-channel transistor 2 connects to the source of the first transistor 1. The gate of transistor 2 connects to its own drain and the gate of 4th n-channel transistor 4. The fourth transistor 4 is connected to the source of the second transistor 3. First, the saws of the third and fourth transistors 2, 4 are grounded. In this configuration,
If the drain current Vout3 of the second transistor increases and the output current Iout tends to increase to its correct value for the input current Iin, the drain source voltage Vds4 of the fourth transistor increases, thereby increasing the second transistor , The gate-source voltage Vds3 of the transistor 3 tends to decrease.
This limits the amount of current flowing along the drain source channel of the second transistor 3 and therefore the output current
Iout decreases. Thus, this circuit utilizes negative feedback for self-control.

The circuit of FIG. 1 is suitable for converting a current source into a current sink. In some cases, it may be necessary to use a current mirror type circuit to extract a second current source from an existing power supply. This is the case when a second current source having a different value from the current source to be developed is required or when a plurality of similar current sources are to be formed from one current source. The plurality of current sources are used, for example, in a digital-analog converter. For this purpose, an inverting current mirror circuit is used as a load for the drain of the second transistor 3 (FIG. 2). The inverted current mirror circuit comprises two pairs of current mirror P-channel transistors 5, 6 and 7, 8 connected in a cascode configuration as described above for transistors 1-4 in FIG. The operation of this inverting circuit is substantially the same as that of the transistors 1 to 4, and therefore detailed description is omitted.
In order to have a satisfactory output impedance so that it has a predetermined and accurate relationship with the input current Iin, the transistor pairs 1, 3 and 7, 8 are necessary. In the well-known digital-to-analog conversion current mirror, there are a plurality of transistor output configurations, indicated by transistors 6,8 and in FIG. 2 only by the dotted lines.

The circuit of FIG. 2 has a major drawback when it is incorporated into a semiconductor chip for CMOS digital processes having a large tolerance. As is well known, the drain-source current (Ids) of the FET for a given gate-source voltage (Vgs)
Is limited by its width / length ratio when incorporated into an actual integrated circuit. Identifying transistor widths in view of the worst possible sources during processing is always necessary in high tolerance processes, where the change in length due to process tolerance has a greater adverse effect than for longer transistors This is a major problem for short transistors. For a general input current of about 2 mA, each of the current mirror transistors 1-4 is 1500
A width W of about 0 μm and a length L of 1-2 μm are required.
This is extremely expensive in terms of space on one chip. Furthermore, the function of Ids, W, Vds in the FET is such that as the width / length ratio increases, Vds decreases for the same current. In the circuit of FIG. 2, when the width / length ratio of the P-channel transistor 5-8 decreases, the Vgs of the transistors 5 and 7 is required to keep Ids constant.
Must be increased. This means that the drain voltage of the n-channel transistor 3 approaches the ground region. Assuming that Vgs of transistor 3 is greater than the sum of its drain-source voltage Vds and threshold voltage Vt, transistor 3 will move from a saturated operating region to a linear region. Current mirrors designed to operate in the saturation region will fail in the linear region because Ids will change significantly even if Vds changes small. If the transistor 4 is also out of its saturation operating region, this error will be compounded and the circuit will stop functioning as a current mirror. The effect of reducing the width / length ratio of transistors 1-4 on the operating conditions of transistors 3 and 4 is the same. If there are four transistors connected between the power supply voltage VDD and the ground point as in the circuit of FIG. 2, the width / length ratio of each transistor is
They must be as large as possible so that they remain saturated even under worst-case conditions. At high temperatures and low supply voltages, well-known circuit designs for high tolerance processes cannot be used to keep the transistors saturated without making the dimensions of the transistors too large. Of course, from the viewpoint that as many circuits as possible are formed on one chip, it is important to reduce the width of the transistor.

According to the present invention, there is provided a current mirror circuit including first and second MOS field-effect transistors. The sources of these transistors are at a fixed potential, the gates are connected to receive a common gate voltage, and the drain of the first transistor is connected to a current source. An active controllable feedback element is connected to the drain of the second transistor, the element being controlled by a differential amplifier in response to the difference between the drain voltages of the first and second transistors, and the first and second elements being controlled by a differential amplifier. Keeping the drain voltage of the transistor substantially equal.

(Operation) Due to this use of the feedback element and the differential amplifier, the drain-source voltage of the current mirror transistor changes in the operating conditions of the circuit, for example, changes in load characteristics (affected by temperature and process tolerance, for example). Alternatively, it is maintained equal regardless of a change in the power supply voltage. Since the drain-source voltage of the second transistor depends only on the drain-source voltage of the first transistor, it is hardly affected by the load condition, and thus this current mirror circuit is higher than the conventional current mirror, and the cascode current mirror circuit Has the same impedance as.

However, due to the feedback control of the source-drain voltage, the width of the current mirror transistor can be greatly reduced to about 1300 μm as compared with the cascode current mirror circuit. Since no cascode transistors are required, fewer transistors span the power supply line, and therefore there are fewer problems keeping them saturated.

The feedback element may be an FET having a gate adapted to receive the output signal of the differential amplifier. This FET
Can be driven by a forward amplifier circuit that receives the output of the differential amplifier. Thereby, the second
Vgs of the first FET can be increased independently of the drain voltage of the second transistor, and thereby can conduct more strongly. This transistor can come with a smaller width / length ratio for the same Ids.

When the circuit of the present invention is used to generate an output current that is a constant multiple of the input current, another transistor in series with the feedback element may be connected to the drain of the second transistor. The first output element is driven by a differential amplifier,
The second output element is connected in series to the first output element and to this additional transistor. When a plurality of output currents are generated, a plurality of sets each including a first and a second output element and adapted to provide an output current can be connected in parallel with the first and the second output elements. With this configuration, the circuit of the present invention has the special effect of being able to generate an output element bias voltage without using the silicon area required by conventional circuits. Further, the set of first and second output elements connected in series as respective cascade pairs will create a high impedance current source.

The gates of the first and second transistors may be connected to the drain of the first transistor, but preferably the first and second transistors
Preferably, the gates of the transistors receive a common gate voltage from another voltage source circuit.

Independent control of the gate voltage means that Vgs can be greater than Vds. This allows small transistors,
That is, the same current can flow through a transistor having a small width / length ratio as a transistor having a large width / length ratio. In general, the width of the current mirror transistor can be reduced to about 360 μm. Therefore, the width of the transistor is significantly reduced even in consideration of a large tolerance.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to FIGS.

In FIG. 3, the element of the conventional current mirror circuit is a first n-channel transistor 2 having a drain connected to a current source Iin.
4 and a second transistor 26 having a gate connected to the gate of this transistor. The sources of the first and second transistors have a fixed potential (ground potential) and are connected. An active controllable feedback element in the form of a P-channel field effect transistor 28 is connected to the drain of transistor 26. In the embodiment of FIG. 3, the gates of transistors 24 and 26 connect to the drain of first transistor 24 at point 30. The gate of the P-channel transistor 28 is connected to the output of the differential amplifier, ie, the operational amplifier 12. The operational amplifier 12 creates a feedback loop in the current mirror circuit. The negative input 14 of the operational amplifier 12 receives the drain voltage V1 of the first transistor 24 at point 16. The positive input 18 of the operational amplifier 12 receives the drain voltage V2 of the second transistor 26 at point 20. The purpose of the operational amplifier 12 is the first and second transistors
This is to make drain voltages V1 and V2 of 24 and 26 equal. The drain voltage V2 of the second transistor 26 is
Increases with respect to the drain voltage V1, the output signal Vo of the operational amplifier 12 acts to reduce the Vgs of the transistor 28 and thus the Ids, thereby reducing the drain voltage V2 of the second transistor 26. When the drain voltage V2 becomes lower than V1, the output signal of the operational amplifier 12 acts to increase Vgs of the transistor 20 and increase V2. This way the point
16 and 20 are continuously equally biased.

Connected between the output of the operational amplifier 12 and its positive input 18 is a capacitor C1 that stabilizes the control loop when its phase margin is 45 ° C. or less.

The gate of the output transistor 50 receives the output signal Vo of the operation pump 12, and this transistor is driven by this output. A second output transistor 52 is connected in series with the first output transistor 50 to increase the output impedance of the circuit. Another P-channel transistor 48 is connected to the drain of the second transistor 26 to drive the first output transistor 52, which has its gate connected to the gate voltage Vg of the transistor 48.
Is to receive. Several output transistor sets can be provided as shown by the dotted lines in FIG. The output transistors 50 and 52 generate an output current Iout of the current mirror circuit controlled by the current source Iin.

In FIG. 4, two P-channel transistors 4
A forward amplifier comprising 0,42 and two channel transistors 44,46 is connected between the output of the operational amplifier 12 and the gate of the P-channel transistor 48. Transistor 48
At this time becomes the second actively controllable feedback element. These transistors of this amplifier circuit are connected as follows. That is, the P-channel transistor 40
The transistor 40 is connected between the power supply line VDD and the drain of the n-channel transistor 44. Transistor 44 has a gate connected to its drain and its source and gate connected to the source-gate of n-channel transistor 46, respectively. P-channel transistor 42 connects to the drain of transistor 46. Transistor 42 is connected to power supply VDD, and its gate is connected to the drain of transistor 46 and to the gate of transistor 48, which is a controllable feedback element.

The purpose of this circuit is to make the gate voltage V2 of the transistor 48 a positive function of the output voltage Vo of the comparator 12. The ratio is given by:

Here, W40 and W42 indicate the widths of the transistors 40 and 42, respectively, and K1 is a constant. The effect of this amplifier circuit is to reduce the width / length ratio of transistor 48 as described above.

FIG. 5 shows another embodiment of the present invention. First and second
The gates of transistors 24 and 26 receive the control voltage Vc at point 10 instead of being connected to the drain of first transistor 24.
This control voltage Vc is the drain voltage of transistor 24 from point 22
Taken out of the amplifier circuit that receives V1. The amplifier circuit comprises input and output n-channel transistors 36, 38 having a grounded source. Two P-channel transistors 32,34 connect the drains of transistors 36,38 to the power supply VDD and their gates connect to each other. The gates of transistors 32 and 34 are also connected to the drain of input transistor 36. The drain of output transistor 38 is connected to its gate. This circuit operates such that the ratio of Vc to V1 is given by:

Here, W38 and W36 are the widths of the transistors 38 and 36, and K2 is a constant. The independent control of Vpc and therefore the gate voltage of the first and second transistors 24, 26 allows this gate voltage to be fixed at a value higher than the drain voltage V1, but not so high that the transistor goes out of saturation. This offers the advantage that more current can flow for transistors of the same size, in which case the gate voltage is added to the drain voltage. Conversely, if the current value is constant, a smaller transistor can be used. 24th transistor
Is in the saturation region due to the power supply circuits 32, 34, 36, 38,
Biased closer to the linear region. The independent control of the feedback elements formed by the P-channel transistors 28, 42 has the same effect that the width of these transistors can be reduced for the same current as compared to the transistors 5, 7 of FIG. P-channel transistor 28,4
The dimensions of 8,40,42 are chosen so that in the worst case of maximum temperature, minimum supply voltage, maximum transistor length and maximum threshold voltage, feedback elements 28,48 are in the saturation region. In other cases, a deeper saturation region results.

〔The invention's effect〕

The reduction in transistor width made possible by this circuit is important, as in FIG. 2 (i), FIG. 3 (ii),
This is shown in Table 1 which compares the transistor widths for the case (iii) of FIG. 4 and the case (iv) of FIG.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a conventional cascode current mirror circuit, and FIG. 2 is a conventional cascode current mirror when used to generate an output current which is a multiple of an input current and can provide a variable output current. FIG. 3, FIG. 4, FIG. 4 and FIG. 5 are circuit diagrams of an embodiment of the present invention. 12 ... operational amplifiers, 24, 26 ... first and second n-channel transistors, 28, 48 ... P-channel field-effect transistors, 50, 52 ... output transistors, 40, 42 ... P-channel transistors, 44, 46 ... ... n-channel transistor.

Claims (11)

(57) [Claims] 1. A first and a second MOS field having a source connected to a fixed potential, a gate connected to input a common potential, and a drain of a first transistor connected to a current source. An effect transistor (24, 26) and a drain of the second transistor, and the first and second transistors are connected in accordance with a difference between drain voltages of the first and second transistors (24, 26). Actively controlled by a differential amplifier (12) for maintaining the drain voltages of the transistors substantially equal to each other;
The output terminal of this differential amplifier (12) is the output stage (50, 52)
A feedback element (28) connected to a first output terminal adapted to output a first reference voltage
And a biasing element (48) connected to the drain of the second transistor and to the actively controllable feedback element, the biasing element being connected to the output stage (50, 52).
A current mirror circuit coupled to the second output terminal for outputting a second reference voltage to the output of the differential amplifier (12). 2. The circuit of claim 1, wherein said actively controllable feedback element is a field effect transistor having a gate connected to an output terminal of said differential amplifier. 3. The circuit according to claim 1, further comprising an output stage coupled to said first output terminal and having an output element driven by said differential amplifier. 4. The circuit of claim 3, further comprising another output element connected in series with said first output element and coupled to said second output terminal. 5. The circuit according to claim 3, wherein each of said output elements is a field effect transistor. 6. The circuit according to claim 1, wherein said bias element is a field-effect transistor whose gate is connected to a drain. 7. A forward amplifier circuit (40) coupled to receive the output of said differential amplifier and arranged to drive said bias element (48) and said another output element (52). The circuit according to claim 4, comprising: 8. The circuit according to claim 1, comprising a plurality of said output stages, each providing an output current. 9. The circuit according to claim 1, wherein the gates of the first and second transistors are connected to a drain of the first transistor. 10. The circuit according to claim 1, wherein the gates of the first and second transistors are connected to input a common voltage from independent voltage supply circuits. 11. A capacitor (C ₁ ) connected between an output terminal of the differential amplifier (12) and a third terminal of the second transistor (26). The circuit according to any one of the above.