JP3152739B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the same, and more particularly to a technique for connecting a wiring constituting the semiconductor integrated circuit device to a semiconductor substrate.

[0002]

2. Description of the Related Art Aluminum (Al) or an alloy thereof is used as a wiring material of a semiconductor integrated circuit device.
Al is a wiring material for semiconductor integrated circuit devices, such as low resistivity, low contact resistance with p ^{+ -type} or n ^{+ -type} semiconductor layers formed on silicon (Si), and easy film formation and processing. This is because it has excellent properties to be used as.

However, in the case of single-layer Al wiring, with the miniaturization of wiring and connection holes in a semiconductor integrated circuit device, wiring disconnection failure due to electromigration and stress migration, and Si deposition on the Al wiring side. The problem of wiring reliability, such as an increase in the contact resistance between the Al wiring and the semiconductor substrate, has become significant.

Therefore, in recent years, for example, titanium tungsten (TiW), titanium nitride (Ti
By providing a base metal film made of N), tungsten (W), molybdenum (Mo), or the like, there is a tendency that wiring disconnection failure, Si deposition, and the like are prevented and wiring reliability is ensured.

However, when the underlying metal film is brought into direct contact with the Si substrate, the contact resistance, particularly the p-channel MOS • F
There is a problem that the contact resistance at the contact portion when directly contacting the p-type semiconductor layer forming the source / drain region such as ET (hereinafter simply referred to as pMOS) increases.

As a solution, it is conceivable to increase the contact area, but in this case, it is against the tendency of miniaturization of the semiconductor integrated circuit device. It is also conceivable to set the impurity concentration of the p-type semiconductor layer to be higher. However, in this case, a problem of deteriorating the characteristics of the pMOS, such as a short channel effect, occurs, which hinders miniaturization of the pMOS.

Therefore, without causing such a problem,
As a method of reducing the contact resistance between the underlying metal film and the p-type semiconductor layer, a low-resistance silicide layer such as a platinum silicide (PtSi) layer is interposed between the underlying metal film and the p-type semiconductor layer. A method has been proposed. This method is, for example, as follows.

First, a connection hole for exposing a p-type semiconductor layer is formed in an insulating film on a main surface of a Si substrate, and then a P hole is formed on the Si substrate.
A t film is deposited. Subsequently, a heat treatment is performed on the Si substrate to cause Pt and Si to react at a contact portion between the Pt film and the p-type semiconductor layer to form a PtSi layer at the contact portion. To remove. At this time, the PtSi layer remains on the p-type semiconductor layer in the connection hole. After that, a base metal film and an Al alloy film are sequentially deposited on the Si substrate, and the laminated film is patterned by a photolithography technique to form a wiring having a two-layer structure.

[0009] Regarding the prior art of providing a base metal film below the Al wiring, see, for example, Nikkan Kogyo Shimbun, Showa 6
It is described in “CMOS Device Handbook”, published on September 29, 2010, pages P332 to P333, which describes the necessity of providing a barrier metal below the Al wiring.

[0010]

A low-resistance silicide layer such as a PtSi layer is provided at a contact portion between a base metal film constituting a wiring and a p-type semiconductor layer of a semiconductor substrate. Does not violate the miniaturization of the semiconductor integrated circuit device, and does not have to increase the impurity concentration of the semiconductor layer, so that the short channel effect does not occur and the miniaturization of the element can be promoted. However, the present inventor has found that a step of depositing a Pt film and a step of removing the Pt film are required, which increases the number of manufacturing steps of the semiconductor integrated circuit device and complicates the steps. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a base metal film forming a wiring and a semiconductor substrate without increasing or complicating the manufacturing process of a semiconductor integrated circuit device. It is an object of the present invention to provide a technology capable of reducing the contact resistance with the contact.

The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the first aspect of the present invention, a wiring is formed by laminating a base metal film and a conductor film in order from the lower layer on an insulating film on a semiconductor substrate. And the constituent atoms of the base metal film and the semiconductor substrate are combined at the contact portions of the semiconductor integrated circuit, and a compound layer that is epitaxial with respect to the semiconductor substrate is provided.

According to a fifth aspect of the present invention, a step of forming a connection hole reaching the semiconductor substrate in an insulating film on the semiconductor substrate, and depositing a base metal film for forming wiring on the insulating film in which the connection hole is formed. And annealing the semiconductor substrate, at a contact portion between the base metal film and the semiconductor substrate, the respective constituent atoms of the base metal film and the semiconductor substrate are combined, and epitaxially formed on the semiconductor substrate. Forming a compound layer to electrically connect the base metal film and the semiconductor substrate.

[0016]

According to the first aspect of the present invention, for example, the work function difference between the underlying metal film forming the wiring and the semiconductor layer of the semiconductor substrate can be reduced, so that the wiring and the p-type semiconductor layer can be reduced.
The contact resistance with the semiconductor layer can be reduced.

For this reason, for example, the impurity concentration of the p-type semiconductor layer forming the source / drain regions of the pMOS can be made lower than before, so that the short channel effect of the pMOS can be suppressed and the miniaturization of the pMOS is promoted. It becomes possible.

According to the fourth aspect of the present invention, for example, the step of depositing the Pt film and the step of removing the Pt film are not required, so that the number of manufacturing steps of the semiconductor integrated circuit device can be reduced. The process can be simplified.

[0019]

FIG. 1 is a cross-sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention. FIGS. 2 to 4 are cross-sectional views of a main part during a manufacturing process of the semiconductor integrated circuit device of FIG. FIG. 5 is a graph showing the relationship between the contact resistance between the wiring and the semiconductor substrate and the annealing temperature.

The semiconductor integrated circuit device according to the first embodiment is constituted by, for example, a CMOS (Complimentary MOS) circuit. FIG. 1 shows a pMOS portion of the semiconductor integrated circuit device according to the first embodiment.

The semiconductor substrate 1 is, for example, n ^- consists shape Si single crystal, the inactive region on the main surface, for example SiO
₂ is formed. Note that a channel stopper layer 3 is formed below the field insulating film 2. For example, phosphorus which is an n-type impurity is introduced into the channel stopper layer 3.

On the main surface of the semiconductor substrate 1, for example, a pMOS 4 is formed in an active region surrounded by the field insulating film 2. That is, the periphery of the pMOS 4 is defined by the field insulating film 2.

The pMOS 4 includes semiconductor layers 5 and 5 formed on the semiconductor substrate 1, a gate insulating film 6 formed between the semiconductor layers 5 and 5, and a gate formed on the gate insulating film 6. And an electrode 7.

The semiconductor layer 5 is doped with, for example, a p-type impurity such as boron.
⁺ Semiconductor layer 5b. That is, in the first embodiment, the pMOS 4 is an LDD (Lightly
Doped Drain) structure.

The gate insulating film 6 is made of, for example, SiO ₂ . The gate electrode 7 is configured by, for example, laminating two layers of conductor films 7a and 7b in order from the lower layer. Conductive film 7a
Is made of, for example, doped polysilicon. The conductor film 7b is made of, for example, tungsten silicide (WSi ₂ ).

The spacer 8 is formed on the side wall of the gate electrode 7. The spacer 8 is an insulating film for forming the LDD structure, and is made of, for example, SiO ₂ .

On the semiconductor substrate 1, an interlayer insulating film 9 is deposited. The interlayer insulating film 9 is made of, for example, SiO ₂ , on which a wiring 10 is formed.

The wiring 10 is composed of a base metal film 10 a and a conductor film 10 b laminated in order from the bottom, and a part of the base metal film 10 a is formed in the interlayer insulating film 9 by a connection hole 11.
Through the semiconductor layer 5.

In the first embodiment, the contact portion between the base metal film 10a and the semiconductor layer 5 is
a and the constituent atoms of the semiconductor layer 5 are combined,
Further, a silicide layer (compound layer) 12 which is epitaxial with respect to the semiconductor substrate 1 is formed.

That is, in the semiconductor integrated circuit device of the first embodiment, since the silicide layer 12 is provided at the contact portion between the underlying metal film 10a and the semiconductor layer 5, the Since the work function difference can be reduced, the structure is such that the contact resistance between the underlying metal film 10a and the semiconductor layer 5 can be reduced.

The base metal film 10a is, for example, 30 atm%.
It is made of TiW containing about titanium (Ti), and its thickness is, for example, about 150 nm.

However, the amount of Ti in the base metal film 10a is
It is not limited to 30 atm% but can be variously changed. For example, a range of 15 atm% or more and 60 atm% or less is preferable. This is based on the following research results of the inventor.

That is, for example, when the amount of Ti contained in the base metal film 10a is set to 15 atm% or less, an epitaxial silicide layer is not sufficiently formed at a contact portion between the base metal film 10a and the semiconductor layer 5, and the base metal The contact resistance between the film 10a and the semiconductor layer 5 was not too low.

On the other hand, when the contact resistance between the underlying metal film 10a and the semiconductor layer 5 is sufficiently reduced,
a was removed, and the silicide layer 12 was analyzed with an X-ray microanalyzer.
It was about 6 to 4.

Although the composition ratio of Ti and W is slightly different due to a difference in sputtering equipment even when the same sputter target is used, the above analysis results show that if TiW contains about 60 atm% or less of Ti, the silicide layer 12 is formed. It has been found that the semiconductor substrate 1 can be made epitaxial.

However, the underlying metal film 10a is not limited to TiW but can be variously changed.
W, TiTa or the like may be used.

The conductor film 10b is made of, for example, Al or Al-
It is made of a Si-copper (Cu) alloy and has a thickness of, for example, 4
It is about 00 nm.

The silicide layer 12 is made of, for example, a compound of Ti, W and Si, and has a thickness of, for example, about 3 nm.

Although not shown, a surface protective film is deposited on the wiring 10 and the interlayer insulating film 9. The surface protective film is, for example, an insulating film made of SiO ₂ deposited by a plasma CVD method and an insulating film made of silicon nitride (Si ₃ N ₄ ) also deposited by a plasma CVD method or the like, which are sequentially stacked from the lower layer. It is configured.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS. In the first embodiment, to simplify the description, the n-channel MO
The description of the manufacturing process of S is omitted.

First, as shown in FIG. 2, for example, the n ^- type S
An inactive region on a main surface of a semiconductor substrate 1 made of i-single crystal is selectively oxidized to form a field insulating film 2 in that region. At this time, an n-type channel stopper layer 3 is formed below the field insulating film 2 at the same time.

Subsequently, on the main surface of the semiconductor substrate 1, an active region whose periphery is defined by the field insulating film 2 is oxidized, and a gate insulating film 6 is formed in that region.

Thereafter, a conductor film made of doped polysilicon and a conductor film made of WSi ₂ are deposited on the semiconductor substrate 1, and the conductor film is patterned by photolithography to form a gate electrode 7.

Next, using the gate electrode 7 as a mask, the semiconductor substrate 1 is lightly ion-implanted with, for example, boron, which is a p-type impurity, to form a p-type semiconductor layer 5a.

Subsequently, after depositing an insulating film (not shown) on the semiconductor substrate 1, the insulating film is etched back to form spacers 8 on the side walls of the gate electrode 7.

Thereafter, after forming a thin oxide film on the entire surface of the semiconductor substrate 1, a gate electrode 7 and the spacer 8 as a mask, the semiconductor substrate 1, for example by ion implantation of boron or the like as p-type impurity, p ⁺ The semiconductor layer 5b is formed. Thus, the pMOS 4 is formed on the semiconductor substrate 1.

Next, as shown in FIG.
After an interlayer insulating film 9 made of, for example, SiO ₂ is deposited thereon by a CVD method or the like, a connection hole 11 reaching the semiconductor layer 5 is formed in the interlayer insulating film 9 by photolithography.

Subsequently, a metal film 10a1 made of, for example, TiW for forming a base metal film 10a (see FIG. 1) is deposited on the semiconductor substrate ₁ by a sputtering method or the like.

[0049] The amount of Ti in the metal film 10a ₁ at this time, for the reasons mentioned above, for example, about 30 atm%. The thickness of the metal film 10a ₁ is, for example, about 150 nm.

Thereafter, the semiconductor substrate 1 is housed in a normal furnace body (not shown), and is annealed at 650 ° C. for 30 minutes in, for example, a nitrogen atmosphere, and TiW of the metal film 10a ₁ and Si of the semiconductor layer 5 are formed. by compounding bets, as shown in FIG. 4, a silicide layer 1 in the contact portion between the metal film 10a ₁ and the semiconductor layer 5
Form 2

That is, in the first embodiment, a step of depositing a Pt film and a step of removing the Pt film as in the conventional technique of forming a PtSi film at a contact portion between the base metal film 10a and the semiconductor layer 5 are unnecessary. Therefore, the manufacturing process of the semiconductor integrated circuit device can be reduced, and the process can be simplified.

The silicide layer 12 formed by annealing was epitaxial with respect to the semiconductor substrate 1 and was a thin layer having a thickness of about 3 nm. Therefore, the stress on the semiconductor substrate 1 and the semiconductor layer 5 due to the volume change accompanying the chemical reaction or the like when forming the silicide layer 12 can be small, and no increase in the junction leak or the like due to the stress is observed. Showed good electrical characteristics.

Furthermore, by annealing, the resistance of the conductor film 10b (see FIG. 1) was lower than in the case where the annealing was not performed, and the resistance of the wiring 10 could be reduced. This is because where the annealing, since the oxide of low reactivity Ti on the surface of the metal film 10a ₁ or the like is segregated, and thereafter, the conductive film 10b and a metal film made of Al is deposited on the metal film 10a ₁ results of the reaction is suppressed in 10a _1, conductive films 10b intrinsic conductivity of Al is assumed to be due to reserved.

However, the annealing temperature is not limited to 650 ° C. but can be variously changed.
C. to 750.degree. C., ideally, for example, 600.degree.
A range of 0 ° C. or lower is preferred.

FIG. 5 shows the relationship between the contact resistance of the contact portion between the base metal film 10a and the semiconductor layer 5 and the annealing temperature.
As shown in FIG. 5, it can be seen that the contact resistance between the underlying metal film 10a and the semiconductor layer 5 significantly decreases at about 600 ° C. or higher.

However, according to the study of the present inventors, when the annealing temperature is 750 ° C. or higher, non-uniform crystal grains having a diameter of about several tens nm are observed in the silicide layer 12. As a result of observing the cross section of the sample in this case with a transmission electron microscope or the like, a strong strain was observed in the p ^{+ -type} semiconductor layer 5b around the connection hole 11, which caused the p ^{+ -type} semiconductor layer 5 and the semiconductor substrate 1
Was found to be destroyed.

Further, according to the study of the present inventors, the silicide layers of the samples at the annealing temperatures of 600 ° C. and 700 ° C. were removed from the underlying metal film after each annealing treatment, and the photoelectrons were removed. Inspection by spectroscopy and the like revealed that the silicide layer in that case had almost the same surface state as the favorable silicide layer 12 when the above-mentioned annealing temperature was 650 ° C.

Therefore, since it is assumed that the temperature varies depending on the annealing method, etc., it cannot be specified unconditionally. However, if the annealing temperature is at least in the range of about 600 ° C. to 700 ° C., for example, A good silicide layer 12 is formed.

[0059] After forming the silicide layer 12 by annealing on the metal film 10a _1, for example, Al-Si-
After depositing a conductive film made of Cu alloy (not shown), a wiring 10 which shows the conductive film and the metal film 10a ₁ in FIG. 1 is patterned by photolithography.

Thereafter, although not shown, an SiO ₂ film and a Si ₃ N ₄ film are deposited on the wiring 10 and the interlayer insulating film 9 by, for example, a plasma CVD method or the like, and the semiconductor substrate 1 is formed.
A surface protective film is formed thereon.

As described above, according to the first embodiment, the following effects can be obtained.

(1). Base metal film 10 a constituting wiring 10
And providing a silicide layer 12 that is epitaxial with respect to the semiconductor substrate 1 at a contact portion between the semiconductor layer 5 and the pMOS 4, thereby reducing the work function difference between the base metal film 10 a and the semiconductor layer 5. Therefore, the contact resistance between the base metal film 10a and the semiconductor layer 5 can be reduced.

(2) According to the above (1), the p ^{+ type} semiconductor layer 5b
Can be made lower than before,
The short channel effect of pMOS4 can be suppressed,
It is possible to promote the miniaturization of the MOS4. Therefore, the degree of element integration of the semiconductor integrated circuit device can be improved.

(3) By forming the silicide layer 12 by annealing, a step of depositing a Pt film as in the prior art in which a PtSi film is formed at a contact portion between the underlying metal film 10a and the semiconductor layer 5 or Since the step of removing the Pt film becomes unnecessary, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced as compared with the case of the related art, and the step can be simplified.

(4) The underlayer metal film 10a is, for example, 15 at.
m% or more and 60 atm% or less, ideally 30 atm
% Of TiW and an annealing temperature of 550 ° C. to 750 ° C., ideally 6 ° C.
Annealing in the range of not less than 00 ° C. and not more than 700 ° C. allows the silicide layer 1 to be very thin, for example, about 3 nm and to be epitaxial with the semiconductor substrate 1
2 can be formed.

(5) According to the above (4), the stress on the semiconductor substrate 1 and the semiconductor layer 5 due to the volume change accompanying the chemical reaction or the like when forming the silicide layer 12 can be small, and the bonding caused by the stress can be reduced. No increase in leakage was observed, and pMOS4
And it is possible to obtain good electrical characteristics.

[0067]

Second Embodiment FIGS. 6 to 10 are cross-sectional views of a main part of a semiconductor substrate during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention, and FIG. 11 is a main portion of the manufacturing process of the semiconductor integrated circuit device. FIG. 12 is a graph showing the annealing temperature dependence of the contact resistance between the wiring and the p ^{+ -type} semiconductor layer in the connection hole, FIG. 13 is a graph showing the annealing temperature dependence of the junction leak current, and FIG. a) is a graph showing the forward current-voltage characteristics of a Schottky barrier diode, FIG.
4 (b) is a graph showing the reverse current-voltage characteristics of the Schottky barrier diode, FIG. 15 is a cross-sectional view of the silicide layer after post-annealing observed by SEM, and FIG.
6 is a cross-sectional view of the interface between the base metal film and the semiconductor substrate after annealing observed by TEM, FIG. 17 is a graph showing an X-ray diffraction spectrum of the silicide layer, and FIGS.
(C) is a graph showing an ESCA spectrum of the silicide layer, and FIG. 19 is an explanatory diagram showing a model of silicidation of the underlying metal film.

The method of manufacturing the semiconductor integrated circuit device according to the second embodiment uses, for example, a CMOS circuit and a Schottky barrier diode on the same semiconductor substrate.
e: hereinafter abbreviated as SBD). Hereinafter, a method of manufacturing the semiconductor integrated circuit device according to the second embodiment will be described with reference to FIGS.

The semiconductor substrate 1 shown in FIG. 6 is a (100) substrate made of, for example, p-type Si single crystal and having a resistivity of 10 Ω · cm.

First, for such a semiconductor substrate 1,
After the field insulating film 2 is formed by the LOCOS method or the like, for example, phosphorus (P), which is an n-type impurity, is ion-implanted into the pMOS formation region P and the SBD formation region S to form an n-well 13n. Note that N in FIG. 6 indicates an nMOS formation region.

Subsequently, as shown in FIG. 7, for example, boron (B) which is a p-type impurity is ion-implanted into the nMOS formation region N to form a p-well 13p.

Thereafter, as shown in FIG.
Is formed, for example, boron is ion-implanted into the pMOS formation region P and, for example, phosphorus is ion-implanted into the nMOS formation region N, and the p ^{+ -type} semiconductor layers 5c,
5c and n ^{+ -type} semiconductor layers 5d, 5d are formed.

Next, as shown in FIG.
After the insulating film 14 is formed thereon, the p ⁺ semiconductor layer 5c, the n ⁺ semiconductor layer 5d and the SBD formation region S
Connection holes 11a reaching the n-well 13n
１１11c are opened.

Subsequently, on the semiconductor substrate 1, for example, TiW
After depositing the underlying metal film 10a made of, silicidation is performed. Thus, a silicide layer (compound layer) not shown in FIG. 9 is provided between the base metal film 10a and the p ^{+ -type} semiconductor layer, the n ^{+ -type} semiconductor layer, and the n-well 13n, as in the first embodiment. It is formed. The silicidation will be described later.

Thereafter, as shown in FIG.
CuSi and TiW are sequentially deposited, for example, TiW / AlC
The wiring 10 made of uSi / TiW is formed. As a result, the n-channel MOS • FET 1 is placed in the nMOS formation region N.
5, a pMOS 4 is formed in the pMOS formation region P, and a Schottky barrier diode (SBD) formation region S is formed.
Then, a Schottky barrier diode (SBD) 16 is formed.

FIG. 11 shows, for example, a process flow of TiW silicidation of the second embodiment.

After connecting holes 11 (see FIGS. 9 and 10) are formed by dry etching or the like (step 101), wet pretreatment is performed (step 102), and then, for example, TiW is sputtered onto semiconductor substrate 1 by sputtering. It is formed thereon (step 103).

For the sputtering, for example, a normal DC sputtering apparatus (not shown) is used, and a target such as 10 W
A t% Ti-W target was used. Thereafter, using a general horizontal furnace (not shown), for example, in an N ₂ atmosphere,
Annealed at 0-800 ° C. for 30 minutes (step 104).

Finally, for example, AlCuSi and TiW are
For example, the wirings 10 were formed sequentially by a sputtering method (steps 105 and 106).

Next, the evaluation items and the evaluation method of the semiconductor integrated circuit device thus formed will be described.

The electrical characteristics were measured for contact resistance, junction leakage current and SBD characteristics.

The contact resistance was measured for a contact hole of about 0.6 μm × 0.6 μm using, for example, the Kelvin method. For the junction leak current, a reverse current was measured using a large-area p / n junction of, for example, 35,000 μm ² . SB
For D characteristics, for example, an SBD having an area of 600 μm ² is manufactured,
Forward characteristics and reverse characteristics were measured.

To clarify the physical phenomenon of silicidation, the cross section of the silicide layer was observed with a scanning electron microscope (SEM) and a transmission electron microscope (TEM).

The TiW / Si interface was analyzed by X-ray photoelectron spectroscopy (ESCA) and X-ray diffraction (XRD).

Next, the electrical characteristics of the semiconductor integrated circuit device based on the evaluation will be described.

FIG. 12 shows the annealing temperature dependence of the contact resistance. contact resistance to the p ⁺ -type semiconductor layer (p ⁺ Si), compared to about 600Ω and high without annealing, the resistance is low as a higher annealing temperature, the following values 100Ω is obtained, for example, 650 ° C. or higher. The contact resistance to the n ⁺ -type semiconductor layer (n ⁺ Si) is about 50Ω and sufficiently low even without annealing, little change was observed even when annealed.

FIG. 13 shows the annealing temperature dependence of the junction leak current. In both cases of the n ⁺ / p junction and the p ⁺ / n junction, the leakage current is as small as up to about 700 ° C. as compared with the case without annealing, but a sharp increase is observed at 750 ° C. or more.

From the above results, the annealing was performed at about 650 ° C. where the contact resistance was sufficiently low and the junction leakage current did not increase, and the measurement was performed on a sample manufactured under these conditions.

FIGS. 14A and 14B show examples of the measurement results of the SBD characteristics in that case. FIG. 14A shows the result of the forward characteristic, and FIG. 14B shows the result of the reverse characteristic. SBD
According to thermionic emission theory, is expressed by the following equation (SM Sze, Physics of Semiconducto).
r Devices, 2nd ed. (Wiley, New York, 198
1)).

J = Js [exp (qV / nkT) −1] Js = A * T2 exp (−qφB / kT) where q is an elementary charge, k is a Boltzmann constant, T is an absolute temperature, A * Is valid Richardson
(rdson) constant, φB is a barrier height. n is a correction coefficient from an ideal value, and ideally n = 1.

From FIG. 14A, for example, φB = 0.61e
V, n = 1.03 was obtained. φB = 0.61 eV is Ti
ΦB of Si ₂ = 0.60 eV and φB of WSi ₂ = 0.65 eV
V (SM Sze, Physics of Semic)
onductor Devices, 2nd ed. (Wiley, New York, 1
981)). Also, n = 1.03 is close to the ideal value, which indicates that the SBD characteristics are good.

Next, FIG. 15 shows a cross-sectional SEM photograph of a connection hole portion annealed at, for example, 700 to 800 ° C. After polishing the cross section of the semiconductor substrate, for example, HF: HNO ₃ : CH
_The diffusion layer (n ⁺ semiconductor layer) was etched by immersion in a ₃ COOH mixed solution and observed.

At 800 ° C., for example, it can be seen that the silicide layer has grown to a thickness greater than the thickness of the diffusion layer, which has increased the junction leakage current. On the other hand, for example, at a temperature of 750 ° C. or lower, no clear silicide layer is formed.

FIG. 1 is a cross-sectional TEM photograph of the TiW / Si interface when annealing is performed at 650 ° C. for 30 minutes, for example.
6 is shown. Semiconductor substrate 1 and base metal film 1 made of TiW
0a, a silicide layer 12 having a thickness of about 4 to 5 nm is formed epitaxially, and the lattice spacing thereof is about 0.
39 nm.

This corresponds to 0.391n of WSi ₂ (002).
m (F. d 'Heurle, et al., J. Appl. Phys., Vol.
51, p. 5976 (1980); S. Murarka, et a
l., J. Appl. Phys., Vol. 52, p. 7450 (1
981)) or 0.3 of Ti ₃ W ₂ Si ₁₀ (100).
99 nm (F. Nova, et al., J. Appl. Phys., Vo.
l. 54, p. 2434 (1983), J. M. Harris, et.
al., J. Electrochem. Soc., Vol. 123, p.
0 (1976)).

Next, FIG. 17 shows an XRD spectrum of the silicide layer. For example, after TiW silicidation, the surface TiW was removed with, for example, H ₂ O ₂ , and the measurement was performed using Cu kα.

At 650 ° C., for example, no clear peak due to silicidation is observed,
A slight peak of (Ti _1-X W _X ) Si ₂ is observed at ₂ ° = 22 ° at ° C. Furthermore, for example, at 750 ° C. or higher intense peak (Ti _1-X W _X) Si _2, WSi ₂ was observed, a thick (Ti _1-X W _X) that a mixed crystal of Si ₂ and WSi ₂ are formed I understand.

Next, the ESCA spectrum of the semiconductor substrate surface after removing TiW with, for example, H ₂ O ₂ is shown in FIG.
(A) to (c) are shown. For example, for an annealing temperature of 500 ° C. to 750 ° C., for example, Si (2p), Ti
(2p), the change of the spectrum of W (4f) is shown.

First, paying attention to the spectrum of Si (2p) in FIG.
(Oxide) The binding energy difference (chemical shift) from the peak is, for example, 4.40 eV at 550 ° C. or lower, whereas it is 4.24 eV at 600 ° C. or higher, which is 0.16.
eV is smaller. This result indicates that silicide was generated at, for example, 600 ° C. or higher.

Further, Ti (2p) shown in FIGS. 18B and 18C is used.
And W (4f) spectrum, for example, 550 ° C.
In each case, only an oxide peak is observed, whereas, for example, at 600 ° C. or higher, metal and oxide are observed.
The peak of e is observed. This suggests that a silicide layer of Ti and W is formed at, for example, 600 ° C. or higher. Note that the oxide peak was observed because, in addition to oxidation in the air, TiW was removed by H ₂ O ₂ to oxidize.

Next, for example, a model of TiW silicidation is shown in FIG. After the base metal film 10a made of TiW is formed on the semiconductor substrate 1, annealing is performed at a temperature of, for example, 600 ° C. or more, so that the silicide layer 12 is formed between the base metal film 10a and the semiconductor substrate 1.

From the results of TEM and ESCA, for example, 60
In the range of 0 to 700 ° C., a ternary alloy of Ti, W and Si (T
i _1-X W _X ) Si ₂ was found to be formed epitaxially. By forming the silicide layer 12, the contact resistance is reduced.

SE Babcock et al.
Annealing, TiW for Ti-rich TiW
/ Si interface is formed with 25 nm TiSi ₂
In the case of rich TiW, it is thick at 750 ° C. or higher (Ti
_1-X W _X) only Si ₂ or WSi ₂ have reported that is formed (S. E. Babcock, et al. , J. Appl.
Phys., Vol. 53, p. 6898 (1982);
E. Babcock, et al., J. Appl. Phys., Vol. 59,
p. 1599 (1986)).

This is because their analysis tools are XRD and RBS.
Is very thin (Ti
_{It is considered that 1-X} W _x ) Si ₂ silicide layer could not be observed. Onishi et al. Reported that TiW ₂ was formed at the TiW / Si interface by lamp annealing (RTA) of TiW (Shigeo Onishi, et al., ECS Japan Branch 2nd Symposium << Al Wiring in ULSI Problems on Technology >> p. 50 (1989)).

Further, in annealing at 750 ° C. or more, the silicide layer is made of polycrystalline (Ti _1-x Wx) Si ₂ and WSi.
It becomes a mixed crystal of ₂ and rapidly thickens. Then, this thick silicide layer 17 penetrates through the diffusion layer, causing an increase in junction leak current.

A difference in silicidation due to annealing between TiW / Si and W / Si has already been reported (M.
Suzuki, et al., 1991 SSDM p.
991)), as described above, an epitaxial layer of (Ti _1-x W _x ) Si ₂ is formed in TiW / Si, whereas epitaxy is not formed in W / Si and polycrystalline WSi
₂ causes junction leakage at low temperatures,
Process window narrows. That is, TiW silicidation is a process more suitable for fine ULSI than W.

As described above, according to the second embodiment, low contact resistance and good SBD characteristics can be simultaneously obtained by silicidation of TiW deposited on the semiconductor substrate 1.

As a result, for example, the connection hole 11b having a thickness of 0.6 μm is formed.
, The p ^{+ type} semiconductor layer 5c is also
A low contact resistance of 0Ω or less can be achieved. In addition, for example, SB of barrier height φB = 0.61 eV
D can be obtained.

In particular, during the silicidation of TiW, for example, annealing at 600 to 700 ° C.
Si interface ternary alloy _{(Ti 1-X W X)} Si 2 is formed epitaxially Thus, it is possible to reduce the contact resistance, and makes it possible to obtain good SBD properties.

Further, by forming the silicide layer 12 by annealing, a Pt film as in the prior art in which a PtSi film is formed at a contact portion between the base metal film 10a and the semiconductor layer is formed in the same manner as in the first embodiment. Since the step of depositing and the step of removing the Pt film are not required, the number of manufacturing steps of the semiconductor integrated circuit device can be reduced as compared with the related art, and
The process can be simplified.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the first and second embodiments, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the first and second embodiments, the case is described in which the wiring is formed by laminating a conductor film made of Al or the like on a base metal film made of TiW. However, the present invention is not limited to this. For example, Ti as a base metal film
Mo, TiTa, ZrW, ZrMo, ZrTa, Hf
W, HfMo, HfTa may be used. This is IV
The group a Ti, Zr, and Hf can reduce the SiO ₂ at the metal / Si interface, so that the interfacial reaction uniformly occurs, and T
a, W, and Mo are slower in silicidation than IVa group metals, and form only a thin silicide layer. And
This is because the silicide layer is thin and can stably exist on Si even if the lattice strain is large.

For example, the wiring may be formed by laminating a W film on a base metal film. In these cases, after patterning the wiring, annealing for forming a silicide layer may be performed.

In the first and second embodiments, the case in which the annealing for forming the silicide layer is performed in the furnace is described. However, the present invention is not limited to this. Is also good. At the time of lamp annealing, the atmosphere in the processing chamber is, for example, a nitrogen atmosphere or an ammonia atmosphere.

When lamp annealing is used, the annealing time can be reduced to about one minute. In this case, a thin silicide layer was formed even after annealing at 750 ° C., for example, and no increase in junction leakage was observed.

If a nitrogen atmosphere is used during lamp annealing, the surface of the underlying metal film made of
Since i was deposited, the wiring resistance could be reduced as compared with the case where annealing was not performed.

When the lamp annealing is performed in an ammonia atmosphere, TiN, tungsten nitride, or the like is formed on the surface of a base metal film made of TiW or the like. Can be reduced, and the wiring resistance can be reduced.

In the above description, the invention made mainly by the present inventor is described in the CMO, which is the field of application in which the background was used.
Although the description has been given of the case where the present invention is applied to a semiconductor integrated circuit device constituted by S circuits, the present invention is not limited to this, and various applications are possible. For example, a semiconductor integrated circuit device constituted by a bipolar transistor or a BiC-MOS (Bipola MOS)
r CMOS) and other semiconductor integrated circuit devices such as a semiconductor integrated circuit device.

[0119]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) According to the first aspect of the present invention, for example, the work function difference between the underlying metal film forming the wiring and the p-type semiconductor layer of the semiconductor substrate can be reduced. Contact resistance between the semiconductor layer and the p-type semiconductor layer can be reduced. For this reason, for example, the impurity concentration of the p-type semiconductor layer forming the source / drain regions of the pMOS can be reduced, so that the short channel effect of the pMOS can be suppressed, and miniaturization of the pMOS can be promoted. Therefore, it is possible to improve the degree of element integration of the semiconductor integrated circuit device.

(2) According to the fifth aspect of the present invention, for example, the step of depositing the Pt film and the step of removing the Pt film are not required, so that the number of manufacturing steps of the semiconductor integrated circuit device can be reduced. In addition, the process can be simplified. That is, it is possible to reduce the contact resistance between the wiring and the semiconductor substrate without increasing or complicating the manufacturing process of the semiconductor integrated circuit device.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention.

2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;

3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;

4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;

FIG. 5 is a graph showing a relationship between a contact resistance between a wiring and a semiconductor substrate and an annealing temperature.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate during a manufacturing step of a semiconductor integrated circuit device according to another embodiment of the present invention;

7 is a fragmentary cross-sectional view of the semiconductor substrate during a manufacturing step of the semiconductor integrated circuit device, following FIG. 6;

8 is a fragmentary cross-sectional view of the semiconductor substrate during a manufacturing step of the semiconductor integrated circuit device, following FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor substrate during a manufacturing step of the semiconductor integrated circuit device, following FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor substrate during a manufacturing step of the semiconductor integrated circuit device, following FIG. 9;

FIG. 11 is a process diagram of a main part of a manufacturing process of the semiconductor integrated circuit device.

FIG. 12 is a graph showing the annealing temperature dependency of the contact resistance between the wiring and the p ^{+ -type} semiconductor layer in the connection hole.

FIG. 13 is a graph showing the dependence of junction leakage current on annealing temperature.

14A is a graph showing a forward current-voltage characteristic of the Schottky barrier diode, and FIG. 14B is a graph showing a reverse current-voltage characteristic of the Schottky barrier diode.

FIG. 15 is a cross-sectional view of the silicide layer after annealing observed by SEM.

FIG. 16 is a cross-sectional view of an interface between a base metal film after annealing and a semiconductor substrate observed by TEM.

FIG. 17 is a graph showing an X-ray diffraction spectrum of a silicide layer.

18 (a) to (c) show ESCA of a silicide layer.
It is a graph which shows a spectrum.

FIG. 19 is an explanatory diagram showing a model of silicidation of a base metal film.

[Explanation of symbols]

1 semiconductor substrate 2 field insulating film 3 channel stopper layer 4 p-channel MOS · FET 5 semiconductor layer 5a p-type semiconductor layer 5b p ⁺ -type semiconductor layer 5c p ⁺ -type semiconductor layer 5d n ⁺ -type semiconductor layer 6 gate insulating film 7 a gate electrode 7a conductor film 7b conductor film 8 spacer 9 interlayer insulating film 10 wiring 10a base metal film 10a ₁ metal film 10b conductor film 11 connection hole 11a connection hole 11b connection hole 11c connection hole 12 silicide layer (compound layer) 13n n well 13p p well Reference Signs List 14 Insulating film 15 n-channel MOS • FET 16 Schottky barrier diode 17 Silicide layer P pMOS formation region N nMOS formation region S Schottky barrier diode formation region

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 (72) Inventor Yasushi Oka 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Microcomputer Systems, Inc. (72 ) Inventor Yasuko Yoshida 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Musashi Factory, Hitachi, Ltd. (72) Inventor Ryo Haruta 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Musashi, Ltd. Inside the factory (56) References JP-A-61-296764 (JP, A) JP-A-2-66973 (JP, A) JP-A-4-37167 (JP, A) (58) Fields investigated (Int. . ^7, DB name) H01L 21/28 - 21/288 H01L 21/44 - 21/445 H01L 29/40 - 29/43 H01L 29/47 H01L 29/872 H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (4)

(57) [Claims] A step of partially removing an insulating film on the semiconductor substrate to expose a part of the semiconductor substrate; and forming an alloy of a group IVa metal and a metal other than the group IVa metal on the entire surface of the semiconductor substrate. A step of depositing a film, annealing the semiconductor substrate, compounding each constituent atom of the alloy film and the semiconductor substrate at a contact portion between the alloy film and the semiconductor substrate, Forming a compound layer to be epitaxial by sputtering. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1 , wherein said group IVa metal is any of Ti, Zr or Hf, and said metal other than said group IVa metal is W, Mo or Ta. A method for manufacturing a semiconductor integrated circuit device. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein said alloy film is TiW, and the amount of Ti is not less than 15 atm% and not more than 60 atm%. Method. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the annealing temperature is not lower than 600 ° C. and not higher than 700 ° C. Manufacturing method.