JP3151966B2 - Bus controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control device for performing internal communication via a bus for control and monitoring purposes.

[0002]

2. Description of the Related Art A conventional bus control device includes a device internal bus for transmitting control monitoring information and timing information inside the device, and a busy (B) signal indicating that the internal bus is occupied.
USY) has a plurality of device units connected to a busy signal line for transmitting a signal, and each device unit is connected to an input / output port for inputting / outputting information by connecting to an internal bus of the device, and connecting to a busy signal line. Signal detection circuit that detects a busy signal, a busy signal output circuit that outputs a busy signal to a busy signal line when the unit occupies the internal bus of the device, and receives busy signal state information from the busy signal detection circuit An input / output control circuit for transmitting control information to the input / output port, and an input information determination circuit for determining only a correctly received information by performing a transmission error determination of input information from the input / output port and an address determination based on a physical address. ing.

[0003]

In this conventional bus control device, information on whether or not a certain unit in the device occupies the internal bus is controlled only by a busy signal. When the unit in the device tries to use the device internal bus at the same time, there is a possibility that information will collide in the device internal bus, and if the priority to use the device internal bus is set to avoid this, However, there is a problem that the unit in the device having a low priority has a long waiting time until the internal bus of the device can be used.

[0004]

The bus control device of the present invention transmits an internal bus for transmitting control monitoring information and timing information inside the device and a busy signal indicating that the internal bus is occupied. An input / output port connected to the internal bus of the device for inputting / outputting the control monitoring information and the timing information; and a busy signal detection connected to the busy signal line and detecting the busy signal. A busy signal output circuit that outputs the busy signal to the busy signal line when the own unit occupies the internal bus of the device; and a busy signal from the own unit that receives the busy signal from the busy signal detection circuit. An input / output control circuit for generating control information for instructing a signal output wait timing, and transmission of input information from the input / output port An input information determination circuit that performs error determination and address determination based on a physical address and extracts only correctly received information; and a priority indication according to output priority information set by provisioning and response request information from the input information determination circuit. A priority control circuit for generating control information; an address input circuit for generating address control information in accordance with the physical address; and an input / output control circuit, the priority control circuit, and a control circuit in response to each control information from the address input circuit. And a timer circuit for controlling the time from when another unit releases the occupation of the internal bus to when the own unit outputs the busy signal indicating that the own unit occupies the internal bus. It has a unit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The bus control device according to the present embodiment includes a device internal bus 1 for transmitting control and monitoring information and timing information inside the device.
And a plurality of in-device units 12 connected to a busy signal line 2 for transmitting a busy (BUSY) signal indicating that the device internal bus is occupied. An input / output port 3 connected to the bus 1 for inputting / outputting information, a busy signal detection circuit 4 connected to the busy signal line 2 for detecting a busy signal, and a case where the device unit 12 occupies the device internal bus 1. A busy signal output circuit 5 for outputting a busy signal to the busy signal line 2, a timer circuit 10 for receiving the status information of the busy signal from the busy signal detecting circuit and setting the input / output port 3 and the timing of waiting for the busy signal output. An input / output control circuit 6 for transmitting control information to the input / output port 3 and a transmission error determination of input information from the input / output port 3 and an address determination based on a physical address are performed, and only correctly received information is determined. An input information judging circuit 7 for outputting, a priority control circuit 8 for transmitting control information to a timer circuit 10 in accordance with output priority information set by provisioning and response request information from the input information judging circuit 7, and a physical address. Address input circuit 9 for transmitting control information to timer circuit 10, input / output control circuit 6, priority control circuit 8, and address input circuit 9
A timer for controlling the time from when another device unit 12 releases the occupation of the device internal bus 1 to when it outputs a busy signal indicating that it owns the device internal bus 1 in response to the control information from And a circuit 10.

FIG. 2 shows a signal timing chart in the embodiment of FIG. Through the priority control circuit 8 and the address input circuit 9, the longer timer value is set among the two internal units 12 in which the different busy signal output wait timer values are set according to the provisioning or physical address information. When the in-device unit 12 receives a command requesting a response from the in-device units 12 other than the two in-device units 12, the input information determination circuit 7 is The response information request is transmitted to the priority control circuit 8, and the output priority control circuit 8 transmits, to the timer circuit 10, information for shortening the timer value waiting for the busy signal output. The timer circuit 10 changes the timer value (t1) of the busy signal output waiting set by the provisioning or the physical address information to the other internal unit 1 which has not received the response request command.
By setting the timer to be shorter than the timer value (t2) set in step 2, even if there is a request to occupy the internal bus 1 at the same time in the other internal unit 12 which has not received the response request command. , The response output of the in-device unit 12 that has received the command is prioritized. Also,
When a fault is detected and reported at the same time in the two internal units 12, the internal bus 1 is used in accordance with different busy signal output wait timer values set by provisioning or physical address information. Therefore, the failure information of each device unit 12 can be transferred to the other device units 12 without colliding information on the device internal bus 1.
Can report to

[0008]

As described above, according to the present invention, it is possible to set a priority order for occupying the internal bus of each device for each unit in the device, and in the case of sending a response, the unit in the device. Since it is possible to raise the priority, there is no possibility that information will collide on the internal bus when a plurality of internal units try to use the internal bus at the same time, and when a response is sent. Even in a low-priority unit in the device that uses the device internal bus, there is an effect that the waiting time until the device internal bus can be used is not prolonged.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a signal timing diagram of one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Device internal bus 2 Busy signal line 3 I / O port 4 Busy signal detection circuit 5 Busy signal output circuit 6 I / O control circuit 7 Input information judgment circuit 8 Priority control circuit 9 Address input circuit 10 Timer circuit 12 Unit in device

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 13 / 362,13 / 368 G06F 13 / 372,13 / 376

Claims (1)

(57) [Claims] 1. A device internal bus for transmitting control monitoring information and timing information inside the device, and a busy signal line for transmitting a busy signal indicating that the device internal bus is occupied. An input / output port connected to the device internal bus for inputting / outputting the control monitoring information and the timing information; a busy signal detection circuit connected to the busy signal line for detecting the busy signal; and the own unit occupying the device internal bus A busy signal output circuit for outputting the busy signal to the busy signal line, and control information for receiving the busy signal from the busy signal detection circuit and instructing the output wait timing of the busy signal from the own unit. An input / output control circuit for generating an error, and a transmission error determination of input information from the input / output port and an address based on a physical address. An input information determination circuit that makes a determination and extracts only correctly received information; and a priority control that generates priority instruction control information according to output priority information set by provisioning and response request information from the input information determination circuit. A circuit, an address input circuit for generating address control information according to the physical address, and another unit inside the device according to each control information from the input / output control circuit, the priority control circuit, and the address input circuit. A plurality of internal units each having a timer circuit for controlling the time from when the bus occupation is released to when the own unit outputs the busy signal indicating that the own unit occupies the internal bus. Bus control device characterized.