JP3150496B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a structure of a semiconductor memory device using a dynamic RAM (DRAM).

[0002]

2. Description of the Related Art In recent years, semiconductor storage devices have been steadily becoming higher in integration and larger in capacity, and MOS dynamic RAMs (DRA) comprising MOSFETs and MOS capacitors have been developed.
M) is also studying the miniaturization of the memory cell.

With the miniaturization of such memory cells, the area of a capacitor for storing information (charge) is reduced. As a result, the memory contents are erroneously read or the memory contents are destroyed by α rays or the like. Soft errors are a problem.

As one method for solving such a problem and achieving higher integration and higher capacitance, the occupation area of the capacitor is substantially increased without increasing the occupation area, and the capacitance of the capacitor is increased. Various methods have been proposed to increase the amount of stored electric charge.

As one of the methods for realizing a DRAM of 64 mega or less, a stacked DRAM in which a storage electrode is formed on a bit line and a capacitor area can be ensured.
A memory cell has been proposed, but to increase the capacity after 1 G, it is necessary to use two self-alignment steps of forming a bit line contact and forming a storage node contact. Man-hours such as formation of a film are greatly increased, and the expansion of the diffusion layer of the transistor due to the accompanying heat process cannot be suppressed. In the worst case, the transistor may not be able to operate. .

As a method for solving this problem, there has been proposed a buried electrode type (hereinafter referred to as concave) transistor in which a trench is formed in a substrate surface and a transistor is formed in the trench. When this concave transistor is used, the contact can be easily formed, but there is a problem that the driving capability of the transistor is low due to an increase in channel resistance due to an increase in channel length. Therefore, it is not suitable for high-speed operation, and a conventional planar transistor must be used for a circuit requiring high speed, such as a peripheral driving circuit or a signal processing circuit. However,
However, there is a problem that simply changing the transistors in the cell portion and the peripheral circuit portion increases the number of steps.

[0007]

As described above, the conventional DR
In the AM cell structure, when a concave transistor is used in the cell portion, if the transistor in the peripheral circuit portion is configured by a conventional planar transistor, there is a problem that the number of steps is increased and the device is not practically suitable. .

[0008] The present invention has been made in view of the above circumstances, and when a concave transistor is used in a cell portion,
An object is to form a transistor in a peripheral circuit portion as a high-speed device without increasing man-hours.

[0009]

Therefore, according to the present invention, a concave transistor is formed on the transfer gate of the cell portion, the cell portion is completely flattened, and the gate of the peripheral circuit is formed on the same wiring layer as the bit line of the memory cell. A transistor having electrodes is formed, and a storage node contact is formed in a self-aligned manner with the bit line.

[0010] Preferably, the plate electrode of the capacitor in the cell portion is formed in the same layer as the wiring layer of the peripheral circuit.

Preferably, the bit line and the passing word line are formed so as to avoid the diffusion layer formation region.

[0012]

According to the above structure, the concave portion is used in the cell portion to improve the reliability of the diffusion layer, and the bit line in the cell portion is used as the gate electrode in the peripheral circuit portion. Therefore, the peripheral circuit portion can be a planar transistor that does not hinder high-speed operation without increasing the number of steps.

Further, if the plate electrode of the capacitor in the cell portion is formed in the same layer as the wiring layer of the peripheral circuit, the number of steps for forming the peripheral circuit is further reduced.

Further, if the bit line and the passing word line are formed so as to avoid the diffusion layer formation region, the storage node contact can be easily formed even when the bit line and the word line are formed in advance.

Further, if the element region is formed so as not to cross the bit line except for the contact region, it is possible to prevent the formation of a capacitance between the bit line and the diffusion layer.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

As an embodiment of the semiconductor memory device of the present invention,
A DRAM using a concave transistor will be described. 1, 2 (a), 2 (b) and 2 (c) are a plan view of a DRAM according to an embodiment of the present invention, a sectional view taken along line AA of FIG.
1 shows a B sectional view and a sectional view of a peripheral circuit.

In this DRAM, a memory cell comprising a concave transistor and a capacitor formed thereon is formed on the surface of an n silicon substrate 1 and formed in the same step as the bit line 9B of the memory cell portion. The gate electrode 9G of the peripheral circuit portion is formed by the polycide layer 9 described above.

That is, in this DRAM, a shallow trench 4 is formed in an element region 3 which is insulated and separated by a trench 2 filled with a silicon oxide film so as to form an L-shape. Is filled with a gate electrode 6 via a gate insulating film 5, and a p-type diffusion layer 7 as a source / drain is formed in the trench 4 in a self-aligned manner to form a MOSFET.
A bit line contact 8 is formed so as to be connected to one side of p type diffusion layer 7, a bit line 9B having a polycide structure including polycrystalline silicon film 9a and tungsten silicide 9b is formed, and a side wall of bit line 9B is formed. A storage node contact 11 is formed in a self-aligned manner with the bit line 9B via the covering sidewall insulating film 10, and the storage node electrode 12 and the capacitor insulating film 1 are formed above the bit line 9B.
3. A capacitor composed of the plate electrode 14 is formed to construct a memory cell. On the other hand, in the peripheral circuit part, as shown in FIG. 2C, a polycide wiring formed in the same step as the bit line 9B of the transistor in the memory cell part constitutes a gate electrode 9G. A p-type diffusion layer 17 as a source / drain is formed in a consistent manner to constitute a MOSFET. Here, the tungsten film forming the plate electrode 14 in the memory cell portion is used as the wiring layer 14C.

Next, the manufacturing process of this DRAM will be described. In the following steps, (a) shows a cross-sectional view of a memory cell portion, and (b) shows a cross-sectional view of a peripheral circuit portion.

First, as shown in FIGS. 3A and 3B, a silicon oxide film s is formed on the surface of an n-type silicon substrate 1 having a specific resistance of about 5 Ωcm, and then a silicon nitride film pattern formed by a CVD method. Is used as a mask to form a trench 2 in each memory cell region by etching by a reactive ion etching method. This is filled with a silicon oxide film to form an element isolation region. Here, the depth of this trench is about 5 μm. Then, a trench mask is newly formed and etched by a reactive ion etching method to form concave trenches 4 in each memory cell region.

Next, as shown in FIGS. 4 (a) and 4 (b), after the surface treatment of the concave trench 4 is performed, the surface is oxidized to form a gate insulating film 5. A gate electrode 6 made of a silicon film is buried.
Here, the height of the gate electrode is set lower than the surface of the substrate so that the gate electrode is completely buried. Then, a silicon oxide film 12 is formed thereon by the CVD method. After that, the mask M is peeled off, a silicon oxide film is formed on the surface, and this is used as the gate insulating film 15 in the peripheral circuit portion. Then, in order to protect the gate insulating film 15 in the peripheral circuit portion, a polycrystalline silicon film 16 is formed on the entire surface, and further the silicon oxide film 12 is patterned with the surface, and then the diffusion layer 7 is formed. Thereafter, a bit line contact 8 is further formed on the polycrystalline silicon film 16, and a polycide layer 9 composed of a polycrystalline silicon 9a and a tungsten silicide film 9b is formed. This is later used as the bit line 9B in the memory cell section and as the gate electrode 9G in the peripheral circuit section (FIGS. 5A and 5B).

Further, as shown in FIGS. 6 (a), 6 (b) and 6 (c), a silicon oxide film 20 is deposited on the entire surface by the CVD method, and the bit lines 9 are formed using the resist pattern as a mask.
B is patterned and the gate electrode of the peripheral circuit is patterned to form a diffusion layer 17 in the peripheral circuit. Thereafter, the surface is covered with a silicon nitride film 10, and is patterned by anisotropic etching so that the silicon nitride film 10 remains on the side wall of the gate electrode in the peripheral circuit portion, thereby forming a side wall insulating film. Diffusion is performed again to the memory cell portion and the peripheral circuit portion to perform p diffusion of the LDD structure.
A mold diffusion layer 17 is formed.

Thereafter, FIGS. 7A and 7B and FIG.
As shown in (c), a silicon oxide film 20 and a silicon nitride film 20s are formed on the surface by the CVD method, and etch back is performed to flatten the surface. Then, the storage node contact 11 is opened.

FIGS. 8 (a) and 8 (b) and FIG. 8 (c)
As shown in FIG. 1, a storage node electrode 12 made of a polycrystalline silicon film is formed, a capacitor insulating film 13 made of a silicon nitride film is further formed thereon, and a tungsten film is deposited on the entire surface to a thickness of about 600 nm. By etching and patterning by a method, a plate electrode 14 serving as a cell plate is formed, and a wiring layer 14C is formed in a peripheral circuit portion. Note that the capacitor insulating film is not limited to one silicon nitride film,
In addition to a stacked structure of silicon nitride and silicon oxide, a silicon oxide film, a metal oxide film such as Ta ₂ O _{5, a} silicon nitride film, or a combination thereof can also be used.

Further, as shown in FIGS. 9A, 9B and 9C, an interlayer insulating film 22 is formed. Thereafter, a contact 21 is formed so as to contact the source / drain of the peripheral circuit portion, and the aluminum wiring 23 of the peripheral circuit portion is formed.
And plate wiring 2 in the memory cell portion.
3P is formed. Then, a surface protection film is formed to complete the DRAM shown in FIG.

As described above, when the concave transistor is formed in the memory cell portion, a planar transistor can be formed in the peripheral circuit portion without increasing the number of steps.

In the above embodiment, the plate electrode of the cell portion and the contact wiring to the diffusion layer of the peripheral circuit are formed in the same step. However, it goes without saying that the plate electrode may be formed in another configuration.

In the above embodiment, the element region is formed to have an L-shape. However, the intersection region with the bit line occupies two-thirds of the element region. is there. Therefore, as shown in FIG. 10, the element regions 3 may be formed obliquely and intersect only in the bit line contact regions. Also, as shown in FIG.
It may be formed in a character shape or in a step shape as shown in FIG.

The layout of the bit lines 9B when the element regions are formed obliquely as shown in FIG. 11 is shown in FIGS. 13 and 14 as conceptual diagrams, and FIGS. 15 and 16 show an example of a plane pattern and a sectional view thereof. By doing so, the input and output can be at the same position. In this way, a DRAM having good characteristics and high reliability can be formed even when miniaturization is performed. Here, 6F ² (2F × 3F) (F:
An example of the pattern of the cell size of the minimum design rule) is shown.

By forming the element region and the bit line so as not to overlap with each other, the capacitance can be reduced, and a fine DRAM having excellent characteristics can be provided.

[0032]

As described above, according to the present invention, a high-speed and highly-reliable semiconductor device can be easily formed without increasing the number of steps.

[Brief description of the drawings]

FIG. 1 is a plan view showing a DRAM according to an embodiment of the present invention.

FIG. 2 is a sectional view of a DRAM according to an embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the DRAM according to the embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the DRAM according to the embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the DRAM according to the embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of the DRAM according to the embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of the DRAM according to the embodiment of the present invention.

FIG. 8 is a manufacturing process diagram of the DRAM according to the embodiment of the present invention.

FIG. 9 is a manufacturing process diagram of the DRAM according to the embodiment of the present invention.

FIG. 10 is a diagram showing a modification of the present invention.

FIG. 11 is a diagram showing a modification of the present invention.

FIG. 12 is a diagram showing a modification of the present invention.

FIG. 13 is a diagram showing a modification of the present invention.

FIG. 14 is a diagram showing a modification of the present invention.

FIG. 15 is a diagram showing a modification of the present invention.

FIG. 16 is a diagram showing a modification of the present invention.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 element isolation region 3 element region, 4 trench 5 gate insulating film 6 gate electrode 7 diffusion layer 8 bit line contact 9B bit line 9G gate electrode 11 storage node contact 12 storage node electrode 13 gate insulating film. 14 plate electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (4)

(57) [Claims] 1. A memory cell section comprising a cell array comprising a buried electrode transistor having a transfer gate formed in a trench formed on a surface of a substrate, and a capacitor connected to one of diffusion layers of the transistor. A peripheral circuit portion having a planar transistor connected to the memory cell portion to drive the memory cell portion, wherein a bit line of the memory cell portion is formed of the same conductor layer as a gate electrode of the peripheral circuit; A storage node contact formed in a self-aligned manner. 2. The semiconductor device according to claim 1, wherein the plate electrode forming the capacitor is formed in the same layer as a wiring layer of a peripheral circuit. 3. The semiconductor device according to claim 2, wherein the wiring layer of the peripheral circuit is a gate electrode. 4. The semiconductor device according to claim 1, wherein the bit line and the element region cross only at a bit line contact region.