JP3149296B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory having a plurality of memory words for respectively storing a plurality of stored data.

[0002]

2. Description of the Related Art Conventionally, in an ordinary semiconductor memory, address data is input, and stored data stored in a memory word to which the address is assigned is read. On the other hand, an associative memory having a function of inputting search data from the outside and searching for a memory word in which stored data having a bit pattern matching all or a predetermined part of the search data is stored. Associative
e Memory, Content Addressable Memory; Conte
nt Addressable Memory) has been proposed.

Hereinafter, this associative memory will be described in some detail. FIG. 2 is a circuit block diagram illustrating an example of the associative memory. The associative memory 10 has memory words 13_1, 13_2,.
3_n and address data AD, and memory words 13_1, 13_2,..., 13 corresponding to the address.
_N are activated through buffers 12_1, 12_2,..., 12_n.
, 11_n are provided.

The associative memory 10 has flag registers 14_1, 14_2,..., 14_n corresponding to the respective memory words 13_1, 13_2,. When search data REF_DATA is input from outside, the input search data REF_DATA,
The respective stored data stored in the memory words 13_1, 13_2,..., 13_n are compared with each other, and when they match, “1” is stored in the corresponding flag register, and “0” is stored in the corresponding flag register when they do not match. Is stored. In the comparison of the match / mismatch, some bits may be masked (considered as a match).

The associative memory 10 is further provided with a priority encoder 15. The priority encoder 15 has a plurality of flag registers 1
4_1, 14_2,..., 14_n is a circuit for generating an address of a memory word corresponding to a flag register having the highest priority among flag registers storing "1". Assuming that the priority is higher, the address of the memory word 13_2 corresponding to the flag register 14_2 having the highest priority among the flag registers storing "1" is generated.

The address data AD output from the priority encoder 15 is transferred to the decoder 1 if necessary.
, 11_n, the memory word 13_2 becomes active, and the data stored in the memory word 13_2 is output data READ_DATA.
Is output as

[0007]

In recent years, it has been demanded that a semiconductor memory be provided with various search functions, for example, as in the above-mentioned associative memory. A function to search for a minimum value is required. Performing this search using a conventional semiconductor memory requires operations such as reading stored data stored in the address in the address order from the semiconductor memory and performing successive comparisons with the CPU, which takes time. Was.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor memory having a function of searching for maximum or minimum storage data or an address at which the storage data is stored.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor memory comprising: (1) a plurality of memory words arranged for storing respective storage data; and (2) a plurality of memory words. The value of the input reference data provided in correspondence with the value of the stored data stored in the corresponding memory word is compared, and the data having the larger value is arranged as new reference data on the lower side. And a plurality of comparison circuits for outputting to the selected memory words.

[0010] The first semiconductor memory further, (3) the plurality of provided in correspondence to the comparison circuits, respectively, a plurality of flag registers (4) which is set in accordance with the comparison result of the comparison circuit the An address encoder that outputs address data of a memory word storing storage data having a maximum value among a plurality of storage data stored in the plurality of memory words according to a set state of the plurality of flag registers; you.

A second semiconductor memory according to the present invention that achieves the above object is: (5) a plurality of memory words arranged for storing respective storage data; and (6) a plurality of memory words corresponding to the plurality of memory words. The input reference data and the stored data stored in the corresponding memory word are compared with each other, and the smaller data is compared as a new reference data in the memory word arranged on the lower side. A plurality of comparison circuits that output the signals to the plurality of comparison circuits.

[0012] Also in this second semiconductor memory, the above-mentioned 1
As in the case of the semiconductor memory of (1), in addition to the above (5) and (6), (7) a set provided in correspondence with each of the plurality of comparison circuits, in accordance with a comparison result in the comparison circuit. (8) A memory word in which stored data having a minimum value among a plurality of stored data stored in the plurality of memory words is stored according to a set state of the plurality of flag registers. that having a address encoder for outputting the address data.

In the first and second semiconductor memories of the present invention, the maximum value and the minimum value of the stored data stored in all of a large number of memory words constituting the semiconductor memory may be searched. Good, but not limited to this, a part of a plurality of memory words constituting the semiconductor memory, a plurality of memory words are referred to as the plurality of memory words according to the present invention, and only those memory words are searched. Is also good.

In the present invention, as the address encoders of the above (4) and (8), for example, priority encoders having various structures used for an associative memory or the like can be used. As described above, the present invention includes elements common to an associative memory and the like, and therefore, the present invention may be incorporated into a semiconductor memory such as an associative memory.

[0015]

The first semiconductor memory according to the present invention, as described in (2) above, comprises comparison circuits corresponding to each memory word, and these comparison circuits sequentially send data having a large value to the lower side. Therefore, the storage data having the maximum value is output from the lowermost comparison circuit.

Also, the first semiconductor memory of the present invention described above.
Is provided with the flag register and the address encoder of the above (3) and (4), so that the address of the memory word storing the storage data having the maximum value can be known. Further, the second semiconductor memory of the present invention comprises:
As described in the above (6), since the comparison circuits corresponding to the respective memory words are provided, and these comparison circuits sequentially transmit data having a small value to the lower side, the lowest comparison circuit has a minimum value. The stored data having a value is output.

Further, the second semiconductor memory of the present invention
Is provided with the flag registers and the address encoders of (7) and (8) as in the case of the first semiconductor memory described above , so that the memory word storing the storage data having the minimum value is stored. You can know the address of.

[0018]

Embodiments of the present invention will be described below. FIG. 1 is a block diagram showing a configuration of an associative memory including a configuration of a semiconductor memory according to an embodiment of the present invention. The blocks corresponding to the blocks constituting the associative memory shown in FIG. 2 are denoted by the same reference numerals as those shown in FIG. 2, and only the differences will be described.

The associative memory shown in FIG. 1 includes comparison circuits 16_1, 16_2,..., 16_n corresponding to the respective memory words 13_1, 13_2,. Each of the comparison circuits 16_1, 16_2, ..., 16_
n is the data input from the higher-order comparison circuit and the corresponding memory words 113_1, 13_2, ..., 13_n
Is compared with the stored data, and the larger one of the two data is input to a lower-side comparison circuit.
When the stored data of 3_1, 13_2,..., 13_n is larger, the corresponding flag register among the flag registers 14_1, 14_2,. .

These comparison circuits 16_1, 16_2,
, 16_n, the start data START_DATA having a small value is input to the uppermost comparison circuit 16_1, and the comparison circuits 16_1, 16_2,..., 16_n sequentially perform a comparison operation. Is output as the maximum data MAX_DATA. At this time, the memory word 13_n corresponding to the flag register (in the illustrated case, the flag register 14_2, 14_n−1 in the lowermost stage (in the illustrated case, the flag register 14_n−1) in which the “1” is stored. −
This means that the storage data of the maximum value is stored in 1. Therefore, assuming that the lower the flag register in the associative memory 15 is, the higher the priority is, the memory word storing the storage data of the maximum value from the priority encoder 15 (the memory word 13_ in the illustrated case).
The address data of (n-1) is output.

Thus, in the associative memory shown in FIG.
.., 13_n, the stored data having the maximum value and the address of the memory word in which the stored data is stored can be obtained. Here, each of the comparison circuits 16_1, 16_2,
, 16_n are configured to transmit the smaller value data of the two input data to the lower-side comparison circuit, and the corresponding memory words 13_1, 13_2,
,..., 14_n corresponding to the case where the data stored in.
Is set to "1", an associative memory is obtained which obtains the storage data having the minimum value and the address of the memory word in which the storage data is stored.

Although each of the above embodiments is incorporated in an associative memory, it goes without saying that the present invention can be constructed independently of an associative memory.
Although the above embodiment is an example in which both the data having the maximum value or the minimum value and the storage address thereof are obtained, if it is sufficient to determine only the maximum value or the minimum value, the flag registers 14_1, 14_2,. And the priority encoder 15 is unnecessary, and only the storage address of the data having the maximum value or the minimum value needs to be known, or the maximum value or the minimum value can be known only after inputting the storage address to the decoder. In this case, as shown in FIG. 1, data from the lowest comparison circuit 16_n (in FIG. 1, maximum value data MAX_DAT).
The output of A) is unnecessary.

Further, in the above embodiment, the associative memory for obtaining either the maximum value or the minimum value has been described. However, both the maximum value and the minimum value can be obtained by switching the mode of the circuit. You may comprise.

[0024]

As described above, the semiconductor memory of the present invention includes the respective comparing circuits corresponding to the respective memory words.
The larger data or the smaller data is sequentially sent to the lower comparison circuit while operating the flag by comparing the magnitudes of the two input data, and the maximum value of the stored data or You can get the minimum value or its address.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an associative memory including a configuration of an embodiment of a semiconductor memory of the present invention.

FIG. 2 is a circuit block diagram illustrating an example of an associative memory.

[Explanation of symbols]

 11_1, 11_2,..., 11_n Decoders 12_1, 12_2,..., 12_n Buffers 13_1, 13_2,.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G11C 15/00-15/06 G06F 7/00 WPI (DIALOG)

Claims (2)

(57) [Claims] 1. A plurality of memory words arranged to store respective storage data, input reference data provided corresponding to each of the plurality of memory words, and stored in a corresponding memory word. a plurality of comparator circuits that output to the memory word arranged in the lower side by comparing the magnitude of the value of the stored data the larger data value as a new reference data, corresponding to each of said plurality of comparator circuits Provided
A plurality of sets that are set according to the comparison result
A flag register, and a plurality of flag registers,
Of multiple stored data stored in multiple memory words
Memory memory in which stored data having the largest value is stored.
Address encoder that outputs
Semiconductor memory, comprising a. 2. A plurality of memory words arranged for storing respective stored data, input reference data provided corresponding to each of the plurality of memory words, and stored in a corresponding memory word. a plurality of comparator circuits that output to the memory word arranged in the lower side as a storage data and the values of large and small new reference data to data of the small <br/> have how compared with values, said plurality A plurality of flag registers provided corresponding to the respective comparison circuits, and set in accordance with a comparison result in the comparison circuit; and stored in the plurality of memory words in accordance with a set state of the plurality of flag registers. half, characterized in that it comprises an address encoder for storing data having a minimum value among the plurality of stored data to output the address data stored memory word Body memory.