JP3148803B2 - Sound source device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone generator for generating and outputting digital musical tone waveform data.
The present invention relates to a sound source device capable of executing both a recording waveform process and a reproduction waveform process in parallel using one DSP.

[0002]

2. Description of the Related Art Various types of tone generators have been known. The tone generated by such a sound source device is D
The sound is emitted after applying an effect by an SP (Digital Signal Processor).

[0003]

On the other hand, there has been known such a sound source device in which an external musical tone is sampled, stored (recorded) in a waveform memory, and used for generating a musical tone. To sample musical tones, a tone generator is usually provided with a sampling circuit for taking in external musical tones.

[0004] In recent years, there has been a growing demand for functions of the sound source device, and there has been a demand for improving the functions of the sound source device without complicating the structure of the device. However, without complicating the configuration of the apparatus, sampling is performed during sound generation, or waveform data once sampled and written to the waveform memory is read, an effect is applied, and resampling is performed to write the waveform data to the waveform memory again. I couldn't do that. That is, it was not possible to perform both the recording waveform processing and the reproduction waveform processing without complicating the configuration of the apparatus.

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to perform both recording waveform processing and reproduction waveform processing in a sound source device of various types without making the device configuration so complicated.

[0006]

To achieve this object, a sound source device according to the first aspect of the present invention records a tone waveform.
And a plurality of channels at a predetermined sampling period.
Waveform supply means for supplying musical tone waveforms for channels, and supply
Processing means for performing signal processing on the selected tone signal
And a plurality of channels supplied from the waveform supply means.
Musical tone waveform and musical tone supplied from the signal processing means
Input signals and mix appropriately to obtain mixing results
By executing the processing in a plurality of series, at least the first,
Obtain and output the second and third mixing results respectively
Mixing means, and an output from the mixing means.
For writing the first mixing result to be stored in the storage means
Writing means, and a second output from the mixing means.
The result of mixing to an external sound system
Output means, and the signal processing means
The tone signal of the third mixing result is supplied,
Signal processing means for the tone signal resulting from the third mixing.
Signal processing for recording or signal processing for playback.
And features.

[0007]

[0008]

[0009]

[0010]

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall block configuration of an electronic musical instrument to which a tone generator according to the present invention is applied. FIG. 2 shows FIG.
2 shows a detailed block configuration of the sound source section of FIG. In the drawings described below, the same reference numerals denote the same components.

Referring to FIG. 1, the overall configuration of the electronic musical instrument will be described. The electronic musical instrument includes a keyboard 101, a display unit 10
2. Switch group (SW) 103, central processing unit (CP)
U) 104, read-only memory (ROM) 105, random access memory (RAM) 106, external storage device 107, tone generator 108, waveform memory 109, external circuit 1
10, delay memory 111, digital-to-analog converter (DAC) 112, sound system (SS) 113,
And a bus line 114. Keyboard 101, display unit 102, switch group 103, CPU 104, ROM
The 105, the RAM 106, the external storage device 107, and the tone generator 108 are mutually connected by a bus line 114.

The keyboard 101 is a keyboard provided with a plurality of keys for a user to perform a performance operation. The display unit 102 is provided on a panel of the electronic musical instrument and displays various information. The switch group 103 is provided on a panel,
By operating this, the user can give various instructions to the electronic musical instrument. The CPU 104 controls the operation of the entire electronic musical instrument. In particular, during a normal performance, an operation of the keyboard 101 is detected, and a sounding instruction is issued to the sound source unit 108 in accordance with the operation. ROM 105 is a CPU
(A sound source control program for controlling the sound source unit 108) and various constant data are stored. The RAM 106 is used for a work register or the like. The external storage device 107 includes a DRAM described later.
Waveform data to be loaded and the like are stored in the configured waveform memory 109.

The tone generator 108 reads out waveform data (waveform samples) from the waveform memory 109 in accordance with an instruction from the CPU 104, and performs interpolation, envelope addition (volume change control), channel accumulation (mixing), and effect (effect). Processing such as adding is performed and output as musical sound waveform data. The tone waveform data output from the sound source unit 108 is converted into an analog signal by the DAC 112,
The sound is emitted by the sound system 113.

The waveform memory 109 is constituted by a DRAM (Dynamic RAM). Waveform memory 109
Stores waveform sample data sampled at a predetermined rate. One waveform sample is in a 16-bit uncompressed format, and an address is assigned to each waveform sample. That is, one waveform sample can be read by one access. The waveform samples are read from the external storage device 107 prior to the generation of musical tones and read from the waveform memory 1.
09 may be stored, but in the sound source of this embodiment, in particular, empty time slots that have not been used when performing the operation of generating musical tones for a plurality of channels can be used for another purpose. Therefore, the waveform data may be read out from the external storage device 107 and stored in the waveform memory 109 using the empty time slot during the tone generation operation.

The external circuit 110 will be described later in detail. The delay memory 111 is a delay memory used in a signal processing circuit (DSP) in the sound source unit 108.
When performing a process such as adding an effect to a musical tone waveform, for example, data at a certain timing is written into the delay memory 111 and read out after a predetermined clock and used for calculation. 1
11 is used.

Referring to FIG. 2, the sound source section 108 will be described in detail. 2, the tone generator 108 includes a control register 201, a read / write circuit 202, a volume change control circuit 203, a mixer 204, a signal processing circuit 205, and an interface 206. This sound source unit 108
Operate on 32 time-division channels. Control signals such as a control clock signal serving as a reference signal for performing a time-division operation and a channel count value for repeatedly counting 0 to 31 are supplied to each unit in the sound source unit 108.

In FIG. 2, the control register 201 stores C
Various kinds of designation information (sound source unit 10
8 is a control register for storing instructions and parameter information for the E.8. An X access circuit 304 for controlling X access processing is provided in the control register 201, which will be described later in detail. The CPU 104
Predetermined specified information is set in the control register 201 and a sound generation start instruction is issued. The designated information to be set includes an assigned channel, a waveform memory read pitch (frequency number), a waveform memory read section, an envelope parameter, setting information for the mixer 204, an effect coefficient, and the like.

When receiving a sound generation start instruction for a certain channel, the tone generator 108 starts the operation of generating a musical tone waveform. First, the read / write circuit 202 sequentially generates read addresses of the waveform memory 109. The read address is a value obtained by sequentially accumulating the designated read pitch from the beginning of the designated read section. In particular, in the tone generator 108, a waveform buffer (32 in FIG.
7), only the required number of waveform samples (waveform data) are read from the waveform memory 109 for each channel, and the number of times of access to the waveform memory in each channel can be varied. Therefore, the read / write circuit 202 sets the read address of the waveform sample according to the number of accesses necessary for each channel,
At a timing different from the time division channel timing,
They are output sequentially and sequentially. The read address generated by the read / write circuit 202 is stored in the waveform memory 10
9 so that the waveform samples are stored in the waveform memory 109 at a timing different from the time-division channel timing.
Is read from. The read / write circuit 202 receives this waveform sample, stores it in an internal waveform buffer, performs interpolation processing, and outputs it as musical sound waveform data.

As described above, the read / write circuit 202 is provided with a waveform buffer for buffering waveform samples, and reads out only a required number of waveform samples from the waveform memory 109 for each channel. You get slots. In the empty time slot, the read / write circuit 202 performs X access processing, which will be described later, that is, accesses the waveform memory 109 from the CPU 104 or returns the tone waveform data returned from the mixer 204 via the X access circuit 304 to the waveform memory 109. It operates so that writing can be performed.

The volume change control circuit 203 adds an envelope to the tone waveform data of each channel output from the read / write circuit 202 in a time division manner and outputs the resultant data. What kind of envelope is given is determined based on the envelope parameter given from the CPU 104 via the control register 201. Volume change control circuit 20 of FIG.
The addition of “32” to the output line 211 of No. 3 indicates that the output of the volume change control circuit 203 is equivalent to 32 channels in time division. Numerical values attached to the input / output lines of the other units also indicate the number of channels.

The mixer 204 includes a volume change control circuit 20
Musical sound waveform data for 32 channels output from 3,
Music waveform data for eight channels output from a signal processing circuit 205 described later and an external circuit 110 described later
8 output (via interface 206)
The tone waveform data for the channel is input to the input line 211,
Input via 212 and 213. The mixer 204 multiplies the musical tone waveform data of each channel input from each of these input lines by an appropriate coefficient (the coefficient value is given by the CPU 104 via the control register 201) to perform mixing. The output of the mixer 204 includes eight channels for the signal processing circuit 205, eight channels for the external circuit 110 (via the interface 206), and one channel for the X access circuit 304 in the control register 201.
Two channels (L and R outputs), which are final outputs of the sound source unit 108, are output to the DAC 112 via output lines 221, 222, 223, and 224, respectively. The mixer 204 can multiply the musical tone waveform data of an arbitrary channel input from an arbitrary input line by multiplying it by a designated coefficient and mix the result, and send the mixing result to an arbitrary channel of an arbitrary output line. Multiply the input of which channel of which input line by what coefficient, how to mix the multiplication result,
The output line to output the mixing result depends on the CP
It is determined based on the designation of U104.

The signal processing circuit 205 is a DSP that operates in accordance with a microprogram loaded in an internal microprogram memory. The signal processing circuit 205 performs signal processing on the tone waveform data from the mixer 204 independently for each channel, and Return to mixer 204 again. When performing signal processing, the signal processing circuit 205 obtains delayed data using the delay memory 111 as necessary. The microprogram executed by the signal processing circuit 205 is the CPU 1
04 loads appropriately. The function of the signal processing circuit 205 is defined by a microprogram to be loaded, but in brief, performs signal processing such as waveform processing at the time of sampling or resampling, or effect addition. The specific setting of the microprogram will be described later with reference to FIGS.

The external circuit 110 is, for example, an analog / digital converter (ADC) for taking in voices and musical sounds from the outside, an external DSP for effecting an effect, or a digital filter. The output from the mixer 204 to the external circuit 110 is equivalent to eight channels, and the input from the external circuit 110 to the mixer 204 is equivalent to eight channels. Since these are channels that can be used independently, a plurality of external circuits (of course, different Process 110) to any channel on any input / output line (via interface 206)
Can be connected. Note that “external” refers to the sound source unit 10.
8 means “external”, and the external circuit 110 may be provided in the electronic musical instrument of FIG. 1 or may be provided outside the electronic musical instrument of FIG.

As described above, the mixer 204 multiplies the musical tone waveform data of an arbitrary channel input from any one of the input lines 211 to 213 by a specified coefficient and mixes the resulting data.
Since the data can be transmitted to any channel of H.224, for example, the following processing can be performed.

Using an ADC as the external circuit 110,
An analog signal input from a microphone or the like is converted into a digital signal and input to the mixer 204. The mixer 204 converts the external tone signal into the sound source unit 108
Internally, waveform data is read out from the waveform memory 109 and mixed with a generated tone and output to an output line 224 to the DAC 112. If necessary, instead of outputting the output of the mixer 204 to the DAC 112, the output is once input to the signal processing circuit 205 or another external circuit 110, and the waveform of the effect imparting process or the like is generated using the signal processing circuit 205 or the other external circuit 110. After the processing is performed, the data may be output to the DAC 112.

It is possible to sample an external tone. That is, using an ADC as the external circuit 110, an analog signal input from a microphone or the like is converted into a digital signal and input to the mixer 204.
The mixer 204 mixes this external tone signal with a tone generated by reading out waveform data from the waveform memory 109 in the tone generator 108, for example, and outputs the resulting signal to an output line 223 to the X access circuit 304. The data is written to the waveform memory 109 via 202. If necessary, the output of the mixer 204 is input to the signal processing circuit 205 or the external circuit 110 instead of being output to the output line 223 to the X access circuit 304, and the effect imparting processing is performed using the signal processing circuit 205 or the external circuit 110. After performing such waveform processing as described above, the signal may be output to the X access circuit 304.

Resampling (processing of processing a waveform prepared on the waveform memory 109 by sampling or the like and writing the processed waveform into the waveform memory 109 again) can be performed. That is, waveform data stored in the waveform memory 109 by sampling or the like is read out using a predetermined tone generation channel of the read / write circuit 202 and input to the mixer 204. In some cases, resampling involves mixing and rewriting two or more waveforms.
The waveform data read out here is one or more waveform data. In the mixer 204, the tone signal is passed to the signal processing circuit 205 and the external circuit 110, and various waveform processing is performed as necessary, and the result is obtained. The mixer 204 having received the tone signal subjected to the waveform processing outputs the tone signal to an output line 223 to the X access circuit 304,
The data is written to the waveform memory 109 via the read / write circuit 202. Note that the first mixing result in the mixer 204 is not sent to the signal processing circuit 205 or the external circuit 110,
It may be supplied to the X access circuit 304 as it is.

Using a DSP or a digital filter as the external circuit 110, or using a signal processing circuit 205, effects processing and filtering processing are performed on the musical tone waveform extracted from the mixer 204, and the processing result is returned to the mixer 204. The mixer 204 mixes the processed musical sound waveform with a musical sound generated inside the sound source unit 108, and outputs an output line 224 to the DAC 112 and an X access circuit 3.
04 to the output line 223.

The above-mentioned is an example of processing that can be realized in the present embodiment. The processing time of the time-division processing in the sound source unit 108 can be secured, and the necessary microprogram can be loaded into the signal processing circuit 205. Then, various functions of the external circuit 110 and the signal processing circuit 205 including the above-mentioned are arbitrarily combined to perform processing on a musical tone waveform, output to the DAC 112, and output to the X access circuit 3.
04 to the read / write circuit 202 to return to the waveform memory 10
9 can be written.

FIG. 3 shows the control register 2 in the tone generator 108.
1 shows the detailed block configuration of the read / write circuit 202. In the circuit shown in FIG. 3, the control register 201 does not show all of the control registers, but shows a part of the control registers. Control register 20
1, other control data such as envelope parameters, mixer settings, and effect coefficients are also stored.

The control register 201 includes a register 301,
It includes a register 302, a priority flag 303, and an X access circuit 304. Registers 301 and 302
Stores various kinds of instruction information transmitted when instructing generation of a musical tone from the CPU 104. Specifically, the register 30
1 stores, for example, an initial value AS of a read address (relative address) for reading a waveform, a data length LPA of a loop portion of the waveform data, a pitch PITCH, and the like.
The register 302 stores an absolute address WA indicating the beginning of the loop portion of the waveform data to be read. Note that the initial value AS of the read address is set to a negative value because it is a relative address based on the start position of the loop portion of the waveform data (that is, the end of the attack portion). The waveform data is read from the absolute address WA using the initial value AS.
Start from the previous position by the amount indicated by. The data length LPA of the loop portion of the waveform data is a relative address (positive value) at the end position of the loop portion.

The X access circuit 304 has an XA register 3
11, selector 312, FIFO (First In)
A first-out (first-in, first-out) register 313, an X flag 314, and a sample number register 315. The X access circuit 304 performs X access processing (waveform memory 1 from the CPU 104) described later.
09 and output line 2 from mixer 204
Waveform memory 1 of musical tone waveform data transmitted via
09) in parallel with the reading of the waveform memory for generating a musical tone. The priority flag 303 is a flag that is turned on when the X access process is to be preferentially performed. The operation and function of the X access circuit 304, and the X access processing and usage of the priority flag 303 will be described later.

The read / write circuit 202 includes a processing A operation circuit 3
21, an address RAM (ARAM) 322, an accumulator (ACC) 323, a control RAM 324, a processing B operation circuit 325, an interpolation circuit 326, a waveform buffer 327, a capture circuit 328, and a selector (SEL) 329.
330 is provided.

The control register 201 and the read / write circuit 202 shown in FIG. 3 roughly perform five processes: process A, process B, fetch process, interpolation process, and X access process. The outline of each process is as follows. Process A is
The processing is mainly executed by the processing A arithmetic circuit 321. More specifically, the processing is for generating an address (waveform sample read address (relative address)) for each channel in accordance with time-division channel timing for generating a musical tone. . The address of each channel is ARAM3
22. The process B is a process mainly executed by the process B arithmetic circuit 325. Specifically, for generating a tone, the address WMA (waveform sample read address (absolute address)) is generated at a timing different from the time-division channel timing. ) Is sent to the waveform memory 109 via the selector 329. The capture processing is mainly executed by the capture circuit 328. Specifically, the waveform memory 1
This is a process of taking in a waveform sample read in accordance with the address sent to the address 09 via the selector 330 and writing the sample into the waveform buffer 327 for each channel. When the process B and the capture process are performed, the selectors 329 and 330 determine that the address WMA output from the process B operation circuit 325 is input to the address terminal of the waveform memory 109 and the waveform sample read from the waveform memory 109 Is selected and controlled so as to be captured by the capture circuit 328. The interpolation process is a process executed by the interpolation circuit 326. Specifically, the waveform samples of the respective channels are read from the waveform buffer 327 according to the time-division channel timing, and the interpolation is performed to obtain the interpolated samples (tone waveform data). ) Is generated and output. The tone waveform data output from the interpolation circuit 326 is
It is input to the volume change control circuit 203 of FIG. The X access process is a process mainly executed under the control of the X access circuit 304. More specifically, the CPU 104 uses a time slot other than the time slot for accessing the waveform memory 109 in the process B and the acquisition process. This is a process for accessing the waveform memory 109 from the mixer and writing the tone waveform data transmitted from the mixer 204 via the output line 223 to the waveform memory 109. At the time of X access processing, the selectors 329 and 330
The address stored in the register 311 is input to the address terminal of the waveform memory 109, and the selection is controlled so that the data line of the waveform memory 109 is connected to the FIFO 313. Details of the above five processes will be described later.

FIG. 4 shows the configuration of the control RAM 324 of FIG. As will be described in detail later, in the process A, a process of obtaining the required number of samples to be read for each channel and storing it in the control RAM 324 is performed in parallel with the creation of the address of each channel. Therefore, the control RAM 324
A plurality of areas for storing a channel number (CH number) and the number of samples to be read in the channel are prepared. The read / write circuit 202 has a write pointer and a read pointer, and controls the required number of samples to be read in each channel.
When writing to M324 (process A), the write pointer is recommended, and when the channel number and the number of samples are read from the control RAM 324 and a read address for the channel is transmitted (process B), the read pointer is advanced. The control RAM 324 is used in a ring shape. When the write or read pointer reaches one end of the control RAM 324, the position of the next pointer is the other end of the control RAM 324. Also,
Writing and reading are performed so that the position pointed to by the read pointer follows the position pointed to by the write pointer, and it is assumed that a size of an area is secured such that the write pointer does not overtake the read pointer. As with the accumulator 323, the write pointer and the read pointer are provided separately for the first half and for the second half. When simply referred to as a write pointer and a read pointer, the first half processing indicates the one for the first half processing, and the second half processing indicates the one for the second half processing. The first half processing is the processing of the 0th to 15th channels, and the second half processing is the processing of the 16th to 31st channels (described later in FIGS. 8 and 9). In addition to the configuration as shown in FIG. 4, an address may correspond to each channel one by one, and the required number of samples may be written there.

FIG. 5 shows a memory map of the ARAM 322 of FIG. The ARAM 322 is an area used for creating an address of each channel in the process A. A
The RAM 322 is composed of areas for each channel of 32 channels (0th to 31st channels), and stores the current address value of each channel in these areas. The area of each channel is composed of an address upper ADH and an address lower ADL. The size of each of the ADH and ADL areas is 16 bits. Address upper ADH
The 32-bit address value including the address and the lower ADL is divided into an address integer part and an address decimal part. Address integer part is 23 bits, address decimal part is 9
Is a bit. The address integer part corresponds to the address of the waveform memory 109. That is, there is one waveform sample in the waveform memory 109 corresponding to one value of the address integer part. The address decimal part indicates a finer unit and is information used in interpolation processing using some waveform samples.

FIG. 6 shows the waveform buffer (sample R) of FIG.
AM) 327 is shown. The waveform buffer 327 includes four reproduction sample storage areas for each channel. The four reproduction sample storage areas are used in a ring shape. That is, a pointer is provided for each channel, and when writing a waveform sample, writing is performed at the position indicated by the pointer, and the pointer is advanced by one. For example, if the pointer is the i-th channel in FIG.
→ 4 → 1 → 2 → ...

Next, the above five processes executed by the control register 201 and the read / write circuit 202 in FIG. 3 will be described in detail. First, the timing of executing these processes will be described, and then details of each process will be described.

Referring to FIGS. 3, 8, and 9, an outline of the processing timing of the main part of the read / write circuit 202 will be described. In FIG. 8, “Process A” indicates a section in which the process A mainly performed by the process A operation circuit 321 in FIG. 3 is performed. "Process B and X access process"
FIG. 3 mainly shows a section in which the processing B executed by the processing B arithmetic circuit 325 and the X access processing executed under the control of the X access circuit 304 are performed. The “acquisition process and X access process” indicate a section in which the acquisition process mainly executed by the acquisition circuit 328 in FIG. 3 and the X access process executed under the control of the X access circuit 304 are performed. “Interpolation processing” indicates a section in which the interpolation processing is performed by the interpolation circuit 326 in FIG.

The processing section of "processing A" and "interpolation processing" divides one sampling cycle into a first half section and a second half section.
Processing of the 0th to 15th channels is performed in the first half section, and processing of the 16th to 31st channels is performed in the second half section. That is, the first half section (the first half section of the processing A)
At 801, processing A for the 0th to 15th channels is performed. For second half section (processing A second half section) 811, processing A for the 16th to 31st channels is performed at the first half section (first half section of interpolation) 8.
In 06, the interpolation process for the 0th to 15th channels is performed, and in the latter half section (interpolation latter half section) 816, the interpolation processing for the 16th to 31st channels is executed. "Process B
And X access processing ”, processing B is performed in front sections 802 and 812 of each section obtained by dividing one sampling cycle into a first half section and a second half section, and a rear section 8
At 03 and 813, X access processing is performed. 0th to 15th
The first half section 802 of the processing B for performing the processing B of the channel includes:
The first half section 801 of the processing A for performing the processing A of the channel
Is started immediately after the end of the processing, and the X access processing is performed in the interval 803 of the idle time after the necessary processing B is performed. Similarly, the second half section 812 of the processing B for performing the processing B of the 16th to 31st channels is the processing A of the channel.
A, which starts immediately after the second half section 811 of the processing A is completed, and the section 8 of the idle time after the necessary processing B is performed.
At 13, an X access process is performed. The import process is
Since the processing B is performed in accordance with the address sending timing, the capture processing is also performed in the front sections 804 and 814 of each section obtained by dividing one sampling period into the first half section and the second half section, and the rear section is performed. In steps 805 and 815, X access processing is performed. After the capturing process, the interpolation process of each channel is performed according to the time-division channel timing in sections 806 and 816, which are started at timings at which it is guaranteed that the waveform samples of each channel are aligned in the waveform buffer 327.

FIG. 9 shows the state of the channel during each processing of the first half processing of FIG. “Processing A first half ch” in FIG. 9 indicates the state of the channel in the section 801 in FIG. FIG.
“Processing B first half channel and X access processing” indicates the state of channels in sections 802 and 803 in FIG.
“Import first half channel and X access processing” in FIG.
FIG. 9 shows the state of channels in sections 804 and 805 in FIG. “First half channel of interpolation” in FIG. 9 indicates the state of the channel in the section 806 in FIG. The same applies to the latter half processing. In FIG. 9, the respective channel timings are vertically aligned and described, but actually, the timings of the respective processes are shifted as shown in FIG.

In this embodiment, as can be seen from FIG. 9, the processing A for creating an address by the processing A operation circuit 321 and the interpolation processing by the interpolation circuit 326 are respectively performed by time division channel timings obtained by equally dividing one sampling period. , The processing for each channel is performed in order. On the other hand, the processing B for sending an address from the processing B arithmetic circuit 325 and the processing for capturing waveform data by the capture circuit 328 operate at a timing independent of the time division channel timing.

For example, in FIG. 8 and FIG.
In the first half section 801, the processing A arithmetic circuit 321 sequentially creates addresses of the 0th to 15th channels in accordance with the time division channel timing. In the first half section 802 of the processing B, the processing B arithmetic circuit 325 assigns one address of the 0th channel and the second address at a timing different from the time division channel timing.
The addresses of the 0th to 15th channels are sent out, for example, three channel addresses, one fifth channel address, and so on. The time width of the section in which one address is sent out is 1 / th of the time width of the section in which processing for one channel is performed at the time-division channel timing.
4. Therefore, four accesses to the waveform memory can be made within a time width for performing processing for one channel. The number of addresses to be sent out for each channel is different if the waveform buffer (sample RAM) 327 holds the past waveform data (reproduced samples) and only the required number of waveform data for each channel is read out. This is because there is a sufficient channel, or there is a channel that does not need to be sounded and does not need to send an address. In this case (FIG. 9), the 0th channel is 1 access and the 2nd channel is 3 access, respectively.
The fifth channel shows the case where one access is required, and the seventh channel is the case where it is necessary to read from the waveform memory for two accesses. The other channels are channels that are not sounding or can generate musical tones using only the samples that have already been read and stored in the waveform buffer 327.
The channel that is not sounding is a channel whose volume level has been lowered by the volume change control circuit 203 or the like, and the channel is controlled so as not to use the access timing of the waveform memory in the process B. .

In the first half section 804, waveform data read from the waveform memory 109 is fetched in accordance with the address sending timing of the first half section 802 of the processing B. The interpolation circuit 326 performs interpolation processing on the 0th to 15th channels using the data of the waveform buffer 327 in the interpolation first half section 806 according to the time division channel timing. At the time of performing interpolation on a certain channel, the waveform data of the channel required for performing the interpolation is prepared in the waveform buffer 327.

At the above timing, the 0th to 15th
The musical tone waveform data of the channel is generated. The same applies to the 16th to 31st channels processed using the latter half section.

Processing B The processing B of address sending in the arithmetic circuit 325 and the processing of waveform data capture in the capture circuit 328 are performed at timings different from the time-division channel timing by the required number of accesses, so that an empty time slot appears. . In the section of “processing B first half channel and X access processing” and “capture first half channel and X access processing” in FIG.
"h" indicates an empty time slot that is not used for sample reading of any channel. The sections 803 and 805 of the empty time slots can be used arbitrarily. Therefore, the processing B arithmetic circuit 325 switches the selectors 329 and 330 in this empty time slot section,
X access processing (access processing to the waveform memory 109 by the CPU 104 performed under the control of the X access circuit 304, and output from the mixer 204 to the output line 223)
Waveform memory 109 of musical tone waveform data returned via
Write process to the memory).

A control clock from a clock generator (not shown) is input to the control register 201 and the read / write circuit 220 shown in FIG. Each unit operates with reference to this clock, so that each process is executed at timings shown in FIGS.

Next, five processes by the control register 201 and the read / write circuit 202 in FIG. 3 will be described in detail in the following (1) to (5).

(1) Process A The process A executed by the arithmetic circuit 321 will be described in detail. When a tone generation start instruction is given on a certain channel, the processing A operation circuit 321 starts executing the processing A for the channel. Processing A
Is executed at the time-division channel timing as described with reference to FIGS. First, in the first time slot of the corresponding channel (immediately after the rise of note-on), the processing A
The arithmetic circuit 321 includes an ARAM corresponding to the channel.
322 (FIG. 5) address storage area (ADH and ADL)
Is initialized. The initial value is the start address AS of the waveform data to be read (negative value because it is a relative address based on the start position of the loop portion of the waveform data).
104 is designated via the register 301 of FIG. In the time slot of the channel after the next time, the processing A operation circuit 321 sets the ARAM 32 corresponding to the channel.
The pitch PITCH, which is the advance value (frequency number) of the address in the channel, is added to the current address value of the address storage area of No. 2. The addition result is the original ARAM
322 is stored in the address storage area. Pitch PIT
The CH is designated by the CPU 104 via the register 301 in FIG.

More specifically, the pitch PITCH is added to the address decimal part of the current address value of the channel, and a value overflowing from the number of bits of the address decimal part in the addition result is calculated as the current address value. This is performed by adding to the address integer part. This overflow value is the number of waveform samples to be newly read. Read / write circuit 20
In No. 2, the waveform sample read so far is held in the waveform buffer 327, and the overflow value is the advance amount of the read address on the waveform memory. In FIG. 9 described above, the overflow value is 1 in the 0th channel,
This is the case where the second channel is 3, the fifth channel is 1, and the seventh channel is 2. For other channels,
The channel is not pronounced or the overflow value is 0.

The waveform data on the waveform memory 109 is composed of an attack part and a loop part following the attack part.
The initial value AS of the read address is based on the start position of the loop portion of the waveform data (that is, the end of the attack portion).
(Negative value) and relative address LPA at the end of the loop
(Positive value) is set. The access of the waveform sample is started from the head of the attack part (that is, the current address starts from a negative relative address AS and gradually increases). Enter the department. Thereafter, the waveform samples of the loop portion are repeatedly read as necessary. for that reason,
The current address value is at the end of the loop (= relative address LP
If the value exceeds A), a process of subtracting the value LPA from the current address value and setting the result of the subtraction as a new current address value is performed. The absolute address WA indicating the beginning of the loop portion of the waveform data is later added to the current address value. The process A operation circuit 321 is in the process of creating the above-described address,
A process of returning such an address to near the beginning of the loop is also performed.

As described above, the pitch (frequency number) is accumulated in the current address on the ARAM 322 in the time slot of the channel, and the sequential address for the channel is generated on the ARAM 322.

In the process A, in addition to the above-described process of creating the address of each channel, the write pointer pointing to the write position in the control RAM 324 (FIG. 4) is advanced by one, and the required number of samples for each channel is stored in the control RAM 324.
Is stored at the position indicated by the write pointer. Since the required number of samples for each channel matches the value overflowing above the bit number of the address decimal part in the result of adding the pitch PITCH to the address decimal part of the above-mentioned current address value, this overflow value And stores it in the control RAM 324 together with the channel number.

Further, in the process A, in addition to the above-described processes of creating the address of each channel and storing the required number of samples for each channel, the number of waveform memory accesses required for each of a plurality of predetermined channels (in this embodiment, A process of accumulating (the number of samples matches the number of accesses) is also performed. Specifically, the processing A operation circuit
The required number of samples to be read for these channels is accumulated in parallel with the address creation of the 15th channel (first half processing), and further, in parallel with the address creation of the 16th to 31st channels (second half processing). Accumulate the required number of samples to be read for the channel.

An accumulator (ACC) 323 is an accumulator for performing this accumulation. The accumulator 323 is actually composed of two accumulators, a first half accumulator and a second half accumulator, because the read / write circuit 202 performs accumulation in the first half processing and the second half processing separately. When simply referring to the accumulator 323,
The first half processing refers to the first half accumulator, and the second half processing refers to the second half accumulator.

More specifically, the accumulation process is performed as follows. First, the accumulator 323 is initialized (cleared to zero) at the start of the first half process and the second half process. After that, until the last channel of the first half processing and the second half processing,
The required number of samples (that is, the number of accesses) is accumulated in the accumulator 323. The required number of samples to be read for each channel is determined by the control RAM 324.
You can tell when you write to.

Further, in the process A, the accumulative value of the number of accesses as a result of the accumulation as described above is the maximum accessible number (access limit number) in the first half or the second half of the process B for actually executing the access. Is determined, and the number of accesses and the interpolation order for each channel are determined according to the result. Hereinafter, this will be described. First, a description will be given focusing on the section of the first half processing. The first half processing section is a time section that is half of one sampling period, and processing B relating to the 0th to 15th channels is performed in that section.
(And a fetch process performed after some delay time). In addition, the time width of the section in which one address is sent out in the process B is の of the time width of the section in which the processing for one channel is performed at the time-division channel timing. Therefore, if X access processing is not performed in the section (ie, sections 803 and 805 in FIGS. 8 and 9).
), 64 accesses are possible in the first half section. In this embodiment, four-point interpolation is performed for each channel. Therefore, even when it is necessary to read out four-point waveform samples from all 16 channels to be processed in the first half section,
Since 4 points × 16 ch = 64 accesses, if all of the first half section is used for processing B and fetching processing without performing X access processing, 4-point interpolation can be performed on all channels. However, when the priority flag (to be described in detail in the following process B) 303 is turned on, a predetermined number of (one in this embodiment) access is preferentially executed in the X access process in the first half section. Therefore, the maximum accessible number by the process B and the fetch process in the first half section is a value obtained by subtracting the access number of the X access process from 64. Therefore, it is conceivable that the accumulative access count accumulated by accumulator 323 exceeds the maximum accessible number in the first half section as described above. In this case, it is not possible to access the entire number of samples of each channel written in the control RAM 324. Therefore, the number of accesses of any of the channels having a large number of accesses (for example, three or four times) is reduced and interpolation is performed. Decrease order. Reducing the interpolation order means, for example, that the processing of four-point interpolation is three-point interpolation or two-point interpolation.
That is, change to point interpolation (linear interpolation). As a method of determining the channel to reduce the number of accesses,
For example, there are the following methods.

The number of accesses is reduced from one end in channel order. At that time, the number of accesses is reduced from the channel having the lower volume level. In this way, the influence on the musical sound is small. The volume level of each channel is known from the envelope value.

In this embodiment, 64 is used in the first half section.
It is accessible and the interpolation is 4-point interpolation.
Since it is considered very rare to read four points in all the fifteenth channels, the number of accesses and the interpolation order of each channel are determined from the result of accumulating the number of accesses and comparing with the maximum accessible number. There is almost no problem in practical use even if no function is provided. However, 4
This is an effective function when, for example, 6-point interpolation is performed on each channel instead of point interpolation, or when the number of accesses to be preferentially secured in the X access processing when the priority flag 303 is on is large. Although the description has been given focusing on the first half section, the same applies to the second half section.

(2) Next, the processing B executed by the processing B arithmetic circuit 325 will be described in detail. Processing B operation circuit 3
Reference numeral 25 denotes processing B, that is, an address which is different from the time-division channel timing, that is, the
The process of sending out to is performed. As described with reference to FIG. 9, four accesses (reading of four samples) are possible within the time per channel of the time division channel timing. The waveform memory access process of the process B has no relation to the process of the process A according to the time-division channel timing, and is sequentially and continuously performed for each channel that needs to be read. The channels that need to be read and the number of samples are determined in the above-described process A and set in the control RAM 324. Also, as described with reference to FIGS.
When the process B is performed for a certain channel, the process A for the channel has already been executed, and the address value of the channel has been set in the ARAM 322.

The address sending process will be described. First, it is determined whether or not the value of the read pointer indicating the read position in the control RAM 324 shown in FIG. 4 matches the value of the write pointer at the end of the first half or the second half of the processing A for the channel. For example, when the process B of the channel is a process in the first half section 802 of the process B in FIG. 8, the value of the read pointer is compared with the value of the write pointer at the end of the first half section 801 of the process A. . If this coincides, it means that there is no more sample to be read in the section of the process B, so that the process B of the section is completed and control is performed so that X access processing described later is performed in the remaining empty slot.

When the value of the read pointer does not match the value of the write pointer, the read pointer is advanced by one, and the channel number and the number of samples indicated by the read pointer are read from the control RAM 324. And
The addresses corresponding to the channel numbers corresponding to the number of samples are sent to the waveform memory 109. Specifically, ARA
The current address integer part of the channel is read from M322, a plurality of offsets for sequentially accessing a required number of samples are added, and an absolute address WA indicating the head of the loop part of the waveform data is added (processing Since the address created in A is a relative address, WA is added to convert the address to an absolute address), a final read address WMA is obtained, and the selector 329 is controlled to select and output this address WMA. Thus, one address is sent to the waveform memory 109. For example, in the example of FIG. 9, the offset to be added is 0 for the 0th channel, −2 for the first time of the second channel, −1 for the second time, −1 for the third time, and −1,2 for the first time of the fifth channel.
The number of times is 0 or the like. As described above, at the address sending timing described with reference to FIGS.

As described above with reference to FIGS. 8 and 9, the address sending process is performed a necessary number of times at a timing different from the time-division channel timing, so that an empty time slot as an extra access time appears.
Therefore, after the address sending process, the process B arithmetic circuit 325 switches the selector 329 so that the address from the XA register 311 is selectively output (further, the selector 330 such that the data line of the waveform memory 109 is connected to the FIFO 313). Is switched), and the X access processing is performed using the extra time under the control of the X access circuit 304.

The priority flag 303 is appropriately turned on / off by the CPU 104. When the priority flag 303 is turned on, the processing B arithmetic circuit 325 performs at least one (or a plurality of times, the number of slots to be reserved) for the X access processing regardless of the state of reading the waveform data of each channel for generating a tone. 8 and 9 are secured (that is, in FIGS. 8 and 9, sections 803 and 805 are used in the first half processing, and sections 813 and 815 are used in the second half processing).
Are secured for at least one access each). Thereby, the access process from the CPU 104 to the waveform memory 109 or the output line 223 from the mixer 204 is performed.
Waveform memory 109 of musical tone waveform data returned via
Can always be included in only one access.

(3) Next, the fetch process executed by the fetch circuit 328 will be described. Capture circuit 328
Is the address W sent from the processing B operation circuit 325.
The waveform sample read by the MA is captured and written to the waveform buffer 327. At this time, the selector 330
Connects the data line of the waveform memory 109 to the fetch circuit 328 under the control of the processing B arithmetic circuit 325. As a result of capturing the waveform sample, the waveform buffer 327
, Basically 4 samples are prepared for each channel. However, if there is a channel whose interpolation order is lowered in the process A, the waveform buffer 327 prepares samples necessary for the channel by the interpolation whose order is lowered. If the waveform samples stored in the waveform memory 109 are compressed, the acquisition circuit 3
At 28, decoding is performed.

Since the fetching process is performed in synchronization with the address sending by the process B, an empty time slot as an extra access time appears as described in the process B. Therefore, after the capture processing, the processing B operation circuit 3
25 is a data line of the waveform memory 109 and the FIFO 31
3 is switched so that X.3 is connected to X.
Under the control of the access circuit 304, this extra time is used to perform the X access processing.

(4) Next, the interpolation processing executed by the interpolation circuit 326 will be described in detail. The interpolation circuit 326 performs an interpolation process for each channel in order according to the time division channel timing. The interpolation process for one channel is as follows. First, four waveform samples of the channel are sequentially read from the waveform buffer 327. Then, each sample is multiplied by a predetermined interpolation coefficient and accumulated. The interpolation coefficient by which each sample is multiplied is determined based on the address decimal part FRAC of the channel. The address decimal part FRAC is input from the ARAM 322 via the processing B operation circuit 325. As described above, the interpolated musical tone waveform data is generated and output. Note that, for channels whose interpolation order has been reduced by reducing the number of accesses to the waveform memory described above, interpolation is performed at the reduced order to obtain interpolated tone waveform data.

(5) Next, the X access processing will be described in detail. As described above, after successively sending addresses for each channel necessary for the processing B and the acquisition processing, and reading out waveform samples to the waveform buffer 327, if there is an empty time slot, the processing B arithmetic circuit 325 The selectors 329 and 33 are set so that X access processing is performed in an empty time slot section.
Switch 0. Specifically, sections 803 and 803 in FIGS.
At 813, the XA register 311 stores the waveform memory 109
The selector 329 is switched so as to be connected to the address line of the FIFO 313 in the sections 805 and 815.
Is switched to connect the selector 330 to the data line of the waveform memory 109. Processing B operation circuit 325
Switches the selectors 329 and 330 in this way, and informs the X access circuit 304 that the X access processing is enabled. Thereby, the X access circuit 30
4 starts the X access processing (if instructed by the CPU 104). Further, the processing B operation circuit 325
At the end of the access processing (at the end of the first half section and the second half section, which are half the time width of one sampling period), the selectors 329 and 330 are switched again so that the next processing B and the fetch processing can be performed. Note that there is a slight timing difference between the input of an address to the waveform memory 109 and the data access of the address (for example, the first half section 804 of FIG. 8 is slightly delayed from the first half section 802 of the processing B), so that the selector 329 is used. The timing of the switching of the selector 330 slightly deviates from the timing of the switching of the selector 330, but the switching is controlled appropriately by the processing B arithmetic circuit 325.

The X access process is executed by the CPU 1
04, a process of writing waveform data from the waveform memory 109 to the waveform memory 109, a process of reading waveform data from the waveform memory 109 by the CPU 104, and a waveform memory 10 of waveform data returned from the mixer 204 via the output line 223.
There are three types of write processing for writing data to Nin. Hereinafter, each will be described.

When writing data from the CPU 104 to the waveform memory 109, first, the CPU 104
Is switched so that the data bus to which the CPU 104 is connected and the FIFO 313 are connected. Then, the CPU 104 sets a write address (head address) in the XA register 311, sets the number of waveform sample data to be written in the sample number register 315, and sets the first eight samples of the waveform sample data to be written via the selector 312. Then, it is sequentially set in the FIFOs 313 of eight stages, and the X access circuit 304 is instructed to start writing. Thereafter, the CPU 104 appropriately refers to the X flag 314 and, when the X flag 314 is turned on, sequentially writes the remaining waveform sample data to be written to the FIFO 313. X flag 314 is FIFO3
13 is a flag indicating an empty state. When writing data from the CPU 104, the flag is automatically turned on when there is an empty space in the FIFO 313, and is automatically turned off when there is no empty space in the FIFO 313. Therefore, the CPU 10
4 may send write data to the FIFO 313 until the X flag 314 is turned off.

FIG. 7A shows a case where the CPU 104
313 shows how to use the FIFO when writing data. The rectangles 701 and 702 indicate the FIFO 313, the hatched portion indicates a portion where data is written, and the white portion indicates an empty portion. At 701, data is written in all of the eight stages of the FIFO 313, and the X flag is turned off. At this time, the CPU 104 stores the data in FIFO3
13 cannot be written. FI in X access processing
When the data of the FO 313 is read and written into the waveform memory 109, the FIFO 313 becomes empty as indicated by 702, and the X flag is turned on. At this time, the CPU 104
Detects that the X flag is on and returns the next write data to F
It can be written to IFO 313.

When all the waveform sample data to be written has been sent to the FIFO 313, the writing is completed when viewed from the CPU 104. Therefore, the CPU 104 instructs the X access circuit 304 to perform a CPU write stop process, and ends the write process.

On the other hand, when the X access circuit 304 receives the write start instruction from the CPU 104, the X access circuit 304 determines the time in each of the sections (sections 803, 813, 805, and 815) in which the processing B operation circuit 325 indicates that it is an empty time slot. In the slot, a process of writing the waveform sample data in the FIFO 313 to the waveform memory 109 is performed. The processing performed in one time slot is as follows. First, the address stored in the XA register 311 is sent to the waveform memory 109. Next, one piece of waveform sample data is taken out from the FIFO 313, sent to the waveform memory 109, and written to the above-mentioned address position. Thereafter, the address of the XA register 311 is incremented. The X access circuit 304 includes a counter that is cleared to zero by a write start instruction and counts up when one piece of waveform sample data is written to the waveform memory 109. The value is compared with the number of samples in the sample number register 315. When the value of the counter reaches the number of samples in the sample number register 315, it means that all the specified data has been written, and the writing process ends.
When the CPU 104 instructs a CPU write stop process, all data remaining in the FIFO 313 is written into the waveform memory 109, and the process ends. In addition, without providing the sample number register 315, the X access circuit 304
FIFO3 until PU write stop processing is instructed
If there is data in 13, it may be written in the waveform memory 109.

When reading data from the waveform memory 109 to the CPU 104, first, the CPU 104
Is switched so that the data bus to which the CPU 104 is connected and the FIFO 313 are connected. Then, the CPU 104 sets a read address (head address) in the XA register 311, sets the number of waveform sample data to be read in the sample number register 315, and instructs the X access circuit 304 to start reading. Thereafter, the CPU 104 refers to the X flag 314 as appropriate, and when the X flag 314 is turned on, the FI
The waveform sample data is sequentially read from the FO 313. X
The flag 314 is a flag indicating an empty state of the FIFO 313. When reading data by the CPU 104, the flag 314 is automatically turned on when there is data read from the waveform memory 109 in the FIFO 313.
Automatically turns off when there is no read data.

FIG. 7B shows that the CPU 104
The following describes how to use the FIFO when reading data from O313. Rectangle 703,704 shows FIFO313,
The hatched portion indicates the portion storing the read data, and the white portion indicates the empty portion. In 703, 8 of FIFO 313
All the areas in the row are empty and the X flag is turned off. At this time, since there is no read data in the FIFO 313, the CPU 104 cannot read the data. When data is read from the waveform memory 109 and written to the FIFO 313 in the X access processing, the X flag is turned on as indicated by 704. At this time, the CPU 104
Can detect the ON of the X flag and read the read data from the FIFO 313.

The X flag 314 indicates whether or not there is read data in the FIFO 313, and the X flag 314
Is off, it is possible to determine whether or not the number of waveform samples specified by the sample number register 315 has been read. Therefore, when the X flag 314 is off, the CPU 104 determines whether or not the number of waveform sample data specified by the sample number register 315 has been read out.
U read stop processing is instructed, and the read processing ends.

On the other hand, upon receiving the read start instruction from the CPU 104, the X access circuit 304 determines the time in each of the sections (sections 803, 813, 805, and 815) in which the processing B operation circuit 325 indicates that it is an empty time slot. In the slot, a process of reading waveform sample data from the waveform memory 109 and writing the sample data to the FIFO 313 is performed. The processing performed in one time slot is as follows. First, the address stored in the XA register 311 is sent to the waveform memory 109. Next, one waveform sample data at the address is read from the waveform memory 109 and written into the FIFO 313. Thereafter, the address of the XA register 311 is incremented. The X access circuit 304 includes a counter that is cleared to zero by a read start instruction and counts up when one waveform sample data is read from the waveform memory 109 to the FIFO 313. Counter value and sample number register 31
Compare 5 sample numbers. When the value of the counter reaches the number of samples in the sample number register 315, it means that the specified number of data has been read, and the reading process ends. When the CPU 104 instructs the CPU reading stop process, the process ends. In addition, without providing the sample number register 315, the X access circuit 304
Data reading from the waveform memory 109 to the FIFO 313 may be continued until an instruction to stop PU reading is given.

When writing the waveform data returned from the mixer 204 via the output line 223 into the waveform memory 109, the CPU 104 first switches the selector 312 to connect the output line 223 from the mixer 204 to the FIFO3.
13 is connected. And the CPU 104
Sets the write address (head address) in the XA register 311, sets the number of waveform sample data to be written in the sample number register 315, and instructs the X access circuit 304 to start writing. Thereafter, the mixer 204 outputs the output line 22
Since the waveform sample data is sent out via 3
X access circuit 304 stores the transmitted data in F
Write to IFO 313. In the case of writing the data returned from the mixer 204, it is not possible to write the data to the FIFO 313 when the X flag 314 is on as in the case of the data writing from the CPU 104 described above. Since the received data is sent at each sampling period, the sent data must be written to the FIFO 313 immediately. If there is no free space in the FIFO 313 at that time, the data sent from the mixer 204 is discarded. However, as described above, it is considered that there is almost no situation in which waveform memory accesses for generating musical tones are so crowded that no slot for the X access processing can be taken during one sampling period. 2
Even if the data sent from 04 is discarded, there is almost no problem in practical use. Further, if the priority flag 303 is turned on, the slot for the X access processing can be secured at least once during one sampling period.
9 can be written.

On the other hand, the X access circuit 304, which has received the write start instruction from the CPU 104, sets each time in the section (section 803, 813, 805, 815) in which the processing B operation circuit 325 indicates that it is an empty time slot. In the slot, the processing of writing the waveform sample data in the FIFO 313 to the waveform memory 109 is performed. This processing is the same as that described for the writing of the waveform data from the CPU 104, and thus the description is omitted.

The detailed description of the five processes by the control register 201 and the read / write circuit 202 in FIG. 3 has been completed.

FIGS. 10 and 11 show specific examples of setting of the signal processing circuit (DSP) 205 and the mixer 204 of FIG.

FIG. 10A shows an example of a setting for performing sampling. Blocks 1001 and 1005 correspond to a mixing process (hereinafter simply referred to as M
IX). Blocks 1002, 1003, 1
Reference numeral 004 indicates processing (corresponding to a microprogram set in the signal processing circuit 205) executed by the signal processing circuit 205 in FIG. Arrows indicate signal flow,
O1006 is a FIFO in the X access circuit 304 of FIG.
313. "ADC input" to MIX1001
Is an external tone signal input from the external circuit (ADC) 110 of FIG. 2 via the interface 206 and the input line 213. This ADC input is connected to the mixer 20
One of the eight channels of input to 4 is used.

The output of the MIX 1001 is the mixer 2 of FIG.
04 via the output line 221 to the signal processing circuit 205
Out of the eight channels output to In the signal processing circuit 205, the blocks 1002 to 1002 in FIG.
04 is performed. That is, the envelope is extracted from the output from the MIX 1001 by the envelope extraction processing 1003, and the gate 1002 is opened at the rising edge of the envelope. When the gate 1002 is opened, the output of the MIX 1001, that is, the tone waveform input from the outside, is subjected to the waveform processing 1004 every sampling period.
Sent to. In the waveform processing 1004, various waveform processing is performed on the input musical sound waveform. For example, DC cut processing for cutting DC components, noise mute processing for muting when the input level is low, compressor processing for lowering the gain when the level of the envelope is above a certain value, and when the level of the input waveform is low. An expander process for reducing the level and an Fs (sampling frequency) conversion process for lowering the tone waveform input from the outside at a high sampling frequency to a low sampling frequency or conversely increasing the sampling frequency.

The output of the waveform processing 1004 is again MIX10
Return to 05. This corresponds to a portion in which the processing result of the signal processing circuit 205 in FIG. 2 is returned to the mixer 204 using one channel of the input line 212. And MIX1
From 005, the tone waveform is output to the FIFO 1006 and written to the waveform memory 1009. This corresponds to the FIFO in the control register 201 from the mixer 204 via the output line 223.
O313 indicates a portion where waveform data is written. FIFO
The data written to 313 is written to the waveform memory 109 as described above.

FIG. 10B shows an example (1) of setting of a microprogram for resampling and a mixer. As in FIG. 10A, MIX 1011 and 1014
Corresponds to the mixer 204 in FIG. 2, and the FIFO 1015 corresponds to the FIFO 313 in FIG. Block 1012, 1
013 corresponds to the microprogram set in the signal processing circuit 205 of FIG. The “ch output” to the MIX 1011 is a tone signal input from the volume change control circuit 203 of FIG. It is a musical sound waveform.
This “ch output” may be one of the 32 channels or a plurality of channels. That is, a plurality of waveform data may be read from a plurality of tone generation channels, and the read plurality of waveform data may be mixed by the MIX 1011.

The output of MIX 1011 is the mixer 2 of FIG.
04 via the output line 221 to the signal processing circuit 205
Out of the eight channels output to The signal processing circuit 205 performs the processing shown in blocks 1012 and 1013. That is, the output from the MIX 1001 is subjected to component separation by the separation filter 1012 to extract a periodic component and an aperiodic component. Interleave 1013
MIX101 alternates the periodic component and the non-periodic component.
4 to be written to the FIFO 1015. As a result, resampling is performed in which the tone waveform prepared in advance in the waveform memory is subjected to component separation by sampling or the like and returned to the waveform memory again. The periodic component output from the separation filter 1012 may be subjected to, for example, LPC compression.

FIG. 10C shows an example (part 2) of setting a microprogram for resampling and a mixer. As in FIG. 10A, the MIXs 1021, 1023
Corresponds to the mixer 204 in FIG. 2, and the FIFO 1024 corresponds to the FIFO 313 in FIG. Block 1022 is
This corresponds to a micro program set in the signal processing circuit 205 in FIG. The “ch output” to the MIX 1021 is a tone signal input from the volume change control circuit 203 in FIG. It is a musical sound waveform. This "ch
The “output” may be one of the 32 channels or a plurality of channels. That is, a plurality of waveform data may be read from a plurality of tone generation channels, and the read plurality of waveform data may be mixed by the MIX 1021.

The output of the MIX 1021 is the mixer 2 of FIG.
04 via the output line 221 to the signal processing circuit 205
Out of the eight channels output to The signal processing circuit 205 performs the waveform processing shown in block 1022. The waveform processing 1022 includes, for example, equalizer, modulation (modulation), waveform compression, Fs conversion,
There is a physical model sound source and a process of adding reverb. The physical model sound source means that the physical model sound source is operated using the output from the mixer 1021 as a drive signal, and the resulting waveform is output. Waveform processing 102
2 are stored in the FIFO 1024 via MIX1023.
And recorded in the waveform memory 109 again. As a result, resampling is performed by performing various waveform processing on the musical tone waveform existing on the waveform memory by sampling or the like and returning the waveform to the waveform memory again.

FIG. 11 (a) shows an example (1) of setting of a microprogram for generating a musical tone and a mixer. FIG. 11B shows an example (part 2) of setting of a microprogram and a mixer for generating a musical tone. FIG.
As in (a), MIX1101, 1103, 1111
Reference numerals 1113 and 1117 correspond to the mixer 204 in FIG. DACs 1104 and 1118 correspond to DAC 112 in FIG. In FIG. 11A, the block 1102 corresponds to FIG.
In FIG. 1B, blocks 1114 to 1116 respectively correspond to microprograms set in the signal processing circuit 205 in FIG. Each MIX1101, 1111-11
The “ch output” input to 13 is a tone signal (one of 32 channels or a plurality of channels) input from the volume change control circuit 203 of FIG. 2 via the input line 211, respectively. It is. Each MIX11
Outputs 01, 1111 to 1113 are one of eight channels output from the mixer 204 of FIG. 2 to the signal processing circuit 205 via the output line 221.

In the case of FIG. 11A, the signal processing circuit 205
Now, the reverb processing 110 is performed on the output of the MIX 1101.
2 is output to the DAC 1104 via the MIX 1103 to emit sound. In the case of FIG. 11B, the signal processing circuit 20
5, the chorus processing 1114, the reverb processing 1115, and the variation 1116 are performed on the outputs of the MIXs 1111 to 1113, respectively.
The signal is mixed by IX1117 and output to DAC 1104 for sound emission.

In each of the setting examples shown in FIGS. 10 and 11, mixing may be performed by inputting a tone waveform other than the illustrated input to the MIX block. Further, the setting examples of these microprograms can be set so as to be executed in parallel as appropriate in accordance with the capacity of the microprogram memory of the signal processing circuit 205. For example, it is possible to simultaneously execute the sampling microprogram of FIG. 10A and the tone generation microprogram of FIG. 11A. The mixing results of MIX1103 and 1117 are represented by D
AC1104, 1118 and line 2
23 to the FIFO 313 and output to the waveform memory 10
9 may be written. This is a phrase recording in which the played waveform data is recorded as it is.

Next, the processing procedure of the CPU 104 of the electronic musical instrument will be described with reference to a flowchart.

FIG. 12A shows the procedure of the main routine in the control program of the CPU 104. When the power of the electronic musical instrument is turned on, first, in step 1201.
Then, various initial settings are performed. Next, in step 1202, it is checked whether or not there is any activation factor.
If there is an activation factor in step 203, the process proceeds to step 1204. If there is no activation factor, the process returns to 1202 again. Step 120
In step 4, the type of the activation factor that has occurred is determined, and the process branches to each process. When the activation factor is a key operation event of the keyboard 101 (if an external MIDI event can be accepted, the occurrence of the MIDI event is also equivalent), the keyboard processing of step 1205 is performed, and thereafter, The process returns to step 1202 again. If the activation factor is an operation event of the panel switch 103, the panel switch process of step 1206 is performed, and
It returns to step 1202. If the activation factor is an event related to the X flag 314, a flag process is performed in step 1207, and the process returns to step 1202. If the activation factor is another factor (for example, a waveform generation trigger of a software sound source to be described later), other processing is performed in step 1208, and the process returns to step 1202. If the activation factor is an operation event of the power switch, step 1
After performing the termination processing in 204, the processing is terminated.

FIG. 12B shows a procedure of a key-on event process executed when there is a key-on event of the keyboard 101 in the keyboard process of step 1205 in FIG. 12A. First, in step 1211, the note number of the key that has been turned on is set in the register NN, and the velocity at key-on is set in the register VD. Next, in step 1212, sounding channels (0th to 31st channels) are assigned, and the assigned channel numbers are set in the register i. In step 1213, information such as the address of the waveform data corresponding to the note number NN of the currently set tone is set in the control register (specifically, the registers 301 and 302 in FIG. 3) 201.
In step 1214, settings such as the currently set envelope parameter of the tone color and the mixing ratio of the mixer are also made in the control register 201. Then, in step 1215, note-on (sound source 1) for the i-th channel
08 is generated, and the tone generation operation of the tone generator 108 as described above is started.

FIG. 13A shows a procedure of a sampling SW event process executed when the sampling switch (SW) is turned on in the panel switch process in step 1206 of FIG. 12A. The user connects in advance an ADC for inputting an external sound and performing A / D conversion as the external circuit 110, and turns on the sampling SW when performing sampling. When the sampling SW is turned on, first, in step 1301, the CPU 104
OM 105, RAM 106, or external storage device 107
An input waveform processing microprogram is read out from, for example, and loaded into a microprogram memory in the signal processing circuit 205. The microprogram to be loaded here is, for example, blocks 1002 to 1004 in FIG.
This is a microprogram for performing the processing described above. Next, in step 1302, the ADC (external circuit 11
The setting of operation 0) and the setting of the mixing ratio of the mixer 204 are performed. In step 1303, the waveform memory 109
Set the address of the writing area and the number of samples. This corresponds to setting the address of the write area in the XA register 311 in FIG. 3 and setting the number of samples to be written in the sample number register 315. In step 1304, the writing process of the signal processing circuit 205 is started, and the ADC is further started. As a result, the sampling process described with reference to FIG.

FIG. 13B shows the resampling S in the panel switch processing in step 1206 of FIG.
The procedure of the resampling SW event process executed when W is turned on will be described. When the user turns on the resampling switch, first in step 1311, the CPU
The 104 reads a microprogram for resampling from the ROM 105, the RAM 106, the external storage device 107, or the like, and loads the resampled microprogram into the microprogram memory in the signal processing circuit 205. The microprogram to be loaded here is, for example, the block 1012 or 1013 or the block 102 described with reference to FIGS.
This is a microprogram that performs processing such as 2. Next, in step 1312, sounding channels are assigned, and the assigned channel numbers are set in the register i. Next, in step 1313, the address of the read waveform is set, and in step 1314, the envelope parameters, the mixing ratio of the mixer 204, and the like are set. This is equivalent to setting various information in the control register 201. In step 1315, an address in the waveform memory 109 to which the resampled waveform data is to be written and the number of samples are set. This is control register 2
01 XA register 311 and sample number register 3
15 is equivalent to setting. Then, step 13
At 16, the writing of the signal processing circuit 205 is started, a note-on is sent, and the process is terminated. The reason why the note-on is transmitted is to start the process of reading the waveform data from the address set in step 1313. As described above, resampling is performed in a signal flow as shown in FIG. 10B or 10C.

In step 1312, a plurality of channels may be allocated, and the tone waveforms read out from these channels may be mixed and written into the waveform memory after predetermined processing (see MIX101 in FIGS. 10B and 10C).
1,1021 when multiple channel outputs are input),
After performing a predetermined process for each channel, the data may be mixed and written into the waveform memory (in FIG. 10B, 1011 to 1 for each of a plurality of channels).
013 is performed and the plurality of streams are
4 or in FIG. 10C, 1021 to 1022 for each of a plurality of channels.
(2) When a plurality of streams are mixed by the MIX 1023 by performing the processing of step 2). When mixing a plurality of channels, the mixing can be performed by shifting the start position of the waveform in each channel. In this case, note-on needs to be transmitted a plurality of times in step 1316 in accordance with how to shift the start position of the waveform of each channel.
However, the writing of the FIFO starts from the first note-on.

FIG. 14A shows a waveform read SW in the panel switch processing in step 1206 of FIG.
The procedure of a waveform read (write) SW event process executed when the (or waveform write SW) is turned on will be described. Note that the waveform read SW event process and the waveform write SW event process are almost the same process except that “read” and “write” are interchanged, and therefore will be described with reference to FIG. First, the waveform read SW event process will be described, and then the waveform write SW event process will be described.

In the waveform read SW event processing, first, in step 1401, the address of the read area in the waveform memory 109 and the number of samples to be read are set in the XA register 311 and the sample number register 315. Next, in step 1402, an address of a write area in the RAM 106 to which data read from the waveform memory 109 is to be written is set. Next, at step 1403, the CP
U104 instructs the X access circuit 304 of FIG. 3 to start reading (step 1404 is a waveform writing S
Used only for W event processing), and terminates the processing. As described above, the X access processing described above is started, and the waveform data from the waveform memory 109 is sequentially read out to the FIFO 313 in FIG. 3 in parallel with the generation of the musical tone waveform.
The CPU 104 extracts the data of the FIFO 313 by an X flag read event process (FIG. 14B) described later. Such reading processing of the waveform data is performed by reading the waveform data written in the waveform memory by sampling or resampling and storing it in an external storage device (real-time hard disk recording), or processing the read waveform by a CPU. Used when writing to the waveform memory again.

In the waveform write SW event process, first, in step 1401, the address of the write area in the waveform memory 109 and the number of samples to be written are set in the XA register 311 and the sample number register 315. Next, in step 1402, the address of the read area in the RAM 106 where the waveform data to be written in the waveform memory 109 is prepared is set. Next, step 1403
Then, the CPU 104 instructs the X access circuit 304 in FIG. 3 to start writing. In step 1404,
The first 8 of the read area in the RAM 106 as preparation
The sample is read out and written into the FIFO 313, and the process ends. As described above, the X access processing described above is started, and in parallel with the generation of the musical tone waveform, the FIFO3 of FIG.
13 is written to the write area of the waveform memory 109, and the CPU 104 performs FIFO flag write event processing (FIG. 14C) described below to execute FIFO3.
13 is written with waveform data. Such writing of the waveform data is used when writing the waveform data in the external storage device to the waveform memory, or processing the read waveform by the CPU and writing the processed waveform again into the waveform memory. It is also used for writing a waveform in a software sound source to be described later. Further, by providing a buffer area on the waveform memory and sequentially supplying the waveform data of the external storage device to the area while performing loop reproduction of the waveform data of the buffer area by the tone generation channel, the length stored in the external storage device is obtained. Direct reproduction of time waveform data is also possible.

FIG. 14B shows the procedure of the X flag read event process in the flag process of step 1207 in FIG. 12A. This is because the X flag is ON when the reading process from the waveform memory 109 by the CPU 104 is started (when the waveform reading SW event process of FIG. Read data is FIFO
313). First, in step 1411, the waveform data set in the FIFO 313 is read and written in the write area of the RAM 106. Next, in step 1412, it is determined whether the reading is completed by comparing the number of samples in the sample number register 315 with the number of waveform samples actually read from the waveform memory 109 and written into the RAM 106. When the reading is completed, step 141
In 3, the CPU 104 performs a read stop process and ends the process. If the processing has not been completed yet in step 1412, the processing is continued. The read stop process in step 1412 is a process for releasing the state of the read process set in the waveform read SW event process in FIG.

FIG. 14C shows a procedure of an X flag write event process in the flag process of step 1207 of FIG. 12A. This is because the X flag is ON when the CPU 104 has started the writing process to the waveform memory 109 (when the waveform writing SW event process of FIG. 14A has been executed) (that is, when the FIFO 313 has an empty space). This is a process that is executed at some time. First, in step 1421, waveform data to be written next is read from the read area of the RAM 106 and written to a free area of the FIFO 313. Next, in step 1422, the number of samples in the sample number register 315 is compared with the number of waveform samples actually written from the RAM 106 to the FIFO 313, and it is determined whether all the samples to be written have been written. When all the data has been written, it means the end.
In step 1423, the CPU 104 performs a write stop process and ends the process. If the termination condition has not been satisfied in step 1422, the processing is continued. By the write stop processing of step 1423,
The data remaining in O313 is written to the waveform memory 109.

According to the electronic musical instrument of this embodiment described above, since the sample buffer is provided, a surplus time not used for sounding the channel is generated. For the purpose, waveform memory access (for example, CPU access or writing of waveform data returned from the mixer) can be performed during sound generation. In particular, the X access circuit 304 having a function of detecting the access status of the waveform memory 109
Is provided, the CPU 104 refers to the X flag 314, and when it is on, can read and write data more and more and can access at high speed even during sound generation. Further, FI is used as a buffer for X access processing.
Since the FO 313 is provided, access can be performed at a very high speed. Note that the X flag 314 is sent from the CPU 104.
The process of reading and writing data when it is on with reference to
Although the processing is performed during the loop processing of step 04, the processing may be performed using an interrupt. That is, the FIFO 31
3 has free space (when writing from CPU) or F
When there is read data in the IFO 313 (during reading by the CPU), it may be notified to the CPU 104 by an interrupt, and the CPU 104 may access the FIFO 313 accordingly.

According to the electronic musical instrument of this embodiment, since the waveform memory access is made independent of the channel timing, there are the following advantages when the number of accesses is limited. In other words, if the number of sounds is small, there is no effect of the limitation, and all the sounding channels can execute higher-order interpolation (four-point interpolation in the above example). When the number of sounds increases and the number of times of access becomes restricted, it is possible to reduce the interpolation order of some channels of the total number of sounds and to reduce the number of sounds although the interpolation order is reduced.

Further, in the electronic musical instrument of this embodiment,
Since the number of accesses to the waveform memory is managed by the total value, access control is extremely difficult when, for example, a request for X access requires use of 1/3 or 1/4 of the total access time. Easy to do.

According to the electronic musical instrument of this embodiment, DS
Since P is also used for sampling and resampling processing, it is possible to add effects by sampling externally input musical tones or reading waveform data already stored in the waveform memory without complicating the device configuration. After performing such processing, resampling for writing to the waveform memory can be performed again. In the DSP, the waveform processing for reproduction, such as effect addition, and the waveform processing for recording, such as sampling and resampling, can be performed in parallel, so that reproduction and recording can be performed in parallel.

The access operation (process B and capture process) of the waveform memory may be performed during the timing (fixed) of each time-division channel. In this case, since there are four access slots per channel for all sounding channels, each sounding channel performs 0 to 4 sample readings and 4 to 0 X accesses in the remaining slots. Do it.

Regarding how to distribute the 64 accesses of the first half section and the second half section by the processing B (or the fetch processing) and the X access processing, in the above example, once the priority flag 303 indicates X access is prioritized. However, there are cases where it is desired to give priority to two or more accesses. For example, when transferring the waveform data from the external storage means to the waveform memory, or when transferring the waveform data from the waveform memory to the external storage means, it is efficient to perform the transfer according to the data transfer rate of the external storage means. Is good.
It is better to give priority to the number of X accesses required to achieve the speed. In other cases, the number of times of priority of the X access may be arbitrarily set in accordance with the requested speed and the optimum speed of the other party who exchanges the waveform data.

Next, an example in which a software sound source (hereinafter, referred to as a software sound source) is realized by the CPU 104 in the electronic musical instrument of this embodiment will be described. The soft sound source generates a musical sound waveform by executing predetermined software in the CPU 104. The musical tone waveform generated by the CPU 104 is emitted using a predetermined channel of the sound source unit 108.

Note that the software sound source is stored in the ROM by the CPU 104.
The tone generation software is realized by executing the tone generation software 105. From the viewpoint of using the software tone generator, the tone generation software is registered as a driver, and after the driver is started, a predetermined software tone source is executed. API
MIDI (Musical Instruments digital Interface) representing various performance inputs in the (Application Program Interface)
ace) The procedure is to output an event message and perform various processes related to musical sound generation on the software sound source. The CPU 104 is a general-purpose arithmetic processing unit.
A process different from the software sound source is also performed, such as a process of giving a performance input to I, that is, a process of outputting a MIDI event to the API. The process in which the CPU 104 provides a performance input to the API includes, for example, a performance input generated in real time in response to an operation of the keyboard 101.
I or a performance input corresponding to a MIDI event input in real time from an external MIDI device.
Or a sequence of MIDI events is prepared on the RAM 106 (the data on the external storage device 107 may be used).
This is processing such as outputting to a PI.

Referring to FIG. 16, the principle of generating a musical tone of a soft sound source will be described. In FIG. 16, each section of S1 to S4 indicates a time frame as a unit for performing reproduction of a predetermined number of samples (for example, 128 samples). A downward arrow written on the line of “performance input” indicates that a performance input was made at that time. Performance input means API (Application Program Interface) related to software sound source
, Various MIDI events such as note-on, note-off, after-touch, and program change. In the example of FIG. 16, three frames S1 and S3
2 means that there were two performance inputs, and S3 that there was one performance input. The soft tone generator can simultaneously generate a plurality of musical tones for a plurality of channels, and each tone is controlled by a soft tone generator register for a plurality of channels prepared on the RAM 106. When a note-on event (for example, note-on of a key on the keyboard 101) is input as a performance input, the soft tone generator assigns a tone to the soft tone generator register, and assigns the sound of the channel to the soft tone generator register corresponding to the assigned channel. Write various data to be controlled and note-on. When a note-off event is input as a performance input, note-off is written to the software tone generator register corresponding to the corresponding channel. Similarly, for performance inputs other than note-on and note-off (for example, aftertouch change), data corresponding to the performance input is written to the software tone generator register corresponding to the corresponding channel. The data written to the software tone generator register in a certain time frame is always used for the waveform generation calculation from the next time frame regardless of the type of data.

Rectangles 1601 to 1604 of “Waveform generation by CPU” in FIG. 16 indicate sections in which the CPU 104 executes a waveform generation operation. In this waveform generation calculation, a tone waveform for a plurality of channels is generated based on data for a plurality of channels set in a software tone generator register.
The software tone generator register is rewritten according to the performance input,
On the other hand, during the period when there is no performance input, the software tone generator register holds data written in the past. Accordingly, in each of the waveform generation sections 1601 to 1604, a waveform generation calculation corresponding to the performance input detected in the immediately preceding or further previous frame is executed. Since a frame interrupt occurs at the timing of switching frames, the waveform generation calculation in each frame is executed with this frame interrupt as a trigger (FIG. 15B described later).

For example, with respect to three performance inputs detected in the frame S1, a waveform generation operation is performed in a section 1602 triggered by an interruption of the first frame of the next frame S2. The CPU 104 calculates R
Waveform data is generated on the AM 106. The generated waveform data is written into a buffer area prepared on the waveform memory 109 using the remaining time section of the frame. As this buffer area, two buffer areas PB0 and PB0 of the same size prepared at consecutive addresses are used.
1 (the two are collectively called a double buffer).
Writing to the buffer area is performed by the above-described X access processing (particularly, writing processing from the CPU 104 to the waveform memory 109). In addition, the buffer P
B0 and PB1 are used alternately. For example, the waveform data generated in the section 1601 of the frame S1 is written from the RAM 106 to the buffer area PB0 on the waveform memory 109 by the time of disclosure of the next frame,
The waveform data generated in the section 1602 of the frame 2 is written in the buffer area PB1, the waveform data generated in the section 1603 of the frame S3 is written in the buffer area PB0, and the waveform data generated in the section 1604 of the frame S4 is written in the buffer area PB1. ... PB alternately
Write waveform data to 0 and PB1.

The reading and reproducing of the waveform data written in the buffers PB0 and PB1 are performed in the section of the frame next to the frame in which the waveform is generated, triggered by the frame interruption, as shown in "Reading and reproducing" in FIG. That is, the waveform data generated in frame S1 and written in PB0 is the next frame S2, and the waveform data generated in frame S2 is PB0.
The waveform data written in B1 is in the next frame S3, the waveform data generated in frame S3 and written in PB0 is in the next frame S4, and so on, and the waveform data of PB0 and PB1 are alternately read and reproduced. .

FIG. 15A shows the procedure of the soft sound source start SW event processing executed when the soft sound source start SW is turned on in the panel switch processing in step 1206 of FIG. 12A. When the soft sound source start SW is turned on by the user, first, at step 150
In step 1, a sounding channel (0th to 31st channels) used for sounding a tone waveform generated by a soft sound source is assigned, and the assigned channel number is set in a register i. Next, in step 1502, the sound source unit 1
08 is set so that loop reading and reproduction of the double buffer areas PB0 and PB1 are performed by the channel i. This means that the buffers PB0 and PB0 are
B1 so as to alternately read and reproduce them.
This is a process for sending and setting instruction information to the user. Specifically, since the double buffer areas PB0 and PB1 are buffer areas of the same size prepared at consecutive addresses, the start address of the area PB0 is set as the start address (absolute address WA) of the loop, and The value obtained by subtracting (the start address of the area PB0) from the end address of the PB1 is defined as the loop size (relative address LP).
If it is set as A) and the relative address AS is set to 0, the area of PB0 to PB1 is repeatedly read by loop reading. In step 1503, settings such as an envelope parameter and a mixing ratio of a mixer are performed. It should be noted that the envelope parameters set here are merely used for fading in / out of the loop reading, and do not control the envelope of the generated musical sound (temporal change of the musical sound volume). The mixing ratio of the mixer is not a mixing ratio of one musical tone but a mixing ratio for controlling an output destination of a mixed waveform of a plurality of musical tones generated by a soft sound source.

Next, at step 1504, the CPU 104
In order to initially write the musical tone waveform generated in the above as the buffer PB0 in the waveform memory 109, the starting address of the buffer PB0 is set as an initial value in the XA register 311 in FIG. The capacity of the buffer PB0 (1/2 of the loop size LPA) is set. In step 1505, C
The PU 104 performs a write process (X
Preparing for access processing), double buffer PB
0, PB1 is cleared to zero. In step 1506, a note-on is sent to the channel i, a frame interrupt at a predetermined time interval described with reference to FIG. 16 is started, and the process ends. Note that the frame interrupt is sent to the buffer PB0.
This occurs when a return occurs during loop reading of PB1 and PB1 (that is, at the end of reproduction of PB1), and when a loop read intermediate point (LPA / 2) passes (that is, at the end of reproduction of PB0). Although not shown, an interrupt generation circuit for generating a frame interrupt is provided inside the sound source 108. Instead of the interruption, the CPU may check the current value of the address of the tone generation channel set for “reading and reproducing” to detect the timing at which the frame changes.

FIG. 15B shows a procedure of a frame interrupt process executed by a frame interrupt generated for each time frame of the predetermined time described with reference to FIG. When a frame interrupt occurs, first, in step 1511, a tone waveform corresponding to the performance input currently set in the software tone generator register is generated on the RAM 106. This is shown in FIG.
Corresponds to the waveform generation operations 1601 to 1604 executed for each frame interrupt. Next, step 15
12 is a waveform memory 1 in which the generated tone waveform is to be written.
09 (PB0 or PB1)
) And the number of samples to be written (１ ／ of the loop size LPA) are set in the XA register 311 and the sample number register 315. As described with reference to FIG. 16, the buffer areas PB0 and PB1 are used alternately as the write area. Next, in step 1513, C
The PU 104 instructs the X access circuit 304 in FIG. 3 to start writing. In step 1514, the first eight samples of the musical sound waveform are written into the FIFO 313 as preparation, and the process ends. Thereafter, every time the data of the FIFO 313 is written to the waveform memory by the X access processing (X flag is set to 1), the remaining musical tone waveform samples are sequentially transferred to the FIFO memory by the processing similar to the processing of FIG. Supplied to

As described above, the aforementioned X access processing is started, and the musical tone waveform generated in step 1511 is written into the buffer area PB0 or PB1 of the waveform memory 109. On the other hand, according to the process of FIG. 15A, the double buffer PB0
Since the process of alternately reading and reproducing PB1 and PB1 has been started, a tone waveform is generated for each frame interrupt and written in the double buffer as shown in FIG. 15B. Pronounced as The tone generated by the soft tone generator is input to the mixer 204 on the i-th channel. Or write it back to the waveform memory 109.

Also, by adjusting the F number (the pitch PITCH used in the process A of FIG. 3) of the reading process of the double buffers PB0 and PB1 in the i-th channel, the reproduction pitch can be adjusted. Sampling can also be performed. For example, the i-th channel of the tone generator 108 for outputting a musical tone waveform generated by a soft tone generator operates at a sampling frequency of 48 kHz, and the CPU 104
When generating a tone waveform at kHz, the F-th channel
The number may be set to 0.5. In this case, interpolation is performed by the interpolation circuit 326 by cutting off higher harmonic portions so that aliasing noise does not occur even at a sampling frequency of 48 kHz.

In a conventional soft tone generator, a CP is used every sampling cycle for reading and reproducing as shown in FIG.
U was interrupted, and the tone waveform generated by the CPU was DMA-transferred to the tone generator unit for each interrupt. Therefore, the CPU was frequently interrupted. In the soft sound source of this embodiment,
When the CPU 104 performs the processing for each frame interrupt, the CPU 104 automatically performs the X access processing thereafter.
Since the data is reproduced by writing to the CPU, the interrupt processing for the CPU can be reduced.

When using the function of the software sound source,
As described with reference to FIG. 16, it is necessary to hold the performance input in the section of the predetermined frame. Do it.

FIG. 17 shows a modification of the X access circuit 304 of FIG. The XA register 311 in FIG. 3 is replaced with an XA1 register 1701, an XA2 register 1702, and a selector 1703, and the selectors 312 and F in FIG.
The FIFO 313 is replaced with a FIFO 1704, a latch 1705, and a selector 1706. Other parts are the same as those in the above-described embodiment.

XA1 register 1701 and FIFO1
Reference numeral 704 denotes a register for setting an access address and a FIFO for setting access data when the CPU 104 accesses the waveform memory 109 in the X access processing.
It is. XA2 register 1702 and latch 1705
Is the output line 22 from the mixer 204 in the X access processing.
3 when writing to the waveform memory 109 via
Register and mixer 20 for setting access address
4 is a latch for storing data from the memory 4. With this configuration,
The selectors 1703 and 1706 are switched in a time-division manner in the section of the X access processing to write the waveform data returned from the mixer 204 into the waveform memory 109,
The access of the waveform memory 109 from the CPU 104 is
Be able to do it in parallel.

In particular, although waveform data is returned from the mixer 204 every sampling period, the waveform data cannot be discarded, so that it is always stored in the latch 1705. At least once in the X access processing section for each sampling period, the selector 1703 performs the X access processing.
The A2 register 1702 is selected, and the selector 1706 selects the latch 1705, and the waveform data of the latch 1705 is written to the address specified by the XA2 register 1702. In other sections of the X access process, the selector 1703 selects the XA1 register 1701 and the selector 1706 selects the FIFO 1704, so that the CPU 104 accesses the waveform memory 109. The function of sequentially incrementing the addresses of the XA1 register 1701 and the XA2 register 1702 is the same as that described with reference to FIG. In the section of the X access processing, it is necessary to always perform the writing of the waveform data of the latch 1705 with priority once, but it is possible that the section of the X access processing itself cannot be secured. It is preferable that the priority flag 303 be turned on so that the access can be performed several times in the X access processing.

With such a configuration, for example, a sampled or resampled waveform is written from the mixer 204 to the waveform memory 109 via the latch 1705, and when the waveform is accumulated on the waveform memory 109 to a certain extent, the CPU 104
By reading the waveform data and sending it to an external storage device (such as a hard disk), real-time hard disk recording can be performed. Compared to the processing speed of the waveform data written once in one sampling cycle and passing through the latch 1705, the processing speed of the read processing by the CPU 104 is faster. Particularly, the reading speed is further increased because the FIFO is used. Therefore, the data accumulated on the waveform memory 109 is immediately
The data can be read in U104 and written to a hard disk or the like.

In the above embodiment, the processing A operation circuit 321 and the processing B operation circuit 325 are independent in the read / write circuit 202 in FIG.
Alternatively, the processing A and the processing B may be performed by combining the processing circuit 1 and the processing B operation circuit 325 into one operation circuit in a time-sharing manner.

In the above embodiment, the waveform samples in the waveform memory are in a 16-bit uncompressed format, but may be in another format. For example, an 8-bit uncompressed format or an 8-bit compressed format may be used while 16 bits can be read with one access. However, in this case, since the number of samples and the number of accesses are different, it is necessary to adjust them. In the case of the compression format, reproduction cannot be performed unless samples are continuously read out, so that it is necessary to take measures in skipping reading.

When a DRAM is used as the waveform memory, the refresh is always required, so that the refresh may be performed in the X access processing section. Also, reading / writing of the waveform memory from the CPU is as follows.
It is advisable to respond according to the degree of urgency. For example, when the urgency of the waveform memory access from the CPU is low, the access is performed using an empty time slot not used in the sound source channel. When the degree of urgency is high, a portion for waveform memory access from the CPU is secured first, and the rest is used for the sound source channel.

Further, in the above embodiment, as shown in FIGS. 8 and 9, continuous waveform memory access is performed in the front slot of the first half and the second half of the processing B and the fetch, but not in the front. Is also good. For example, the first half /
X access processing may be performed in the front slot in the latter half section, and continuous waveform memory access for each channel may be performed in the rear slot. However, in this case, for example, after the processing of the first half section 804 of FIG. 8 is completed and all the samples necessary for interpolation are prepared in the waveform buffer, it is necessary to start the interpolation processing of the first half section 806 of the interpolation ( The same applies to the latter half processing). Therefore, it is necessary to shift the section in which interpolation is performed (it suffices to start the interpolation first-half process after the capture first-half process is completed and start the interpolation second-half process after the capture second-half process is completed). Further, the time slots of the X access processing may be distributed in the first half section or the second half section.

Further, in the above embodiment, as shown in FIGS. 8 and 9, each processing is executed in a section obtained by dividing one sampling period into a first half and a second half, but the method of dividing the section is not limited to this. . For example, one sampling cycle is 1 /
.. May be divided into 3, 1/4,... And each processing may be performed in units of those sections. Also, instead of equal division,
Irregular sections may be divided. Further, one sampling period may be used as a unit without dividing the section. However, it is necessary to ensure that the ARAM is not rewritten by the process A before the address is sent out in the process B and the waveform memory is accessed.
For that purpose, for example, if you do not divide the section,
It is necessary to adopt a method of preparing two sets of the address RAM and alternately using two sets of the address RAM for rewriting the address in the process A and sending out the address in the process B. According to the method in which one sampling cycle is divided into the first half and the second half, processing A and processing B can be alternately performed by one set of ARAM, so that the circuit configuration can be simplified and rationalized.

[0133]

As described above , according to the present invention,
It is possible to record only some of the musical tone waveforms for a plurality of channels.

[Brief description of the drawings]

FIG. 1 is an overall block diagram of an electronic musical instrument to which a waveform memory sound source device according to the present invention is applied.

FIG. 2 is a block diagram of a tone generator unit to which the waveform memory tone generator according to the present invention is applied;

FIG. 3 is a detailed diagram of a control register and a read / write circuit.

FIG. 4 is a configuration diagram of a control RAM.

FIG. 5 is a diagram showing a memory map of an address RAM;

FIG. 6 is a configuration diagram of a waveform buffer;

FIG. 7 is a diagram showing a method of using a FIFO.

FIG. 8 is a timing chart of a main part of the read / write circuit.

FIG. 9 is a diagram showing a state of a channel during each processing of FIG. 8;

FIG. 10 is a diagram showing a microprogram and mixer setting excitation (part 1);

FIG. 11 is a diagram showing a microprogram and mixer setting excitation (part 2);

FIG. 12 is a flowchart of a main routine and a key-on event processing routine.

FIG. 13 is a flowchart of a sampling SW event processing routine and a resampling SW event processing routine.

FIG. 14 is a flowchart of a waveform read (write) SW event processing routine, an X flag (read) event processing routine, and an X flag (write) event processing routine.

FIG. 15 is a flowchart of a soft sound source start SW event processing routine and a soft sound source frame interrupt processing routine;

FIG. 16 is a diagram for explaining the principle of generating a musical tone of a soft sound source.

FIG. 17 is a diagram showing a modification of the X access circuit.

[Explanation of symbols]

101: keyboard, 102: display unit, 103: switch group (SW), 104: central processing unit (CPU), 105:
Read only memory (ROM), 106: random access memory (RAM), 107: external storage device, 108
... Sound source unit, 109 ... Waveform memory, 110 ... External circuit, 1
11 delay memory, 112 digital-to-analog converter (DAC), 113 sound system (SS), 11
4 Bus lines 114, 201 Control register, 202
... Read / write circuit, 203 ... Volume change control circuit, 204 ...
Mixer, 205: signal processing circuit, 206: interface, 301, 302 ... register, 303: priority flag, 304: X access circuit, 311: XA register,
312 ... selector, 313 ... FIFO (First I
n First Out (first-in, first-out) eight-stage registers), 314: X flag, 315: sample number register, 321: processing A operation circuit, 322: address RAM
(ARAM), 323 ... accumulator (ACC), 3
24: control RAM, 325: processing B operation circuit, 326 ...
Interpolation circuits, 327: Waveform buffer, 328: Capture circuit, 329, 330 ... Selector (SEL).

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-94896 (JP, A) JP-A-63-2097 (JP, A) JP-A-1-116594 (JP, A) JP-A-5-95 53572 (JP, A) JP-A-4-61097 (JP, A) JP-A-7-175477 (JP, A) JP-A-7-271363 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G10H 7/00 511

Claims (1)

(57) [Claims] 1. A storage means for recording a musical tone waveform, a waveform supplying means for supplying musical tone waveforms for a plurality of channels at a predetermined sampling period, and a signal processing means for performing signal processing on the supplied musical tone signal. By inputting the musical tone waveforms for a plurality of channels supplied from the waveform supply unit and the musical tone signal supplied from the signal processing unit and appropriately mixing them to execute a process of obtaining a mixing result, at least the first and second processes are performed. Mixing means for obtaining and outputting second and third mixing results, respectively; writing means for writing the first mixing result output from the mixing means into the storage means; and second means output from the mixing means. Output means for supplying the result of mixing to an external sound system. The means is supplied with the tone signal of the third mixing result, and the signal processing means performs signal processing for recording or signal processing for reproduction on the tone signal of the third mixing result. Sound source device.