JP3141607B2 - Semiconductor input protection element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor input protection device, and more particularly, to a structure of an input protection device of a complementary MOS semiconductor device.

[0002]

2. Description of the Related Art Heretofore, the structure of an input protection element of a complementary MOS semiconductor device of this kind has been as shown in FIGS. 4 (a) and 4 (b). That is, the semiconductor device has an N-type well 14 selectively formed on the surface of the P-type silicon substrate 1, and includes an N-type diffusion layer 16 and a P-type diffusion layer 17 connected to the input terminal 11 in the N-type well 14. Having a P-type silicon substrate 1
A N-type diffusion layer 15 facing the P-type diffusion layer 17 at the surface portion of the N-type well 14 where the N-type well 14 is not formed, and the N-type diffusion layer 15 is formed of an insulating film 8 having a contact hole C1.
Is connected to the ground terminal by the aluminum alloy film wiring 9 which selectively covers the wiring. Further, the N-type diffusion layer 16, P
The mold diffusion layer 17 is connected to the input terminal 11 by the aluminum alloy film wiring 10. When an excessive voltage of the positive electrode is applied to the input terminal 11, the P-type diffusion layer 17, the N-type well 14,
PNP comprising P-type silicon substrate 1 and N-type diffusion layer 15
The N-type thyristor is turned on, that is, turned into a low impedance state, thereby preventing a high voltage from being applied to the internal circuit, particularly to the gate oxide film of the MOS transistor.

The N-type diffusion layer 16 raises the potential of the N-type well 14 when an excessive voltage is applied to the input terminal, and makes it difficult for the parasitic thyristor to enter the ON state with respect to a pulse having a slow rising time. is there.

[0004]

The conventional input protection element has a PN function when an excessive positive voltage is applied to the input terminal.
The thyristor of the PN structure is turned on to protect the internal circuit, but if an excessive negative voltage is applied to the input terminal,
Since the thyristor does not enter the ON state in principle, there is a problem that a high negative voltage is applied to the internal circuit and the internal circuit cannot be protected.

[0005]

A semiconductor input protection device according to the present invention comprises a second conductivity type well selectively formed in a first conductivity type region on a surface portion of a semiconductor substrate and a second conductivity type well. A first conductivity type well formed shallower, a first first conductivity type diffusion layer formed on a surface portion of the second conductivity type well where the first conductivity type well is not formed, A first second conductivity type diffusion layer formed in the first conductivity type region so as to face a side of the second conductivity type well where the first first conductivity type diffusion layer is not formed; A second first-conductivity-type diffusion layer and a second second-conductivity-type diffusion layer formed at a predetermined distance from the surface of the one-conductivity-type well; and the first first-conductivity-type diffusion layer and the first
Wiring means for connecting each of the second conductive type diffusion layers to the fixed potential supply terminal, and connecting the second first conductive type diffusion layer and the second second conductive type diffusion layer to an input terminal and an internal circuit, respectively. And second wiring means for connecting the second wiring means.

[0006]

FIG. 1 (a) is a plan view of a semiconductor chip showing a first embodiment of the present invention, and FIG. 1 (b) is an AA of FIG. 1 (a).
It is a line sectional view.

In this embodiment, a P-type silicon substrate 101 is used.
This surface portion selectively formed N-type well 102 (a depth of about 5 [mu] m, the impurity concentration of about 1 × 10 ¹⁶ cm ^-3) and the N-type well 102 (impurity concentration of about 1 × 10 ¹⁶ cm ^-3) A shallower P-type well 103 (about 3 μm deep,
N-type well 1 having an impurity concentration of about 5 × 10 ¹⁶ cm ⁻³ )
02, the first P-type diffusion layer 106 (having a depth of about 0.4 μm) formed on the surface where the P-type well 103 is not formed.
m, an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ ), and formed on the surface of the P-type silicon substrate 101 so as to face the side of the N-type well 102 where the first P-type diffusion layer 106 is not formed. A second P-type diffusion layer 107 (depth about 0.3 μm, impurity concentration about 1 × 10 ²⁰ cm ⁻³ ) and a second P-type diffusion layer formed at a predetermined distance from the surface of P-type well 103 Diffusion layer 104 (depth about 0.4 μm, impurity concentration about 1 × 10 ²⁰
cm ^-3 ) and the second N-type diffusion layer 105 (depth of about 0.3
μm, an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ ), and first wiring means (aluminum-based alloy film wiring 109) for connecting the P-type diffusion layer 106 and the first N-type diffusion layer 109 to the ground potential supply terminal. ), And second wiring means (aluminum-based alloy film wiring 110) for connecting the second P-type diffusion layer 104 and the second N-type diffusion layer 105 to the input terminal 111 and an internal circuit (not shown), respectively. Things. Note that the distance d1 between the second P-type diffusion layer 104 and the second N-type diffusion layer 105 is 3 μm,
The distance d2 between 7 and the second P-type diffusion layer 104 was 8 μm, and the distance d3 between the second N-type diffusion layer 105 and the first P-type diffusion layer 106 was 8 μm.

In the case of a DRAM in which peripheral circuits are constituted by CMOS, the memory cell array forms a P-type well similar to the P-type well 103 in a deep N-type well formed in the same step as the N-type well 102, and there. An nMOS transistor and the like are formed. In the peripheral circuit, a pMOS transistor and an nMOS transistor are formed in an N-type well and a P-type well which are formed in steps different from those of the N-type well 102 and the P-type well 103, respectively. The first N-type diffusion layer 107 and the second N-type diffusion layer 105 are formed in the same step as the high-concentration N-type diffusion layers in the source / drain regions of the nMOS transistor of the peripheral circuit. Diffusion layer 106 and second
P-type diffusion layer 104 is a source of a pMOS transistor.
It can be formed in the same step as the high-concentration P-type diffusion layer in the drain region. Therefore, this embodiment can be realized as an input protection element for a deep well type DRAM without requiring a special well forming step and a diffusion layer forming step.

When an excessive positive voltage is applied to the input terminal 111 with respect to the ground terminal, the P-type well 103, the N-type well 102, the P-type silicon substrate 101 and the first N-type diffusion layer 107 are formed. The thyristor having the PNPN structure is turned on and comes out to the ground terminal. Also, input terminal 1
When an excessive voltage of a negative electrode is applied to the ground terminal 11 with respect to the ground terminal, an NPNP structure formed by the second N-type diffusion layer 105, the P-type well 103, the N-type well 102, and the first P-type diffusion layer 106 is formed. The thyristor is turned on to prevent a high voltage from being applied to the internal circuit.

In this embodiment, the on-state voltage Vh1 of the thyristor having the PNPN structure and the current Ih1 necessary to maintain the on-state are about 5 volts and about 1 mA, respectively.
It is. Also, the on-state voltage Vh2 of the NPNP-structure thyristor and the current Ih2 required to maintain the on-state
Is about 3 volts and about 1 mA in this embodiment.

The values of Vh1, Ih1, Vh2, and Ih2 depend on the density and size of the parts constituting the thyristor. That is, the distance d2 between the first N-type diffusion layer 107 and the P-type well 103 and the first P-type diffusion layer
It can be adjusted by the distance d3 between the second N-type diffusion layer 105 and the second N-type diffusion layer 105. Vh1 and Ih1 can be increased by increasing d2 in the case of an excessive voltage of the positive electrode, and Vh2 and Ih by increasing d3 in the case of an excessive voltage of the negative electrode.
2 can be increased. Also, regarding the trigger voltage (Vt) and the trigger current (It) for the parasitic thyristor to enter the ON state, when an excessive voltage of the negative electrode is applied, the pulse is like a normal noise with a slow rise. In this case, since the potential difference between the second N-type diffusion layer 105 and the P-type well 103 is hardly generated, the parasitic thyristor is hardly turned on, and Vt and It at this time have a fast rising like an electrostatic discharge pulse. In this case, the trigger voltage and the trigger current are higher than the trigger voltage, but in order to further increase the trigger voltage, d
It is sufficient to reduce 1 and increase the distance of d3. Vt and It when an excessive voltage of the positive electrode is applied can be increased by reducing d1 and increasing d2.

FIG. 2 is a plan view showing a second embodiment of the present invention.

In this embodiment, the P-type well 203 includes:
On the side where the first P-type diffusion layer 206 provided opposite to the P-type well 203 is not provided, the third N-type diffusion layers 212-1 and 212-1 are formed.
12-2 is provided and connected to the aluminum-based alloy film wiring 210.

Second N-type diffusion layer 205 and P-type well 20
Since it is difficult for a potential difference to occur between the signal and the pulse No. 3, only Vt for a pulse such as a normal noise having a slow rise can be increased.

FIG. 3 is a plan view showing a third embodiment of the present invention.

In this embodiment, an N-type diffusion layer 307a and a P-type diffusion layer 306a are provided adjacent to the first N-type diffusion layer 307 and the first P-type diffusion layer 306, respectively, and an aluminum-based alloy film for power supply wiring is provided. This is connected to the wiring 313, and can protect the internal circuit even when an excessive voltage is applied to the input terminal with respect to the power supply wiring (313).

[0017]

As described above, according to the present invention, the structure of the input protection element is the same as that of a so-called DIAC element in which a thyristor having a PNPN structure and a thyristor having a NPNP structure are connected in parallel. By setting the impedance to an ON state, that is, a low impedance with respect to the excessive input, an effect of preventing a high voltage from being applied to the internal circuit is obtained. Further, a trigger voltage (Vt) and a trigger current (It) for entering an ON state, which are important parameters of the input protection element, an ON state voltage (Vh), and a current required for maintaining the ON state. (Ih) can be controlled by changing the horizontal distance of the pattern without changing the manufacturing process. In other words, the effect of the input protection device of the present invention is to discharge efficiently both positive and negative electrostatic pulses, have a high current withstand capability, and control the characteristics of the protection device by the mask pattern at the time of its formation. In addition, the present element can be simultaneously manufactured by a manufacturing process for forming an internal circuit to be protected without requiring a special manufacturing process. Further, the process of forming the input protection element of the present invention does not require any special process, and can be formed by a CMOS process using a deep well such as a DRAM of 16M or more, so that it can be applied to an extremely wide range of applications. .

[Brief description of the drawings]

FIG. 1 is a plan view (FIG. 1A) and a sectional view (FIG. 1B) of a semiconductor chip showing a first embodiment of the present invention.

FIG. 2 is a plan view showing a second embodiment of the present invention.

FIG. 3 is a plan view showing a third embodiment of the present invention.

FIG. 4 is a plan view of a semiconductor chip showing a conventional example (FIG.
(A)) and sectional drawing (FIG. 4 (b)).

[Explanation of symbols]

1,101 P-type silicon substrate 102,202,302 N-type well 103,203,303 P-type well 104,204,304 Second P-type diffusion layer 105,205,305 Second N-type diffusion layer 106,206 , 306, 306a First P-type diffusion layer 107, 207, 307, 307a First N-type diffusion layer 8, 108 Insulating film 9, 109, 209, 309 Aluminum alloy film wiring (ground wiring) 10, 110, 210, 310 Aluminum-based alloy film wiring (input signal line) 11, 111 Input terminal 212-1, 212-2 Third N-type diffusion layer 313 Aluminum-based alloy film wiring (power supply wiring)

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 21/8238 H01L 27/04 H01L 27/092 H01L 29/78

Claims (2)

(57) [Claims] 1. A semiconductor device comprising: a second conductivity type well selectively formed in a first conductivity type region on a surface portion of a semiconductor substrate; and a first conductivity type well formed shallower than the second conductivity type well. A first first conductive type well formed on a surface of the second conductive type well where the first conductive type well is not formed;
A first conductivity type diffusion layer, and a first second conductivity type formed in the first conductivity type region so as to face a side of the second conductivity type well where the first first conductivity type diffusion layer is not formed. A diffusion layer;
A second first-conductivity-type diffusion layer and a second second-conductivity-type diffusion layer formed at a predetermined distance from a surface portion of the first-conductivity-type well; First wiring means for connecting each of the first and second conductive type diffusion layers to a fixed potential supply terminal; and connecting the second first and second conductive type diffusion layers to an input terminal and a second terminal, respectively. A second wiring means for connecting to an internal circuit. 2. The semiconductor input protection device according to claim 1, wherein the first conductivity type is P-type, and the fixed potential is a ground potential.