JP3136692B2 - Method for manufacturing insulated gate semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device having an ultra-shallow junction, a so-called MIS (Metal Insulator S).
The present invention relates to a method for manufacturing an insulated gate semiconductor device which is suitable for application to the manufacture of a semiconductor device.

[0002]

2. Description of the Related Art In recent years, in order to increase the memory capacity, MIS
Insulated gate semiconductor devices such as FETs (field effect transistors) are required to be miniaturized. FIG. 3 is a schematic enlarged perspective view showing a part of an example of the MIS type semiconductor device in section.

In FIG. 3, reference numeral 1 denotes a semiconductor substrate made of Si or the like, on which a thick element isolation insulating layer 12 made of SiO ₂ or the like is formed by thermal oxidation or the like. And on it surrounded by substrate 1 of the surface of the isolation insulating layer 12, of the layer structure of such thin gate oxide film via a (not shown) such as poly Si (polycrystalline silicon) and WSi _X (tungsten silicide) Gate electrode 1 of so-called polycide structure
The diffusion layer 13 is formed on both sides of the gate electrode 10 by ion implantation or the like to form a source / drain region, on which a source electrode 14 and a drain electrode 15 are adhered. .

In this case, as the miniaturization of the semiconductor element progresses, it is necessary to reduce the gate length L in the channel length direction. Accordingly, the reduction in the lateral diffusion length when forming the diffusion layer 13 is required. Is required. That is, the diffusion layer 1
If the gate electrode 3 is deep, the diffusion in the lateral direction becomes large. Therefore, in order to reduce the gate length, it is necessary to form a shallower junction region.

FIG. 4 shows changes in the gate length and the junction depth with the increase in the capacity of the dynamic random access memory (DRAM). As can be seen from the relationship of the junction depth, as the gate length is reduced, the junction depth becomes smaller,
For example, to obtain a capacity of 16 Mbits or more , 0.1
An ultra-shallow junction of about μm or less is required.

As a method for activating a source / drain region and a gate electrode after ion implantation while suppressing thermal diffusion as much as possible in order to obtain such a shallow junction, for example, RTA (Rapid Thermal Annealing) is popular. Is being considered. However, as described above, 0.1 μm
It is difficult to stably form an ultra-shallow junction of a degree or less by RTA by lamp annealing.

For this reason, the thermal diffusion is further suppressed,
As a method of realizing an ultra-shallow junction of about 0.1 μm or less,
Activation by ELA (Excimer Laser Anneal) has been proposed (for example, the present inventors et al., Proceedings of the 51st Autumn Japan Society of Applied Physics, 1990, 28a-E-9, p63).
5).

On the other hand, in order to speed up signal transmission, poly-Si
There has been proposed a polycide gate structure having a lower sheet resistance than that of the prior art. The polycide gate structure has a configuration of laminating a refractory metal silicide such as WSi _x onto poly Si. As described above, this polycide gate structure has the advantages that the resistance is smaller than that of the poly-Si gate and that the adhesion is better than that of the refractory metal silicide gate.

However, it was subjected to the above-mentioned ELA (excimer laser annealing) to such polycide gate, with a relatively low energy density of about 250 mJ / cm ^2, for example, WSi _X refractory metal silicide
Was sometimes peeled off. This is thought to be due to significant mechanical stress following ELA due to local high temperature, rapid thermal quenching.

However, the energy density required for forming the source / drain regions is such that a high recrystallization degree and a low sheet resistance are obtained as shown in FIG. energy density required for the are of the order of 800 mJ / cm ^2, a much higher energy density than 250 mJ / cm ² above.

[0011] Accordingly, it has been desired to avoid such peeling of silicide and to enable ELA with high energy density.

[0012]

SUMMARY OF THE INVENTION The present invention makes it possible to achieve high energy density ELA by avoiding peeling of the refractory metal silicide in the polycide gate structure as described above. It is an object of the present invention to increase the memory capacity of an integrated circuit such as a memory device by obtaining a shallow junction, that is, a so-called ultra-shallow junction, so that an insulated gate semiconductor device having a fine structure can be obtained.

[0013]

FIG. 1 is a schematic enlarged cross-sectional view of an example of an insulated gate type semiconductor device according to the manufacturing method of the present invention. In the present invention, a step of forming a gate insulating layer 2 on a semiconductor substrate 1, a step of forming a gate electrode 10 on the gate insulating layer 2, and a step of forming an impurity on the semiconductor substrate 1 using the gate electrode 10 as a mask. And an excimer laser annealing (ELA) step of excimer laser light irradiation during or after this ion implantation step. And
In particular, the step of forming the gate electrode 10 includes the steps of forming the lower Si layer 3, the refractory metal silicide layer 4,
And a step of sequentially forming an upper Si layer 5 functioning as a heat absorbing film of 500 °.
With the configuration of 0, rapid cooling immediately after ELA can be eased.

This is because the upper Si layer 5 functions as a heat absorbing layer with respect to the refractory metal silicide 4, whereby rapid heating and cooling of the silicide 4 can be suppressed, and the mechanical stress of the silicide 4 after ELA is reduced. It is thought that this is due to the fact that it can be reduced.

Thus, ELA capable of forming an ultra-shallow junction
Technology can be applied to a polycide gate structure, which enables formation of an ultra-shallow junction and miniaturization of the gate length in a MIS semiconductor device having a polycide gate structure with low resistance and good adhesion. In an integrated circuit such as a semiconductor memory device, the memory capacity can be increased.

[0016]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of an insulated gate type semiconductor device according to an embodiment of the present invention; Each example is an example of a MISFET having a polycide gate structure, and shows a case where an impurity is implanted into a diffusion layer, that is, a source / drain region, and then activation is performed by ELA to form a shallow junction to obtain an ultrashort gate length structure.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate made of, for example, Si, on which a thickness of 8 is formed by, for example, thermal oxidation.
A gate insulating layer 2 of about 0 ° made of SiO ₂ or the like is formed. And on this, after depositing a poly-Si layer 3 so DOPOS doped eg P (phosphorus) by such CVD (chemical vapor deposition), further a refractory metal silicide 4 such WSi _X CVD, or the like Then, a Si layer 5 having a thickness of, for example, 500 ° is deposited thereon by, for example, LP-CVD (low pressure CVD) or the like.

The Si layer 5 may be a DOPOS, for example, similarly to the lower Si layer 3 described above, and may have a low resistance by ion implantation at the time of forming a diffusion layer, ie, a source / drain region described later, or by ELA described later. It may be.

The gate insulating layer 2, the Si layer 3,
Anisotropic etching such as RIE (Reactive Ion Etching) is performed on the refractory metal silicide 4 and the Si layer 5 by applying photolithography or the like, and is patterned into a required gate electrode pattern. A gate electrode 10 composed of the silicide 4 and the poly-Si layer 5 is formed so that the upper and lower surfaces are polycide.

Next, using this gate electrode 10 as a mask,
After ion implantation of As ⁺ or the like into the semiconductor substrate 1 to form the source / drain regions 8A and 8B, 800 mJ
/ Cm ² , one pulse ELA to a depth of 0.06 μm
A shallow diffusion layer was formed. Then, although not shown, a source / drain electrode, a wiring layer, and the like are formed to obtain the insulated gate semiconductor device of the present invention.

At this time, the ELA could be performed without the exfoliation of the silicide 4 due to the heat absorption of the Si layer on the silicide 4, in this case, the poly-Si layer 5.

Next, another example of the insulated gate semiconductor device of the present invention will be described with reference to an enlarged schematic sectional view of FIG. 2, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

In this case, SiO 2 is provided on both sides of the gate electrode 10.
_The LDD (Light)
ly Doped Drain) structure is shown.

[0024] In this case, after patterning the gate electrode 10 with the same method as the example described in FIG. 1 described above, which performs first low concentrations of As ⁺ ion implantation, such as a mask, lightly doped source / drain Regions 6A and 6B are formed.

Thereafter, for example, an SiO ₂ layer is entirely deposited by CVD or the like, and the gate electrode 1 is deposited by RIE or the like.
Anisotropic etching is performed in the thickness direction until the upper surface of the substrate 0 and the surface of the base 1 are exposed, and the sidewalls 7 are formed while leaving SiO ₂ on both sides of the gate electrode 10 with a substantial thickness. . Then, using the side wall 7 and the gate electrode 10 as a mask, ion implantation of As ⁺ or the like is performed to form the source / drain regions 8A and 8B.
As in the example described with reference to FIG.
performing one pulse of ELA energy density of mJ / cm ^2, without causing the peeling of the silicide 4, 0.0
By activating the diffusion region having a depth of about 6 μm, an insulated gate semiconductor device having an ultra-shallow junction was obtained.

In each of the above-described examples, the thickness of the upper poly-Si layer 5 is set at 500 °, but this thickness is set at 200 ° to 1500 °.

This means that the thickness is less than 200 °, for example 10
When the thickness is about 0 °, the heat absorption becomes insufficient, the influence on the silicide 4 becomes large, and there is a possibility of peeling. When the thickness exceeds 1500 °, the flatness of the upper surface is reduced. This is because there is a possibility that the wiring layer and the like on the wiring layer may be disconnected and become disconnected.

Further, the upper layer of poly-Si layer 5 because it has a function as a heat absorbing film for protecting the silicide 4 consisting of WSi _X, while avoiding the peeling of the silicide 4 as described above, the heat absorption layer The arrangement in the upper layer makes it possible to perform annealing using the gate electrode 10 itself as a mask, that is, to perform self-aligned annealing.

Further, as described above, this Si layer 5 is
By forming the POS film or the low resistance film by ion implantation, the ohmic contact between the gate electrode 10 and the other wiring layer in the upper layer can be improved.

Further, in each case, a shallow junction of about 0.1 μm can be formed.
The lateral diffusion length from the lower part of the drain regions 8A and 8B to the lower part of the gate electrode 10 can also be reduced,
The parasitic capacitance due to the overlap between the gate electrode 10 and the source / drain regions 8A and 8B can be reduced. Transmission can be speeded up.

The present invention is not limited to the above-described embodiment, but can be modified in various ways. For example, in each of the above-described embodiments, after the ion implantation of the source / drain regions 8A and 8B, The diffusion layer has been formed by annealing with ELA, but the diffusion layer can also be formed by light doping in a gas, that is, laser irradiation such as an excimer laser in an impurity gas such as PH ₃ or AsH _3. In this case, the steps of the above-described ion implantation and laser annealing can be reduced to one step.

[0032]

As described above, according to the insulated gate semiconductor device of the present invention, an ultra-shallow junction can be formed without peeling of the silicide layer, thereby reducing the gate length. Ultrafine structure can be achieved, and the memory capacity of an integrated circuit such as a memory device can be increased.

Also, in such an insulated gate type semiconductor device having an ultrafine structure, a polycide gate structure having a low sheet resistance can be employed, and a diffusion region is formed by ELA. , The speed of signal transmission can be increased.

Further, self-aligned annealing can be performed using the gate electrode as a mask, and the manufacturing process can be simplified.

Further, a diffusion layer can be formed by light doping, and the number of steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic enlarged sectional view of an example of the insulated gate semiconductor device of the present invention.

FIG. 2 is a schematic enlarged cross-sectional view of another example of the insulated gate semiconductor device of the present invention.

FIG. 3 is a schematic enlarged perspective view of an example of an insulated gate semiconductor device.

FIG. 4 is a diagram showing a relationship between a gate length and a junction depth.

FIG. 5 is a diagram showing a change in recrystallization degree and sheet resistance with respect to a pulse energy density of a laser.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor base 2 Gate insulating layer 3 Si layer 4 Refractory metal silicide 5 Si layer 6A Low concentration source / drain region 6B Low concentration source / drain region 7 Side wall 8A Source / drain region 8B Source / drain region 10 Gate electrode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-195870 (JP, A) JP-A-61-150376 (JP, A) JP-A-1-205468 (JP, A) JP-A-3-205 209775 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/336 H01L 29/78

Claims (1)

(57) [Claims] 1. A step of forming a gate insulating layer on a semiconductor substrate, a step of forming a gate electrode on the gate insulating layer, and ion-implanting impurities into the semiconductor substrate using the gate electrode as a mask. An excimer laser annealing step of irradiating an excimer laser beam during or after the ion implantation step, wherein the step of forming the gate electrode comprises a lower Si layer, a high melting metal silicide Forming a layer and an upper Si layer as a heat-absorbing film having a thickness of 200 ° to 1500 ° sequentially, wherein quenching after annealing by excimer laser light irradiation is reduced by heat absorption by the upper Si layer. Of manufacturing an insulated gate semiconductor device.