JP3135888B2 - Burn-in inspection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe card using a probe card which is used for simultaneously inspecting a plurality of integrated circuits of chips formed on a semiconductor wafer in a wafer state.
The inspection method .

[0002]

2. Description of the Related Art In recent years, there has been remarkable progress in miniaturization and price reduction of electronic equipment equipped with a semiconductor integrated circuit device, and accordingly, demands for miniaturization and price reduction of the semiconductor integrated circuit device have increased. ing.

Normally, in a semiconductor integrated circuit device, after a semiconductor chip and a lead frame are electrically connected by bonding wires, the semiconductor chip is supplied in a state of being sealed with resin or ceramic, and is mounted on a printed circuit board. You.

Hereinafter, a conventional burn-in apparatus for performing a burn-in test on a resin-sealed semiconductor chip will be described with reference to the drawings.

FIG. 5 schematically shows the structure of a conventional burn-in device. The burn-in device 100 shown in FIG.
A burn-in chamber 101 and a pattern generator (PG) 121 for generating a test signal to be input to an integrated circuit on a semiconductor chip are provided.

In a burn-in chamber 101, a plurality of burn-in (BI) boards 102 are connected to a connector 1 respectively.
03 and is held. Here, two B
Although the I board 102 is shown, a plurality of BI boards 102 are spaced apart from each other in the vertical direction.
The board is stored. A large number of resin-sealed semiconductor chips 104 are mounted on each BI board 102 so that an inspection signal can be input.

[0007] Outside the burn-in chamber 101, P
Signal line 122 connected to G121 and BI board 102
A driver board 123 corresponding to the BI board 102 is connected to and held by an outer portion of the connector 103 between the two.

The PG 121 is provided on the driver board 123.
Driver and BI board 10 for driving inspection signal from
A plurality of active elements 124 such as a comparator for comparing an expected value signal for each of the semiconductor chips 104 on 2 and an output signal thereof and outputting a comparison result to the PG 121 are mounted.

On the other hand, there has been proposed a probe card having a novel configuration capable of simultaneously performing burn-in simultaneously in a wafer state, as disclosed in Nikkei Microdevice (July 1997, page 129).

FIG. 6 shows a proposed batch burn-in (hereinafter, referred to as “burn-in”).
Called wafer burn-in. 3) shows a cross-sectional configuration of a probe card for (1). As shown in FIG. 6, a probe card 201 is made of glass or the like, and has a card body 201a having a wiring layer on a main surface (a lower surface in the drawing) and a polyimide thin film held by a rigid ring 202 having a peripheral portion made of ceramic or the like. And a bump-attached film 201b. On the main surface of the bumped film 201b, a plurality of bumps 204 serving as probe terminals provided at positions corresponding to the respective electrodes for testing semiconductor chips on the semiconductor wafer 203 are formed. This bump 20
Reference numeral 4 is electrically connected to the card body 201a via a contact penetrating the bumped film 201b.

In order to perform wafer burn-in using the probe card 201, it is necessary to completely contact each bump 204 of the probe card 201 with each electrode of a semiconductor chip formed on the semiconductor wafer 203.
As a jig for this, a wafer tray 211 made of metal such as aluminum and holding the semiconductor wafer 203 is used.
Is required.

At the peripheral portion of the surface (= main surface) of the wafer tray 211 facing the main surface of the probe card 201,
A seal ring 212 made of silicon rubber or the like for forming a sealed space is provided together with the main surface of the probe card 201 and the main surface of the wafer tray 211, and the side portion is electrically connected to the outside and maintains a reduced pressure state. Vacuum valve 213 is provided.

When the air in the closed space is exhausted from the vacuum valve 213 to reduce the pressure in the closed space, the probe card 2
01 and the back surface of the wafer tray 211 are pressed against each other by the atmospheric pressure, so that each bump 204 formed on the main surface of the bumped film 201b of the probe card 201 and each electrode formed on the semiconductor wafer 203 come close to each other. Then, it is further crimped. As a result, the probe card 201, the semiconductor wafer 203, and the wafer tray 211 are integrated and the probe card 201 is
Is supplied to the burn-in apparatus, wafer burn-in can be performed.

[0014]

First, the burn-in apparatus 100 for a resin-encapsulated semiconductor chip performs a burn-in test on each semiconductor chip 104 by setting the temperature in the burn-in chamber 101 to about 125 ° C. For this reason, it is necessary to store each semiconductor chip 104 in the high-temperature burn-in chamber 101 with the semiconductor chip 104 mounted on the BI board 102.
In order to guarantee the operation of 24, these active elements 124 must be installed outside the burn-in chamber 101. As a result, since the signal line 122 becomes longer, there is a problem that the signal is liable to be deteriorated and is not suitable for a high-speed operation test.

Next, the wafer burn-in type burn-in apparatus performs a batch inspection on a larger number of semiconductor chips as compared with the above-described burn-in apparatus for resin-encapsulated semiconductor chips. However, there is a problem that the load on the circuit inspection device side is significantly increased as compared with the case where the inspection is performed at the same time.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems, prevent deterioration of a test signal, and reduce a test load on a circuit test apparatus.

[0017]

In the probe card 201 for wafer burn-in shown in FIG. 6, a large number of semiconductor chips 104 formed on a semiconductor wafer 203 themselves generate heat during operation. In order to maintain the semiconductor wafer 203 at a predetermined temperature,
3 that only the temperature of the wafer tray 211 that is in close contact with 3 needs to be locally controlled (heated or absorbed).
By doing so, even if a plurality of wafer trays 211 are put into the burn-in apparatus, the temperature on the back surface of the probe card 201 can be controlled to about 70 ° C. or less by appropriately controlling the ambient temperature of the probe card 201. We have obtained both findings.

In addition to the above findings, the conventional BI board 10
The present invention has been obtained as a result of paying attention to the fact that there is a free area (space) which does not exist in 2.

That is, according to the present invention, a probe card for wafer burn-in is controlled or tested on the back surface of the probe card (the surface opposite to the surface facing the semiconductor wafer) for each semiconductor chip. This is a configuration in which an element for performing the control is provided or an element for suppressing a change in the control signal is provided.

More specifically, a burn-in inspection method according to the present invention provides a probe card having a plurality of probe terminals integrally provided on one surface and a semiconductor card having a plurality of semiconductor chips formed on a temperature-controllable wafer tray. A loading step of loading a wafer into a burn-in apparatus while holding the wafer and the plurality of probe terminals and each electrode of the semiconductor chip oppositely and integrally so as to be electrically connected to each other; by applying a voltage assumes burn-in test method and a test step of performing a burn-in test to the bulk electrical characteristics of a plurality of semiconductor chips at the wafer level, the other surface of the probe card, formed on the probe card It is has been to probe terminals electrically through the through-hole connection, the control means semiconductor chip for controlling the input and output of the semiconductor chip Is provided integrally with each, Ken
The inspection step includes a step of applying a voltage to each electrode of the semiconductor chip via each control means for each corresponding semiconductor chip.
No.

In the burn-in inspection method of the present invention,
The control means is a drive circuit element, a test function circuit element, and a frequency.
It is preferable that it consists of any of the multiplying circuit elements.
Good.

In the burn-in inspection method of the present invention,
The control means controls each semiconductor chip on the other side of the probe card.
It is preferable that the
New

In the burn-in inspection method of the present invention,
The control means is a signal compression circuit element, a capacitance element, and a current limiting element.
It preferably comprises any of the children.

A probe card according to the present invention applies a voltage to each electrode of a plurality of semiconductor chips formed on a semiconductor wafer to collectively inspect the electrical characteristics of the plurality of semiconductor chips at a wafer level. The probe card, the card body, a plurality of probe terminals provided at positions corresponding to each electrode of the semiconductor chip on one surface of the card body, and provided on the other surface of the card body and electrically connected to the probe terminals A control means is provided between the connected wiring and the wiring on the other surface of the card body and the probe terminal and controls input / output of the semiconductor chip.

According to the probe card of the present invention, the control means for controlling the input / output of the semiconductor chip between the wiring and the probe terminals on the surface (back surface) of the card body opposite to the surface on which the probe terminals are provided. Is provided, when a drive circuit or a test function circuit is used as the control means, the distance between the drive circuit or the test function circuit and the wiring between the semiconductor chip becomes extremely short.

In the probe card according to the present invention, it is preferable that the wiring is a voltage supply line for supplying a voltage to the probe terminal through a through hole formed in the card body, and the control means is composed of a drive circuit element. In this case, since the drive circuit element is provided between the voltage supply line for supplying a voltage to the probe terminal and the probe terminal, that is, near the semiconductor chip, the drive circuit located near the chip to be inspected is provided. The quality of the control signal output from the element does not deteriorate.

In the probe card of the present invention, it is preferable that the wiring is a voltage supply line for supplying a voltage to the probe terminal through a through hole formed in the card body, and the control means is composed of a test function circuit element. This way,
Since the test function circuit element is provided between the voltage supply line supplying the voltage to the probe terminal and the probe terminal, that is, in the vicinity of the semiconductor chip, the output from the test function circuit element located in the vicinity of the chip to be tested is provided. The quality of the test signal and control signal to be used does not deteriorate.

In the probe card of the present invention, it is preferable that the wiring is a voltage supply line for supplying a voltage to the probe terminal through a through hole formed in the card main body, and the control means is composed of a frequency multiplying circuit element. With this configuration, the frequency multiplying circuit element is provided between the voltage supply line for supplying a voltage to the probe terminal and the probe terminal, that is, in the vicinity of the semiconductor chip. Since a high frequency signal having a frequency higher than the frequency of the signal can be generated and the frequency multiplying circuit element is provided near the probe terminal,
The quality of the high-frequency signal generated by the frequency multiplying circuit element does not deteriorate.

In the probe card according to the present invention, it is preferable that the wiring is a data output line for receiving an output from the probe terminal through a through hole formed in the card body, and the control means be composed of a signal compression circuit element. In this case, since the signal compression circuit element is provided between the data output line from which the output signal to the probe terminal is output and the probe terminal, when the output signal is output as many bits, The number of bits of the output signal can be reduced.

In the probe card of the present invention, it is preferable that the control means comprises a capacitance element provided in parallel with the wiring. With this configuration, even if a transient voltage fluctuation occurs in the power supply voltage applied to the wiring, the transient voltage fluctuation can be reliably suppressed near the probe terminal.

In the probe card of the present invention, it is preferable that the wiring is a voltage supply line for supplying a voltage to the probe terminal through a through hole formed in the card body, and the control means be formed of a current limiting element. With this configuration, the current limiting element is provided between the voltage supply line that supplies a voltage to the probe terminal and the probe terminal, that is, in the vicinity of the semiconductor chip. If a large amount of current flows beforehand due to a failure or a failure during the batch inspection, a large amount of current also flows to the current limiting element corresponding to the defective semiconductor chip, and the current limiting element And its resistance value rises significantly.

[0032]

(First Embodiment) FIGS. 1A and 1B show a probe card according to a first embodiment of the present invention and a method of inspecting a semiconductor integrated circuit using the probe card. This will be described with reference to FIG.

FIG. 1A shows a plan configuration of a surface (back surface) opposite to a surface (front surface) of the probe card facing the semiconductor wafer, and FIG. 1B shows a cross-sectional configuration of the probe card. . As shown in FIG. 1B, a plurality of semiconductor chips 11 are formed on a semiconductor wafer 10, and an inspection electrode 12 is formed on each semiconductor chip 11. Although a plurality of test electrodes 12 are usually formed on each semiconductor chip 11, for convenience of illustration, FIG.
FIG. 3B shows a case where one inspection electrode 12 is formed on each semiconductor chip 11. 1A indicates a region where the semiconductor chip 11 is formed.

The card body 20 constituting the probe card shown in FIGS. 1A and 1B has a multilayer wiring in which an insulating layer made of a ceramic thin film and a wiring layer made of a conductor film such as copper are alternately laminated. It has a structure.

As shown in FIGS. 1A and 1B, a probe terminal 21 is formed on the surface of the card body 20 so as to correspond to each test electrode 12 of the semiconductor chip 11.
A driver circuit element 31 as a drive circuit element is provided at a portion corresponding to the probe terminal 21 on the back surface of the card body 20. The card body 20
The contact 23 penetrating the card body 20 in the front and back direction is formed at the portion where the probe terminal 21 is formed, and the front side of the contact 23 is connected to the probe terminal 21 and the back side of the contact 23 is a driver circuit. It is connected to the element 31.

As shown in FIG. 1A, the card body 20
An external electrode 24 to which a voltage is applied from an external device is formed on the periphery of the back surface of the card body 20. A common voltage supply connecting the external electrode 24 and each driver circuit element 31 is formed on the back surface of the card body 20. The line 25 branches and extends. Thus, when a voltage is applied to the external electrode 24, the applied voltage is applied to each probe terminal 21 via the common voltage supply line 25, the driver circuit element 31, and the contact 23. The common voltage supply line 25 may be a power supply voltage supply line for applying a power supply voltage or a ground voltage supply line for applying a ground voltage.

As described above, according to the present embodiment, since the driver circuit element 31 for driving the semiconductor chip 11 is disposed near the semiconductor chip 11 for each semiconductor chip 11, the driver circuit element 31 Since it is possible to prevent deterioration of the control signal and the like, a high-speed operation test of the semiconductor chip 11 can be performed without any trouble. In addition, the back surface of the card body 20, which has a sufficient space for inspecting the semiconductor wafer 20 collectively, can be effectively used.

Although the driver circuit element 31 is provided for each semiconductor chip 11 in the present embodiment, it is divided into blocks which can be optimized in consideration of the number of semiconductor chips 11 formed on a semiconductor wafer. The driver circuit element 31 may be provided for each block.

In place of the driver circuit element 31 for driving the semiconductor chip 11, for example, BIST (Biult in)
A test function circuit having a test function of the semiconductor chip 11 such as a self test circuit or a pattern generator may be mounted. In this manner, similarly to the driver circuit element 31, it is possible to prevent deterioration of the signal quality and distribute the load of the circuit inspection device.

In place of the driver circuit element 31 for driving the semiconductor chip 11, a PL as a frequency multiplication circuit is used.
An L (Phase Locked Loop) circuit element may be mounted. P
The LL circuit element generates a higher internal clock frequency based on the external clock frequency output from the circuit inspection device. For example, an external clock frequency of 12.5 MHz is received, an internal clock frequency of 100 MHz is generated, and supplied to each semiconductor chip 11. This makes it possible to easily improve the function of the circuit inspection apparatus, prevent signal quality deterioration, and distribute the load of the circuit inspection apparatus.

Second Embodiment A probe card according to a second embodiment of the present invention and a method for inspecting a semiconductor integrated circuit using the probe card will be described below with reference to FIG.

In the present embodiment, an active element as a control means mounted on the back surface of the card body 20 is provided on the output side, so that the load of the circuit inspection apparatus and the inspection can be simplified.

FIG. 2 shows a plan view of the rear surface of the probe card. In FIG. 2, the same components as those shown in FIG. 1A are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 2, probe terminals (not shown) are formed on the surface of the card body 20 so as to correspond to the respective output pads of the semiconductor chip 11.
Signal compression circuit elements 32 are respectively provided at portions corresponding to the probe terminals on the back surface of 0. Also,
A contact (not shown) that penetrates the card body 20 in a front-to-back direction is formed at a portion of the card body 20 where the probe terminal is formed, and the front side of the contact is connected to the probe terminal, and the back side of the contact. Is connected to the signal compression circuit element 32.

As shown in FIG. 2, an external data output terminal 24A for outputting an inspection result to an external device is formed at a peripheral portion of the back surface of the card body 20. On the back surface of the card body 20, data output lines 25A connecting the external data output terminals 24A and the respective signal compression circuit elements 32 extend in row units of the semiconductor chips 11 formed in a matrix. Accordingly, if 32-bit data is output from each semiconductor chip 11 to each signal compression circuit element 32 via a probe terminal and a contact, for example,
Each signal compression circuit element 32 outputs a calculation result to the data output line 25A, for example, by calculating a logical sum of all the bits of the 32-bit data.

As described above, according to the present embodiment, the signal compression circuit element 32 for compressing the multi-bit data of the semiconductor chip 11 is provided for each semiconductor chip 11.
1, the load on the circuit inspection apparatus on the side receiving the output result is reduced, and the back surface of the card body 20 has sufficient space for inspecting the semiconductor wafer 20 collectively. Can be effectively utilized.

Third Embodiment Hereinafter, a probe card according to a third embodiment of the present invention and a method for inspecting a semiconductor integrated circuit using the probe card will be described with reference to FIGS. 3 (a) and 3 (b). I will explain while.

In the present embodiment, the control means mounted on the back surface of the card body 20 is configured to use a passive element instead of the above-described active element, thereby suppressing the fluctuation of the control signal.

FIG. 3A shows a plan configuration of the back surface of the probe card, and FIG. 3B shows a cross-sectional configuration of the probe card. Here, in FIGS. 3A and 3B,
The same components as those shown in FIGS. 1A and 1B are denoted by the same reference numerals, and description thereof will be omitted. FIG.
As shown in (a) and (b), probe terminals 21 are formed on the surface of the card body 20 so as to correspond to the test electrodes 12 of the semiconductor chip 11. An external power supply electrode 24B to which a power supply voltage is applied from an external device is formed at one end of a peripheral portion on the back surface of the card body 20, and the external power supply electrode 24B and each probe terminal 21 are formed on the back surface of the card body 20. Power supply line 25B
Extends fork.

An external ground electrode 24C to which a ground voltage is applied from an external device is formed at the other end of the peripheral portion on the back surface of the card body 20, and an external ground electrode 24C is formed on the back surface of the card body 20. And a common ground voltage supply line 25C that connects to a probe terminal (not shown).

Probe terminal 21 in card body 20
The contact 23 is formed in a portion where the card body 20 is formed, penetrating the card body 20 in the front and back direction, and electrically connected to the power supply voltage supply line 25B.
In the vicinity of a portion corresponding to the probe terminal 21 on the back surface of the device, chip capacitors 33 as capacitance elements connected in parallel to the power supply voltage supply line 25B and the ground voltage supply line 25C are provided.

Thus, when a voltage is applied to the external power supply electrode 24B and the external ground electrode 24C, the applied voltage is applied to each probe terminal 21 via the common power supply voltage supply line 25B and the contact 23. At this time, even if a transient voltage fluctuation occurs between the external power supply electrode 24B and the external ground electrode 24C, the power supply voltage supply line 25B and the ground voltage supply line 25C near the probe terminal 21.
Since the chip capacitor 33 connected in parallel between the two terminals absorbs the voltage fluctuation, the voltage applied to the probe terminal 21 can be reliably stabilized.

As described above, according to the present embodiment, the power supply voltage can be stabilized for each of the semiconductor chips 11 and the back surface of the card body 20 which has a sufficient space for inspecting the semiconductor wafer 20 collectively can be effectively used. It can be used for

In this embodiment, the chip capacitor 33 is provided for each semiconductor chip 11, but the chip capacitor 33 may be provided for each block as long as the power supply voltage can be stabilized.

(Fourth Embodiment) Hereinafter, a probe card according to a fourth embodiment of the present invention and a method of inspecting a semiconductor integrated circuit using the probe card will be described with reference to FIGS. 4 (a) and 4 (b). I will explain while.

This embodiment also has a configuration in which a passive element is used for the control means.

FIG. 4A shows a plan configuration of the back surface of the probe card, and FIG. 4B shows a cross-sectional configuration of the probe card. Here, in FIGS. 4A and 4B,
The same components as those shown in FIGS. 1A and 1B are denoted by the same reference numerals, and description thereof will be omitted.

Probe terminals 21 are formed on the front surface of the card body 20 so as to correspond to the respective test electrodes 12 of the semiconductor chip 11. PTC (Positive Temperature Coefficient) element 34 as limiting element
Are arranged respectively. A contact 23 penetrating the card body 20 in a front-to-back direction is formed at a portion of the card body 20 where the probe terminal 21 is formed.
And the back side of the contact 23 is a PTC element 34
Is connected to

An external electrode 24 to which a voltage is applied from an external device is formed on the periphery of the back surface of the card body 20, and the external electrode 24 and each PTC element 34 are formed on the back surface of the card body 20. A common voltage supply line 25 to be connected is branched and extends. Thus, when a voltage is applied to the external electrode 24, the applied voltage is applied to the common voltage supply line 2
5, is applied to each probe terminal 21 via the PTC element 34 and the contact 23. Note that the common voltage supply line 2
5 may be a power supply voltage supply line for applying a power supply voltage, or may be a ground voltage supply line for applying a ground voltage.

As the PTC element 34, a polymer PT
A C-type element or a ceramic PTC element made of barium titanate (BaTiO ₃ ) or the like can be used.

The polymer-based PTC element is a resistance element in which conductive carbon and an insulating polymer such as polyolefin or fluororesin are blended. In a normal state, a large amount of carbon dispersed in the polymer is used. Has a low specific resistance value.
However, when the temperature is gradually increased from the normal state, the thermal expansion coefficient of the polymer is higher than the thermal expansion coefficient of carbon, so that the conductive path of carbon is gradually cut off, and a gradual PTC characteristic is exhibited. Then, after a predetermined temperature (a desired temperature can be selected by selecting a compounding ratio of conductive carbon and insulating polymer or a type of insulating polymer), the PTC effect rapidly increases. Appear. That is, since the volume change of several tens of percent due to the melting of the polymer cuts the conductive paths of carbon one after another, the resistance value increases by several digits, for example, about 5 digits.

In the ceramic PTC element, a predetermined temperature at which the PTC effect appears can be selected by adjusting the amount of impurities added. For example, in a ceramic PTC element made of barium titanate, Pb is used as an impurity.
When Pb is added, the predetermined temperature at which the PTC effect appears can be shifted to a higher temperature side, and the predetermined temperature shifts to a higher temperature side as the amount of Pb added increases.

Generally, a phenomenon in which a large amount of current flows through the PTC element or the temperature of the PTC element rises so that the resistance value of the PTC element becomes significantly higher than in a steady state is called a trip. In the steady state, the resistance value of the PTC element is very low and stable with respect to the load, but when the amount of flowing current exceeds a reference (trip current) determined by the characteristics of the PTC element, self-heating causes the PTC element to lose its resistance. The resistance is increased, and the current flowing through the PTC element is slightly limited. Once the PTC element has tripped, the PTC
The element stabilizes when the resistance value is high, so PTC
The device keeps the trip state. Then, when the power is turned off and the temperature of the PTC element returns to its original state, or when the voltage of the circuit becomes sufficiently low (the amount of heat generated by the PTC element becomes smaller than the amount of heat radiation), the PTC element is automatically turned off. Return to steady state.

Hereinafter, a method of inspecting a semiconductor device using the probe card according to the fourth embodiment will be described.

First, with the test electrodes 12 of the plurality of semiconductor chips 11 formed on the semiconductor wafer 10 connected to the probe terminals 21 of the probe card, a power supply voltage or an external electrode 24 of the probe card is applied to the external electrodes 24 of the probe card. Apply the ground voltage. In this case, the power supply voltage is applied to the external electrodes 24 when the substrate of the semiconductor chip 11 is connected to the ground voltage, and the ground voltage is applied to the external electrodes 24 when the substrate of the semiconductor chip 11 is connected to the power supply voltage. External electrode 2
The voltage applied to 4 is applied to each inspection electrode 12 via a common voltage supply line 25, PTC element 34, contact 23 and probe terminal 21.

Next, the semiconductor wafer 10 and the probe card are held at a predetermined temperature for burn-in while a voltage is applied to each inspection electrode 12. If any of the plurality of semiconductor chips 11 has a defect or a defect occurs in a burn-in process and an abnormally large amount of current flows through the defective semiconductor chip 11, the defective semiconductor chip 11 Element 34 connected to
Since a large amount of current also flows through the PT
Since the resistance of the C element 34 rises significantly due to the high temperature, no voltage is applied to the defective semiconductor chip 11.

As a result, the temperature of the defective semiconductor chip 11 is prevented from rising, so that another semiconductor chip 11 adjacent to the defective semiconductor chip 11 becomes abnormally hot and burn-in cannot be performed normally. At the same time, the power supply voltage line and the ground voltage line are short-circuited via the defective semiconductor chip 11, so that the voltage is not applied to the good semiconductor chip 11.

In the fourth embodiment, the plurality of probe terminals 21 are provided on the front surface of the card body 20 and the common voltage supply line 25 is provided on the back surface of the card body 21. Since there is enough space, the PTC element 34 can be provided on the back surface of the card body 20 for each semiconductor chip 11.

In each of the embodiments of the present invention, a rigid substrate in which insulating layers made of ceramic and wiring layers made of conductive films are alternately laminated is used for the card body 20 constituting the probe card. However, the present invention is not limited to this, and a glass substrate having a multilayer wiring in which an insulating layer made of polyimide or the like and a wiring layer made of a conductive film are alternately laminated on the main surface may be used.

The method of inspecting a semiconductor device using the probe card according to each embodiment of the present invention is not limited to the burn-in at the wafer level, but may be an inspection of ordinary electrical characteristics.

[0070]

According to the burn-in inspection method according to the present invention, the semiconductor chip is electrically connected to the probe terminals through the through holes formed in the probe card on the back surface of the probe card facing the semiconductor wafer. Control means for controlling the input and output of each semiconductor chip
When a drive circuit or a test function circuit is used for the control means, the distance between the drive circuit or the test function circuit and the wiring between the semiconductor chip becomes extremely short.
Signal degradation can be prevented. As a result, a high-speed operation test of the semiconductor chip can be performed, and the load on the circuit inspection apparatus can be distributed by effectively using the back surface of the probe card having a sufficient space.

[Brief description of the drawings]

FIGS. 1A and 1B show a probe card according to a first embodiment of the present invention, wherein FIG. 1A is a plan view and FIG.

FIG. 2 is a configuration sectional view showing a probe card according to a second embodiment of the present invention.

FIGS. 3A and 3B show a probe card according to a third embodiment of the present invention, wherein FIG. 3A is a plan view and FIG.

FIGS. 4A and 4B show a probe card according to a fourth embodiment of the present invention, wherein FIG. 4A is a plan view and FIG.

FIG. 5 is a schematic perspective view showing a conventional burn-in device for a resin-encapsulated semiconductor chip.

FIG. 6 is a configuration sectional view showing a conventional probe card for wafer burn-in.

[Explanation of symbols]

 Reference Signs List 10 semiconductor wafer 11 semiconductor chip 12 inspection electrode 20 card body 21 probe terminal 23 contact 24 external electrode 24A external data output terminal 24B external power supply electrode 24C external ground electrode 25 voltage supply line 25A data output line 25B power supply voltage supply line 25C ground voltage Supply line 31 Driver circuit element (drive circuit element) 32 Signal compression circuit element 33 Chip capacitor (capacitance element) 34 PTC element (current limiting element)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-9-252031 (JP, A) JP-A-7-153298 (JP, A) JP-A-7-111280 (JP, A) JP-A 8- 340030 (JP, A) Japanese Utility Model 63-146770 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/66

Claims (4)

(57) [Claims] 1. A probe card having a plurality of probe terminals integrally provided on one surface and a semiconductor wafer held on a temperature-controllable wafer tray and having a plurality of semiconductor chips formed thereon, the plurality of probe terminals and the plurality of probe terminals An input step for inputting to a burn-in device in a state where each electrode of the semiconductor chip is opposed and integrally held so as to be electrically connected to each other.
A test step of applying a voltage to the electrodes of the semiconductor chip through the probe terminals to perform a burn-in test collectively at a wafer level on electrical characteristics of the plurality of semiconductor chips.
In a burn-in test method wherein the other surface of the probe card is connected the probe terminal and electrically through the through hole formed in the probe card, control means for controlling the input and output of the semiconductor chip
Are provided integrally for each semiconductor chip, and the inspection step includes, for each corresponding semiconductor chip, a step of applying a voltage to each electrode of the semiconductor chip via each of the control means. Burn-in inspection method. 2. The burn-in inspection method according to claim 1, wherein said control means comprises one of a drive circuit element, a test function circuit element and a frequency multiplication circuit element. 3. The burn-in inspection method according to claim 1, wherein the control unit is provided at a position corresponding to each of the semiconductor chips on the other surface of the probe card. 4. The burn-in inspection method according to claim 1, wherein said control means comprises one of a signal compression circuit element, a capacitance element, and a current limiting element.