JP3135813B2 - Image forming apparatus and method of manufacturing the same - Google Patents
Image forming apparatus and method of manufacturing the sameInfo
- Publication number
- JP3135813B2 JP3135813B2 JP4892695A JP4892695A JP3135813B2 JP 3135813 B2 JP3135813 B2 JP 3135813B2 JP 4892695 A JP4892695 A JP 4892695A JP 4892695 A JP4892695 A JP 4892695A JP 3135813 B2 JP3135813 B2 JP 3135813B2
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- Japan
- Prior art keywords
- electron
- source substrate
- electron source
- insulating film
- row
- Prior art date
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- Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
- Cold Cathode And The Manufacture (AREA)
- Electrodes For Cathode-Ray Tubes (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は画像形成装置、特に表面
伝導型電子放出素子を用いた画像形成装置及びその製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus using a surface conduction electron-emitting device and a method of manufacturing the same.
【0002】[0002]
【従来の技術】従来、平面型画像形成装置としては、単
純マトリックス液晶表示装置(LCD)、薄膜トランジ
スタ液晶表示装置(TFT/LCD)、プラズマディス
プレイ(PDP)、低速電子線蛍光表示管(VFD)等
がある。2. Description of the Related Art Conventionally, as a flat type image forming apparatus, a simple matrix liquid crystal display (LCD), a thin film transistor liquid crystal display (TFT / LCD), a plasma display (PDP), a low-speed electron beam fluorescent display (VFD) and the like have been known. There is.
【0003】これらの画像形成装置における発光方法の
一つとして、電子放出素子を用いて蛍光体を発光させる
方法がある。この電子放出素子としては表面伝導型電子
放出素子が一般的に知られている(M.I.Elins
on,Radio Eng.Electron Phy
s.,10,(1965))。この電子放出素子は、基
板上に形成された小面積の薄膜に、膜面に対して平行方
向に電流を流すと電子が放出する現象を利用するもので
ある。As one of the light emitting methods in these image forming apparatuses, there is a method of causing a phosphor to emit light using an electron-emitting device. As this electron-emitting device, a surface conduction electron-emitting device is generally known (MI Elins).
on, Radio Eng. Electron Phys
s. , 10, (1965)). This electron-emitting device utilizes the phenomenon that electrons are emitted when a current is applied to a small-area thin film formed on a substrate in a direction parallel to the film surface.
【0004】表面伝導型電子放出素子の薄膜としては、
SnO2薄膜(M.I.Elinson,Radio
Eng.Electron Phys.,10,(19
65))、Au薄膜(G.Dittmer,Thin
Solid Films,9,317(1972)),
In2O3/SnO2薄膜(M.Hartwell an
d C.G.Fonstad,IEEE Trans.
ED Conf.,519(1975))、カーボン薄
膜(荒木 久ほか,真空,26,1,22(198
3))等が報告されている。As a thin film of a surface conduction electron-emitting device,
SnO 2 thin film (MI Elinson, Radio)
Eng. Electron Phys. , 10, (19
65)), Au thin film (G. Dittmer, Thin
Solid Films, 9, 317 (1972)),
In 2 O 3 / SnO 2 thin film (M. Hartwell an
d C.I. G. FIG. Fonstad, IEEE Trans.
ED Conf. , 519 (1975)), carbon thin film (Hisashi Araki et al., Vacuum, 26, 1, 22 (198)
3)) etc. have been reported.
【0005】表面伝導型電子放出素子の典型的な例を図
5に示す。この電子放出素子の構成は上記のM.Har
twellによるもので、1は絶縁性の基板、12は電
子放出部形成用薄膜、3は電子放出部である。電子放出
部形成用薄膜(12)の形成は、基板(1)上にH型形
状の金属酸化物の薄膜をスパッタで形成することによっ
て行われる。次いで、フォーミングと呼ばれる通電処理
によって電子放出部(3)が形成される。フォーミング
とは、電子放出部形成用薄膜(12)の両端に電圧を印
加通電し、この電子放出部形成用薄膜(12)を局所的
に破壊・変形・変質させ、電気的に高抵抗な電子放出部
(3)を形成することである。また電子の放出は、電子
放出部形成用薄膜(12)の亀裂付近から行われる場合
もある。FIG. 5 shows a typical example of a surface conduction electron-emitting device. The structure of this electron-emitting device is the same as that of the above-mentioned M.E. Har
According to twell, 1 is an insulating substrate, 12 is a thin film for forming an electron emitting portion, and 3 is an electron emitting portion. The formation of the electron-emitting-portion-forming thin film (12) is performed by forming an H-shaped metal oxide thin film on the substrate (1) by sputtering. Next, an electron emission portion (3) is formed by an energization process called forming. Forming is a process in which a voltage is applied to both ends of the thin film for forming an electron emission portion (12), and the thin film (12) for forming an electron emission portion is locally broken, deformed, or altered, and an electron having a high electrical resistance is formed. Forming the discharge part (3). In some cases, electrons are emitted from the vicinity of a crack in the thin film (12) for forming an electron emission portion.
【0006】一方、本出願人は、微粒子が分散配置され
た電子放出材からなる電子放出部形成用薄膜(12)
を、一対の素子電極間に配置することによって、新規な
表面伝導型電子放出素子を開発し、これを技術開示した
(USP5,066,883)。この電子放出素子は、
上記従来のものより電子放出位置を精密に制御できるた
め、より高い精度で電子放出素子を配列することができ
る。この電子放出素子の典型的な例を図6に示す。図6
において、1は絶縁性の基板、2は電気的接続のための
素子電極、12は微粒子が分散配置された電子放出材か
らなる電子放出部形成用薄膜、3は電子放出部である。On the other hand, the present applicant has proposed a thin film (12) for forming an electron emitting portion, comprising an electron emitting material in which fine particles are dispersed and arranged.
Was developed between a pair of device electrodes to develop a new surface conduction electron-emitting device, and disclosed the technology (US Pat. No. 5,066,883). This electron-emitting device
Since the electron emission position can be controlled more precisely than the above-mentioned conventional one, the electron emission elements can be arranged with higher accuracy. FIG. 6 shows a typical example of this electron-emitting device. FIG.
In the figure, 1 is an insulating substrate, 2 is an element electrode for electrical connection, 12 is a thin film for forming an electron emitting portion made of an electron emitting material in which fine particles are dispersed and arranged, and 3 is an electron emitting portion.
【0007】上記の表面伝導型電子放出素子は、基板上
に多数形成され電子源基板が作製される。この電子源基
板は蛍光体を有するプレートと組み合わされ、次いで真
空外囲器内に設置され画像形成装置を形成する。真空外
囲器内では、電子源基板から電子が放出し、その電子が
プレートの蛍光体へ照射される。[0007] A large number of the above surface conduction electron-emitting devices are formed on a substrate to produce an electron source substrate. This electron source substrate is combined with a plate having a phosphor and then placed in a vacuum envelope to form an image forming apparatus. In the vacuum envelope, electrons are emitted from the electron source substrate, and the electrons are irradiated on the phosphor of the plate.
【0008】本出願人は、上記の表面伝導型電子放出素
子を用いて、電子源基板の作製を検討している。この電
子源基板の1例を図7に示す。この図7は、行列方向に
多数形成された電子放出素子のうち、行方向に2個、列
方向に2個(行列合計3個)の電子放出素子を含む電子
源基板の一部を表わすものである。The present applicant is studying the fabrication of an electron source substrate using the above-mentioned surface conduction electron-emitting device. FIG. 7 shows an example of the electron source substrate. FIG. 7 shows a part of an electron source substrate including two electron emitting elements in a row direction and two electron emitting elements in a column direction (a total of three electron emitting elements) among a large number of electron emitting elements formed in a matrix direction. It is.
【0009】このような電子源基板の作製方法として
は、フォトリソグラフ法や印刷法等がある。フォトリソ
グラフ法はパターニング精度が良好である。しかし、4
0インチ以上の大面積の画像表示装置を作製する場合
は、大型の成膜装置や露光装置が必要になり、さらに用
いるプロセス材料も大量に必要となりコストが高くな
る。そのため、大面積の画像形成装置を作製する場合
は、印刷法で行うことがコスト的に望ましい。As a method of manufacturing such an electron source substrate, there are a photolithography method, a printing method, and the like. The photolithographic method has good patterning accuracy. But 4
In the case of manufacturing an image display device having a large area of 0 inch or more, a large-sized film forming device and an exposure device are required, and a large amount of process materials are required, resulting in high cost. Therefore, when manufacturing a large-area image forming apparatus, it is desirable to perform the printing by a printing method in terms of cost.
【0010】[0010]
【発明が解決しようとする課題】しかし印刷法では、電
子放出素子を基板上に形成して電子源基板を作製する
際、パターン寸法精度および位置合わせ精度が低いとい
う問題がある。特に図7および図8において、素子電極
(2)と絶縁膜(6)とのパターン寸法精度および位置
合わせ精度に問題が発生する。すなわち、図8(a)に
示すように、2つの絶縁膜(6)は、その中央に素子電
極(2)を位置するように形成されるべきでものである
が(このときP1=Q)、図8(b)に示すように2つ
の絶縁膜(6)が位置ズレを起こす。その結果、絶縁膜
に覆われていない一対の素子電極の列方向の長さが短く
なり、その素子電極間に形成される電子放出部の列方向
の長さが短くなる(P1>P2=P1−R1)。これが原因
で輝度が低下したり輝度ムラが発生する。なお図8にお
いて、Qは素子電極(2)の列方向の長さ、P1及びP2
は絶縁膜に覆われていない素子電極の列方向の長さ、R
1は絶縁膜(6)の位置ズレによって覆われた素子電極
の列方向の長さを示す。However, the printing method has a problem that the pattern dimensional accuracy and the alignment accuracy are low when an electron emitting element is formed on a substrate to manufacture an electron source substrate. In particular, in FIGS. 7 and 8, problems occur in the pattern dimensional accuracy and the alignment accuracy between the element electrode (2) and the insulating film (6). That is, as shown in FIG. 8A, the two insulating films (6) should be formed so that the element electrode (2) is located at the center thereof (P 1 = Q). As shown in FIG. 8B, the two insulating films (6) are displaced. As a result, the length in the column direction of the pair of device electrodes not covered with the insulating film is reduced, and the length in the column direction of the electron emission portion formed between the device electrodes is reduced (P 1 > P 2). = P 1 -R 1). As a result, the luminance is reduced or the luminance unevenness occurs. In FIG. 8, Q is the length of the element electrode (2) in the column direction, and P 1 and P 2
Is the length in the column direction of the device electrode not covered with the insulating film, R
Reference numeral 1 denotes the length in the column direction of the device electrode covered by the displacement of the insulating film (6).
【0011】そこで本発明の目的は、電子源基板の絶縁
膜形成時に位置ズレが生じても一対の素子電極間の電子
放出部の長さが一定になるようにし、画像の輝度が低下
せず且つ輝度ムラが少ない画像形成装置を提供すること
である。さらに印刷法によって電子源基板を作製し、大
画面の画像形成装置を低コストで提供することである。Accordingly, an object of the present invention is to make the length of the electron-emitting portion between the pair of element electrodes constant even when a positional shift occurs during the formation of the insulating film on the electron source substrate, so that the brightness of the image does not decrease. An object of the present invention is to provide an image forming apparatus with less luminance unevenness. Another object of the present invention is to provide a large-screen image forming apparatus at low cost by manufacturing an electron source substrate by a printing method.
【0012】[0012]
【課題を解決するための手段】本発明は、複数個の表面
伝導型電子放出素子が、基板上に形成された複数の行方
向配線と、該複数の行方向配線と電気的に絶縁され略垂
直方向に複数形成された列方向配線との間に配され、該
表面伝導型放出素子の一対の素子電極の一方が該行方向
配線と電気的に接続され、残る一方の素子電極が該列方
向配線と電気的に接続されてなる電子源基板において、
前記絶縁のために行方向配線の下に帯状に形成された絶
縁膜が、前記一対の素子電極の列方向の両端部を覆うよ
うに形成されていることを特徴とする電子源基板に関す
る。また本発明は、上記電子源基板と、該電子源基板に
対向して蛍光体層が設けられたフェースプレートを備え
た画像形成装置に関する。さらに本発明は、上記電子源
基板を備えた画像形成装置の製造方法であって、該電子
源基板上の配線および絶縁膜を印刷法によって形成する
ことを特徴とする画像形成装置の製造方法に関する。SUMMARY OF THE INVENTION According to the present invention, a plurality of surface conduction electron-emitting devices are provided with a plurality of row wirings formed on a substrate and substantially insulated from the plurality of row wirings. One of a pair of device electrodes of the surface conduction electron-emitting device is electrically connected to the row-direction wire, and the other device electrode is connected to the column-direction wire formed in the vertical direction. In the electron source substrate electrically connected to the direction wiring,
The present invention relates to an electron source substrate, wherein an insulating film formed in a band shape under the row wiring for insulation is formed so as to cover both ends of the pair of element electrodes in the column direction. Further, the present invention relates to an image forming apparatus including the above-mentioned electron source substrate and a face plate provided with a phosphor layer facing the electron source substrate. Further, the present invention relates to a method of manufacturing an image forming apparatus provided with the above-mentioned electron source substrate, wherein the wiring and the insulating film on the electron source substrate are formed by a printing method. .
【0013】以下本発明を詳細に説明する。Hereinafter, the present invention will be described in detail.
【0014】図1に本発明の電子源基板の平面図を示す
(同図において、X軸方向を行方向、Y軸方向を列方向
とする)。この図1は、絶縁性の基板(1)上で行列方
向に多数形成された電子放出素子のうち、行方向に2
個、列方向に2個(行列合計3個)の素子電極を含む電
子源基板の一部を表わしたものである。また図2に、図
1のA−A線断面図を示す。FIG. 1 shows a plan view of the electron source substrate of the present invention (in the figure, the X-axis direction is a row direction and the Y-axis direction is a column direction). FIG. 1 shows that two or more electron-emitting devices formed in rows and columns on an insulating substrate (1) are arranged in a row direction.
2 shows a part of an electron source substrate including two element electrodes in a column direction (three in total in a matrix). FIG. 2 is a sectional view taken along line AA of FIG.
【0015】本発明はこのような電子源基板上におい
て、絶縁膜が、一対の素子電極の列方向の両端部を覆う
ように形成されていることを特徴とする。すなわち図2
(a)において、素子電極(2)の長さ(Q)が、絶縁
膜に覆われていない素子電極の列方向の長さ、すなわち
一対の絶縁膜(6)間の距離(P1)より長いことが特
徴である。印刷法でのパターンの位置ズレは多くとも±
30μm程度であるので、60μm以上長いことが望ま
しい。素子電極の長さをこのように設定することによっ
て、図2(b)に示すように、絶縁膜形成時の位置ズレ
(R2)が生じても絶縁膜に覆われていない素子電極の
列方向の長さ(P2)は一定である(P2=P1)。した
がって、絶縁膜に覆われていない一対の素子電極間の全
体に電子放出部形成用薄膜(12)を形成すると(図1
参照)、この薄膜(12)に形成される電子放出部
(3)の長さも絶縁膜の位置ズレにかかわらず一定にな
るため、輝度の低下が抑えられ、輝度ムラも減少する。The present invention is characterized in that an insulating film is formed on such an electron source substrate so as to cover both ends of a pair of device electrodes in the column direction. That is, FIG.
In (a), the length (Q) of the device electrode (2) is determined by the length in the column direction of the device electrode not covered with the insulating film, that is, the distance (P 1 ) between the pair of insulating films (6). The feature is that it is long. Pattern misalignment in printing method is at most ±
Since it is about 30 μm, it is preferable that the length is 60 μm or more. By setting the length of the device electrode in this manner, as shown in FIG. 2B, even if a displacement (R 2 ) occurs during the formation of the insulating film, the column of the device electrode not covered with the insulating film The length (P 2 ) in the direction is constant (P 2 = P 1 ). Therefore, when the electron-emitting-portion-forming thin film (12) is formed entirely between the pair of device electrodes not covered with the insulating film (FIG. 1).
Reference), the length of the electron-emitting portion (3) formed on the thin film (12) is also constant irrespective of the displacement of the insulating film, so that a decrease in luminance is suppressed and luminance unevenness is reduced.
【0016】なお、素子電極の上記の長さの上限は、画
素ピッチ(図4参照)の長さ未満であり、実際には、印
刷の分解能によるため画素ピッチより50μm程度短く
なる。The upper limit of the above-mentioned length of the element electrode is smaller than the length of the pixel pitch (see FIG. 4), and is actually about 50 μm shorter than the pixel pitch due to the printing resolution.
【0017】図1において、一対の素子電極(2)の電
極間隔は数μm〜数百μmが適当であり、素子電極
(2)の厚さは数百〜数千オングストロームが適当であ
る。素子電極の行方向および列方向の長さは、それぞれ
ともに数百〜1000μmが適当である。In FIG. 1, the distance between the pair of device electrodes (2) is suitably several μm to several hundred μm, and the thickness of the device electrode (2) is suitably several hundreds to several thousand angstroms. The appropriate length of each of the device electrodes in the row direction and the column direction is several hundred to 1000 μm.
【0018】この一対の素子電極間に形成される電子放
出部形成用薄膜(12)の厚さは、数十〜数千オングス
トロームが適当である。The thickness of the electron-emitting-portion-forming thin film (12) formed between the pair of device electrodes is suitably several tens to several thousand angstroms.
【0019】接続電極(4)および列方向配線(5)は
それぞれ素子電極(2)と接続している。これら接続電
極および列方向配線の厚さは数μm〜数十μmが適当で
ある。接続電極の行方向の長さは数十〜数百μmが適当
であり、接続電極の列方向の長さは数百μmが適当であ
る。列方向配線の行方向の長さは100〜300μmが
適当であり、列方向配線の列方向の長さは設計に基ず
き、基板の列方向の長さに従って形成される。The connection electrode (4) and the column wiring (5) are connected to the device electrode (2), respectively. The thickness of these connection electrodes and column direction wirings is suitably several μm to several tens μm. The length of the connection electrode in the row direction is suitably several tens to several hundreds μm, and the length of the connection electrode in the column direction is suitably several hundred μm. The appropriate length of the column wiring in the row direction is 100 to 300 μm. The length of the column wiring in the column direction is based on the design and is formed according to the length of the substrate in the column direction.
【0020】絶縁膜(6)は帯状に形成され、列方向配
線(5)と交差するように設置される。この絶縁膜の厚
さは30〜50μmが適当である。絶縁膜の行方向の長
さは設計に基ずき、基板の行方向の長さに従って形成さ
れ、絶縁膜の列方向の長さは200〜600μmが適当
である。The insulating film (6) is formed in a strip shape and is installed so as to intersect with the column wiring (5). An appropriate thickness of the insulating film is 30 to 50 μm. The length of the insulating film in the row direction is based on the design and is formed according to the length of the substrate in the row direction. The length of the insulating film in the column direction is suitably 200 to 600 μm.
【0021】この帯状の絶縁膜(6)の上部に重ねて行
方向配線(8)が設けられる。この行方向配線(8)は
コンタクトホール(7)を通じて接続電極(4)と接続
している。行方向配線の厚さは40〜60μmが適当で
ある。行方向配線の行方向の長さは設計に基ずいて基板
の行方向の長さに従って形成され、行方向配線の列方向
の長さは100〜500μmが適当である。A row-direction wiring (8) is provided on top of the strip-shaped insulating film (6). The row wiring (8) is connected to the connection electrode (4) through the contact hole (7). The thickness of the row direction wiring is suitably from 40 to 60 μm. The length of the row wiring in the row direction is formed according to the length of the substrate in the row direction based on the design, and the length of the row wiring in the column direction is suitably 100 to 500 μm.
【0022】基板の材料としては、絶縁性材料が用いら
れ、例えば、石英ガラス、Na等の不純物の含有量を低
減したガラス、青板ガラス、スパッタ法等によりSiO
2を積層した青板ガラス、アルミナ等のセラミック類な
どが挙げられる。As a material of the substrate, an insulating material is used, for example, quartz glass, glass with a reduced content of impurities such as Na, blue plate glass, SiO 2 by sputtering or the like.
Blue-sheet glass laminated with 2 , ceramics such as alumina, and the like.
【0023】絶縁膜の材料としては、一般的なガラスペ
ーストを用いることができる。As a material for the insulating film, a general glass paste can be used.
【0024】素子電極、接続電極、行方向配線および列
方向配線の材料は、導電性を有するものであれば制限は
ないが、例えば、Ni・Cr・Au・Mo・W・Pt・
Ti・Al・Cu・Pd等の金属またはこれらの合金、
Pd・Ag・Au・RuO2・Pd−Ag等の金属や金
属酸化物とガラス類とから構成される印刷導体、ポリシ
リコン等の半導体材料、In2O3−SnO2等の透明導
電体などが挙げられる。The material of the device electrode, the connection electrode, the row direction wiring and the column direction wiring is not limited as long as it has conductivity. For example, Ni / Cr / Au / Mo / W / Pt /
Metals such as Ti, Al, Cu, Pd or alloys thereof;
Pd · Ag · Au · RuO 2 · Pd-Ag or the like of the metal or metal oxide and printed conductor composed of a glasses, semiconductor materials such as polysilicon, a transparent conductive material such as In 2 O 3 -SnO 2, etc. Is mentioned.
【0025】電子放出部形成用薄膜の材料としては、例
えば、Pt・Ru・Ag・Au・Ti・In・Cu・C
r・Fe・Zn・Sn・Ta・W・Pb・Ag−Mg・
Ni−Cu等の金属、PdO・SnO2・In2O3・P
bO・Sb2O3等の酸化物、HfB2・ZrB2・LaB
6・CeB6・YB4・GdB4等のホウ化物、TiC・Z
rC・HfC・TaC・SiC・WC等の炭化物、Ti
N・ZrN・HfN等の窒化物、Si・Ge等の半導
体、カーボンなどが挙げられる。Examples of the material of the thin film for forming an electron emitting portion include Pt, Ru, Ag, Au, Ti, In, Cu, and C.
r-Fe-Zn-Sn-Ta-W-Pb-Ag-Mg-
Ni-Cu or the like metal, PdO · SnO 2 · In 2 O 3 · P
oxides such as bO · Sb 2 O 3, HfB 2 · ZrB 2 · LaB
Borides such as 6 · CeB 6 · YB 4 · GdB 4, TiC · Z
Carbides such as rC / HfC / TaC / SiC / WC, Ti
Nitrides such as N / ZrN / HfN, semiconductors such as Si / Ge, carbon, and the like.
【0026】電子放出部形成用薄膜は上記材料の微粒子
膜からなる。微粒子膜とは、複数の微粒子が膜状に集合
したものであり、その微細構造は、微粒子が個々に分散
配置した状態に加えて、微粒子が互いに隣接または重な
りあった状態(島状も含む)の構造を有する。The thin film for forming the electron emitting portion is composed of a fine particle film of the above-mentioned material. A fine particle film is a film in which a plurality of fine particles are aggregated in a film shape. The fine structure is such that the fine particles are adjacent to each other or overlap with each other (including an island shape) in addition to the state in which the fine particles are individually dispersed and arranged. It has the structure of
【0027】以上の構成が1個の表面伝導型電子放出素
子単位(1個の表面伝導型電子放出素子を含む配線単
位)となり、この単位が基板(1)上に行列状に多数設
けられ、電子源基板が形成される。The above structure is one surface conduction electron-emitting device unit (a wiring unit including one surface conduction electron-emitting device), and a large number of such units are provided on the substrate (1) in a matrix. An electron source substrate is formed.
【0028】次に、本発明の電子源基板の製造方法を、
図4の(I)〜(V)を参照しながら説明する。この図
4は、3行3列で合計9個の表面伝導型電子放出素子単
位を配置した場合を表わす。Next, a method of manufacturing an electron source substrate according to the present invention will be described.
This will be described with reference to FIGS. FIG. 4 shows a case where a total of nine surface conduction electron-emitting device units are arranged in three rows and three columns.
【0029】工程(I):よく洗浄した基板(1)の表
面上に素子電極に使用する前記導電性材料からなる導電
性薄膜を形成する。この基板をフォトリソグラフ法によ
って微細加工し、図4(I)に示すように素子電極
(2)のパターンを形成する。このとき、絶縁膜(6)
の形成時(工程(III))の位置ズレを考慮してパタ
ーン寸法を設計する。すなわち、絶縁膜が、一対の素子
電極の列方向の両端部を覆うようにパターン寸法を設計
する。このとき、一対の素子電極の列方向の長さが、絶
縁膜に覆われていない一対の素子電極の列方向の長さよ
り60μm以上長くなるように設計することが望まし
い。Step (I): A conductive thin film made of the conductive material used for the device electrode is formed on the surface of the well-cleaned substrate (1). This substrate is finely processed by a photolithographic method to form a pattern of an element electrode (2) as shown in FIG. At this time, the insulating film (6)
The pattern size is designed in consideration of the positional deviation at the time of forming (step (III)). That is, the pattern dimensions are designed so that the insulating film covers both ends of the pair of element electrodes in the column direction. At this time, it is desirable that the length of the pair of element electrodes in the column direction is designed to be 60 μm or more longer than the length of the pair of element electrodes not covered with the insulating film in the column direction.
【0030】工程(II):接続電極および列方向配線
に用いられる前記導電性材料からなる導電性ペースト
を、スクリーン印刷法によって上記工程(I)の基板上
に塗布し、次いで焼成して図4(II)に示すように接
続電極(4)及び列方向配線(5)のパターンを形成す
る。Step (II): A conductive paste made of the above-mentioned conductive material used for the connection electrodes and the column-directional wiring is applied on the substrate of the above-mentioned step (I) by a screen printing method, and then baked. As shown in (II), a pattern of the connection electrode (4) and the column wiring (5) is formed.
【0031】工程(III):絶縁性ペースト(例え
ば、ガラスペースト)を工程(I)で設計したパターン
寸法にしたがってスクリーン印刷法によって塗布し、次
いで焼成を行い、帯状の絶縁膜(6)のパターン(図4
(III))を形成する。この絶縁膜(6)に、コンタ
クトホール(7)を接続電極(4)上に通じるように開
ける。Step (III): An insulating paste (for example, a glass paste) is applied by a screen printing method according to the pattern dimensions designed in the step (I), and then baked to form a pattern of the strip-shaped insulating film (6). (FIG. 4
(III)) is formed. A contact hole (7) is opened in the insulating film (6) so as to communicate with the connection electrode (4).
【0032】工程(IV):上記の絶縁膜上に、行方向
配線に用いられる前記導電性材料からなる導電性ペース
トを、スクリーン印刷法によって印刷し、次いで焼成を
行い、図4(IV)に示すように行方向配線(8)を形
成する。この行方向配線(8)はコンタクトホール
(7)を通して接続電極(4)へ通電可能となるように
形成する。Step (IV): A conductive paste made of the conductive material used for row-directional wiring is printed on the insulating film by a screen printing method, and then baked, as shown in FIG. As shown, a row wiring (8) is formed. The row wiring (8) is formed so as to be able to conduct electricity to the connection electrode (4) through the contact hole (7).
【0033】工程(V):前記材料からなる電子放出部
形成用薄膜を、工程(IV)で形成された基板の表面上
の全面に形成する。次いで、フォトリソグラフ法によっ
て図4(V)に示すように電子放出部形成用薄膜のパタ
ーニングを行い、これに電子放出部(3)を形成する。
このとき、電子放出部形成用薄膜は、一対の素子電極間
の全体に形成されることが望ましい。以上のようにして
本発明の電子源基板が作製される。Step (V): A thin film for forming an electron emission portion made of the above-mentioned material is formed on the entire surface of the substrate formed in step (IV). Next, as shown in FIG. 4 (V), the electron-emitting portion forming thin film is patterned by photolithography to form an electron-emitting portion (3).
At this time, it is desirable that the thin film for forming an electron-emitting portion is formed entirely between the pair of device electrodes. As described above, the electron source substrate of the present invention is manufactured.
【0034】さらに、このようにして作製された電子源
基板は、その上部にフェースプレーとが配置され、真空
外囲器内に設置される。図3に、図1の電子源基板のB
−B線断面図およびこの電子源基板の上部に組み合わさ
れたフェースプレートの断面図を示す。フェースプレー
トは、ガラス基板(9)の表面上に蛍光体層(10)お
よびメタルバック層(11)が積層されている。Further, the electron source substrate manufactured as described above has a face plate disposed thereon, and is set in a vacuum envelope. FIG. 3 shows B of the electron source substrate of FIG.
FIG. 2B shows a cross-sectional view taken along line B and a cross-sectional view of a face plate combined with the upper portion of the electron source substrate. The face plate has a phosphor layer (10) and a metal back layer (11) laminated on a surface of a glass substrate (9).
【0035】この真空外囲器内において、接続電極に通
電可能な行方向配線(8)、及び列方向配線(5)を通
じて素子電極(2)間に電圧を印加し、上方のメタルバ
ック層(11)へはこれを正の電位として電圧を加え
る。この操作によって一対の素子電極(2)間の電子放
出部(3)から電子が放出される。放出された電子はメ
タルバック層(11)を通って蛍光層(10)に照射さ
れ、蛍光が発生し、画像が形成される。このように本発
明の電子源基板は、画像形成装置において発光素子や平
面型表示装置として適用される。In this vacuum envelope, a voltage is applied between the device electrodes (2) through the row-direction wiring (8) and the column-direction wiring (5) that can supply current to the connection electrodes, and the upper metal back layer ( A voltage is applied to 11) using this as a positive potential. By this operation, electrons are emitted from the electron emitting portion (3) between the pair of device electrodes (2). The emitted electrons irradiate the fluorescent layer (10) through the metal back layer (11) to generate fluorescent light, thereby forming an image. As described above, the electron source substrate of the present invention is applied as a light emitting element or a flat display device in an image forming apparatus.
【0036】[0036]
【実施例】以下、本発明を図3および図4を参照しなが
ら、実施例によりさらに説明するが、本発明はこれらに
限定するものではない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be further described below with reference to the embodiments shown in FIGS. 3 and 4. However, the present invention is not limited to these embodiments.
【0037】実施例1 工程(I):青板ガラスからなる基板(1)を準備し、
よく洗浄した。この基板(1)の表面上にスパッタ蒸着
法によって金属薄膜を形成した。次いで、フォトリソエ
ッチング法によって図4(I)に示すように素子電極
(2)を形成した。素子電極(2)は、厚さ50オング
ストロームのTiを下引層とし、厚さ1000オングス
トロームのNi薄膜から成っている。また、一対の素子
電極間の間隔を2μm、素子電極の列方向の長さを26
0μm、行方向の長さを300μmとした。このときパ
ターン寸法として、完成した電子源基板上で、絶縁膜に
覆われていない一対の素子電極の列方向の長さが200
μmとなるように、一対の素子電極(2)の列方向の両
端からそれぞれ30μmの領域が絶縁膜(6)と重なる
パターンを設計した。すなわちこのパターンでは、完成
した電子源基板状で、一対の素子電極の列方向の長さ
が、絶縁膜に覆われていない一対の素子電極の列方向の
長さより60μm長い。Example 1 Step (I): A substrate (1) made of blue sheet glass was prepared.
Washed well. A metal thin film was formed on the surface of the substrate (1) by a sputter deposition method. Next, an element electrode (2) was formed by photolithography as shown in FIG. The device electrode (2) is made of a Ni thin film having a thickness of 1000 angstroms with an undercoat layer of Ti having a thickness of 50 angstroms. The distance between the pair of element electrodes is 2 μm, and the length of the element electrodes in the column direction is 26 μm.
0 μm, and the length in the row direction was 300 μm. At this time, the length in the column direction of the pair of element electrodes not covered with the insulating film on the completed electron source substrate is 200 as the pattern dimension.
A pattern was designed such that a region of 30 μm from both ends in the column direction of the pair of device electrodes (2) overlapped with the insulating film (6) so as to be μm. That is, in this pattern, in the completed electron source substrate, the length of the pair of device electrodes in the column direction is longer than the length of the pair of device electrodes not covered with the insulating film by 60 μm.
【0038】工程(II):Agペーストインキをスク
リーン印刷法によって上記工程(I)の基板上に塗布
し、図4(II)に示すように接続電極(4)および列
方向配線(5)のパターンを形成した。次いでこれを焼
成した。Step (II): Ag paste ink is applied on the substrate of the above step (I) by a screen printing method, and as shown in FIG. 4 (II), the connection electrode (4) and the column-directional wiring (5) are formed. A pattern was formed. It was then fired.
【0039】工程(III):ガラスを主成分としたペ
ーストを、工程(I)で設計したパターン寸法にしたが
ってスクリーン印刷法によって塗布し、次いで焼成を行
い、帯状の絶縁膜(6)のパターン(図4(III))
を形成した。この絶縁膜(6)に、コンタクトホール
(7)を接続電極(4)へ通じるように開けた。絶縁膜
(6)の厚さは15μm、列方向の長さは400μmで
あった。また、設計したパターン寸法に対する絶縁膜
(6)の列方向の位置ズレは20μmであった。Step (III): A paste containing glass as a main component is applied by a screen printing method in accordance with the pattern dimensions designed in the step (I), and then baked to obtain a pattern of the strip-shaped insulating film (6). (Fig. 4 (III))
Was formed. A contact hole (7) was opened in the insulating film (6) so as to communicate with the connection electrode (4). The thickness of the insulating film (6) was 15 μm, and the length in the column direction was 400 μm. The positional deviation of the insulating film (6) in the column direction with respect to the designed pattern dimension was 20 μm.
【0040】工程(IV):上記絶縁膜(6)の表面上
に、Agペーストをスクリーン印刷法によって印刷し、
次いで焼成を行い、図4(IV)に示すように行方向配
線(8)を形成した。この行方向配線(8)はコンタク
トホール(7)を通して接続電極(4)へ通電が可能と
なるようにした。行方向配線(8)の厚さは20μm、
列方向の長さは300μmであった。Step (IV): An Ag paste is printed on the surface of the insulating film (6) by a screen printing method.
Next, baking was performed to form row-directional wirings (8) as shown in FIG. The row-directional wiring (8) is configured to be able to conduct electricity to the connection electrode (4) through the contact hole (7). The thickness of the row wiring (8) is 20 μm,
The length in the row direction was 300 μm.
【0041】工程(V):有機金属溶液の塗布・焼成に
よって、厚さ約200オングストロームのPd微粒子か
らなる電子放出部形成用薄膜を、工程(IV)で形成し
た基板の表面上の全面に形成した。次いで、フォトリソ
グラフ法によって図4(V)に示すように上記薄膜のパ
ターニングを行い、これに電子放出部(3)を形成し
た。このとき、電子放出部形成用薄膜は一対の素子電極
間の全体に形成した。Step (V): By applying and baking an organic metal solution, a thin film for forming an electron emitting portion composed of Pd fine particles having a thickness of about 200 Å is formed on the entire surface of the substrate formed in the step (IV). did. Next, the thin film was patterned by a photolithographic method as shown in FIG. 4 (V), and an electron emitting portion (3) was formed thereon. At this time, the thin film for forming an electron emission portion was formed entirely between the pair of device electrodes.
【0042】以上の工程によって、列方向配線(5)お
よび行方向配線(8)をそれぞれ10本ずつ形成し、1
00個の表面伝導型電子放出素子単位が行列状に配列し
た本発明の電子源基板を作製した。このとき、素子配列
のピッチを行列ともに600μmとなるように作製し
た。この電子源基板は、工程(III)において絶縁膜
(6)の位置ズレが生じたが、電子放出部(3)の長さ
に変化はなかった(設計通り200μmであった。)。According to the above steps, ten column-directional wirings (5) and ten row-directional wirings (8) are formed.
An electron source substrate of the present invention in which 00 surface conduction electron-emitting devices were arranged in a matrix was manufactured. At this time, the device was manufactured such that the pitch of the element array was 600 μm for both the matrix. In the electron source substrate, the position of the insulating film (6) was displaced in the step (III), but the length of the electron emission portion (3) was not changed (200 μm as designed).
【0043】次に上記の電子源基板を、図3に示すよう
に5mmの間隔でフェースプレートと対面させて組み合
せ、真空外囲器の中に設置した。フェースプレートのガ
ラス基板(9)は青板ガラスからなるものを用いた。蛍
光体層(10)形成は、感光性樹脂に蛍光体を混合して
スラリー状とし、これをガラス基板(9)へ塗布、乾燥
した後、フォトリソグラフ法によってパターニング形成
した。メタルバック層(11)の形成は、蛍光体層(1
0)の表面上にフィルミング処理を行った後、真空蒸着
によって厚さ約300オングストロームのAl薄膜を成
膜し、次いでこれを焼成することによりフィルム層を焼
失させて形成した。Next, as shown in FIG. 3, the above-mentioned electron source substrate was combined with the face plate facing the face plate at an interval of 5 mm, and set in a vacuum envelope. The glass substrate (9) of the face plate was made of blue plate glass. The phosphor layer (10) was formed by mixing a phosphor with a photosensitive resin to form a slurry, applying the slurry to a glass substrate (9), drying the slurry, and then performing patterning by photolithography. The formation of the metal back layer (11) is performed by using the phosphor layer (1).
After performing a filming process on the surface of 0), an Al thin film having a thickness of about 300 Å was formed by vacuum evaporation, and then fired to burn off the film layer, thereby forming a film.
【0044】実施例2 基板(1)を40cm角の大きさ(1辺の長さが40c
mの正方形)とし、表面伝導型電子放出素子単位を行列
方向にそれぞれ350個ずつ(行列合計122500
個)配置した以外は、実施例1と同様な電子源基板を作
製した。この電子源基板を実施例1と同様にしてフェー
スプレートと組み合せ、真空外囲器中に設置した。Example 2 The size of the substrate (1) was 40 cm square (the length of one side was 40 c).
m), and 350 surface conduction electron-emitting device units are arranged in the matrix direction, each having a matrix totaling 122500.
An electron source substrate similar to that of Example 1 was prepared except that the electron source substrates were arranged. This electron source substrate was combined with a face plate in the same manner as in Example 1, and placed in a vacuum envelope.
【0045】フェースプレートついては、蛍光体(2
2)をR、G、Bの各色によって塗り分けした以外は実
施例1と同様なものを使用した。As for the face plate, the phosphor (2
The same thing as in Example 1 was used except that 2) was separately applied by R, G and B colors.
【0046】実施例3 以下の記載以外は実施例1と同様にして電子源基板を作
製した。素子電極(2)の列方向の長さを500μm、
行方向の長さを250μmとした。このときのパターン
寸法として、完成した電子源基板上で、絶縁膜に覆われ
ていない一対の素子電極の列方向の長さが440μmと
なるように、一対の素子電極(2)の列方向の両端から
それぞれ30μmの領域が絶縁膜(6)と重なるパター
ンを設計した。すなわちこのパターンでは、完成した電
子源基板状で、一対の素子電極の列方向の長さが、絶縁
膜に覆われていない一対の素子電極の列方向の長さより
60μm長い。Example 3 An electron source substrate was manufactured in the same manner as in Example 1 except for the following. The length of the element electrode (2) in the column direction is 500 μm,
The length in the row direction was 250 μm. At this time, the pattern dimension of the pair of device electrodes (2) in the column direction is set so that the length in the column direction of the pair of device electrodes not covered with the insulating film is 440 μm on the completed electron source substrate. A pattern in which a region of 30 μm from each end overlaps with the insulating film (6) was designed. That is, in this pattern, in the completed electron source substrate, the length of the pair of device electrodes in the column direction is longer than the length of the pair of device electrodes not covered with the insulating film by 60 μm.
【0047】また、基板(1)を40cm角の大きさと
し、電子放出素子の素子配列のピッチを840μmに設
定し、表面伝導型電子放出素子単位を行列方向にそれぞ
れ350個ずつ(行列合計122500個)配置した。The size of the substrate (1) is 40 cm square, the pitch of the element array of the electron-emitting devices is set to 840 μm, and 350 surface conduction electron-emitting units are arranged in the matrix direction (total of 12,500 matrixes). ) Placed.
【0048】上記の電子源基板を実施例1と同様にして
フェースプレートと組み合せ、真空外囲器中に設置し
た。The above-mentioned electron source substrate was combined with a face plate in the same manner as in Example 1, and set in a vacuum envelope.
【0049】フェースプレートついては、蛍光体(2
2)をR、G、Bの各色によって塗り分けした以外は実
施例1と同様なものを使用した。Regarding the face plate, the phosphor (2
The same thing as in Example 1 was used except that 2) was separately applied by R, G and B colors.
【0050】(評価方法および評価結果)上記各実施例
の電子源基板の列方向配線(5)および行方向配線
(8)に所定の電圧を印加した。その後、フェースプレ
ートのメタルバック層(11)をアノード電極として、
これに電子の引き出し電圧3kVを印加した。列方向配
線(5)および行方向配線(8)の印加電圧を14Vへ
上げたところ、電子が電子放出部(3)から放出され
た。この放出電子量を印加電圧によって調整して、蛍光
体層(10)を任意に発光させ画像を形成した。実施例
1〜3のいずれの電子源基板においても画像は均一であ
り、画像の輝度の低下および輝度ムラは生じていなかっ
た。(Evaluation Method and Evaluation Results) A predetermined voltage was applied to the column wiring (5) and the row wiring (8) of the electron source substrate of each of the above embodiments. Then, using the metal back layer (11) of the face plate as an anode electrode,
An electron extraction voltage of 3 kV was applied to this. When the voltage applied to the column wiring (5) and the row wiring (8) was increased to 14 V, electrons were emitted from the electron emitting portion (3). The amount of emitted electrons was adjusted by the applied voltage, and the phosphor layer (10) was arbitrarily emitted to form an image. In each of the electron source substrates of Examples 1 to 3, the image was uniform, and no reduction in the luminance of the image and no uneven luminance occurred.
【0051】[0051]
【発明の効果】以上の説明から明らかなように本発明に
よれば、電子源基板の絶縁膜形成時において位置ズレが
生じても、絶縁膜に覆われていない一対の素子電極の列
方向の長さが一定であり、この素子電極間に形成される
電子放出部の長さも一定であるため、輝度の低下および
輝度ムラを抑えることができる。さらに、印刷法によっ
て電子源基板を作製するため、大画面の画像形成装置を
低コストで製造できる。As is apparent from the above description, according to the present invention, even if a position shift occurs during the formation of the insulating film on the electron source substrate, the pair of device electrodes not covered by the insulating film in the column direction is not covered by the insulating film. Since the length is constant and the length of the electron-emitting portion formed between the device electrodes is also constant, it is possible to suppress a decrease in luminance and luminance unevenness. Further, since the electron source substrate is manufactured by a printing method, a large-screen image forming apparatus can be manufactured at low cost.
【図1】本発明の電子源基板の平面図である。FIG. 1 is a plan view of an electron source substrate of the present invention.
【図2】図(a)は図1におけるA−A線断面図であ
り、図(b)は絶縁膜形成時に位置ズレが生じた場合の
図1におけるA−A線断面図である。FIG. 2A is a cross-sectional view taken along line AA in FIG. 1, and FIG. 2B is a cross-sectional view taken along line AA in FIG. 1 when a positional shift occurs during formation of an insulating film.
【図3】図(a)は電子源基板の上部に組み合わされた
フェースプレートの断面図であり、図(b)は図1にお
けるB−B線断面図である。3A is a cross-sectional view of a face plate combined with an upper portion of an electron source substrate, and FIG. 3B is a cross-sectional view taken along line BB in FIG.
【図4】本発明の電子源基板の製造工程を示した平面図
である。FIG. 4 is a plan view showing a manufacturing process of the electron source substrate of the present invention.
【図5】図(a)は従来の表面伝導型電子放出素子の平
面図であり、図(b)は図(a)におけるC−C線断面
図である。FIG. 5A is a plan view of a conventional surface conduction electron-emitting device, and FIG. 5B is a cross-sectional view taken along line CC in FIG.
【図6】図(a)は従来の表面伝導型電子放出素子の平
面図であり、図(b)は図(a)におけるD−D線断面
図である。FIG. 6A is a plan view of a conventional surface conduction electron-emitting device, and FIG. 6B is a cross-sectional view taken along line DD in FIG.
【図7】図6の表面伝導型電子放出素子を備えた従来の
電子源基板の平面図である。FIG. 7 is a plan view of a conventional electron source substrate including the surface conduction electron-emitting device of FIG.
【図8】図(a)は図7におけるF−F線断面図であ
り、図(b)は絶縁膜形成時に位置ズレが生じた場合の
図7におけるF−F線断面図である。8A is a cross-sectional view taken along the line FF in FIG. 7, and FIG. 8B is a cross-sectional view taken along the line FF in FIG. 7 when a positional shift occurs during the formation of the insulating film.
1 基板 2 素子電極 3 電子放出部 4 接続電極 5 列方向配線 6 絶縁膜 7 コンタクトホール 8 行方向配線 9 ガラス基板 10 蛍光体層 11 メタルバック層 12 電子放出部形成用薄膜 DESCRIPTION OF SYMBOLS 1 Substrate 2 Element electrode 3 Electron emission part 4 Connection electrode 5 Column wiring 6 Insulating film 7 Contact hole 8 Row wiring 9 Glass substrate 10 Phosphor layer 11 Metal back layer 12 Thin film for electron emission part formation
Claims (4)
板上に形成された複数の行方向配線と、該複数の行方向
配線と電気的に絶縁され略垂直方向に複数形成された列
方向配線との間に配され、該表面伝導型放出素子の一対
の素子電極の一方が該行方向配線と電気的に接続され、
残る一方の素子電極が該列方向配線と電気的に接続され
てなる電子源基板において、 前記絶縁のために行方向配線の下に帯状に形成された絶
縁膜が、前記一対の素子電極の列方向の両端部を覆うよ
うに形成されていることを特徴とする電子源基板。1. A plurality of row-direction wirings formed on a substrate and a plurality of columns formed in a substantially vertical direction and electrically insulated from the plurality of row-direction wirings. One of a pair of device electrodes of the surface conduction electron-emitting device is electrically connected to the row direction wiring,
In the electron source substrate in which one of the remaining element electrodes is electrically connected to the column-directional wiring, an insulating film formed in a strip shape under the row-directional wiring for insulation is formed of a column of the pair of element electrodes. An electron source substrate formed so as to cover both ends in the direction.
基板に対向して蛍光体層が設けられたフェースプレート
を備えた画像形成装置。2. An image forming apparatus comprising: the electron source substrate according to claim 1; and a face plate provided with a phosphor layer facing the electron source substrate.
形成装置の製造方法であって、該電子源基板上の配線お
よび絶縁膜を印刷法によって形成することを特徴とする
画像形成装置の製造方法。3. A method for manufacturing an image forming apparatus comprising the electron source substrate according to claim 1, wherein the wiring and the insulating film on the electron source substrate are formed by a printing method. Manufacturing method.
3記載の画像形成装置の製造方法。4. The method according to claim 3, wherein the printing method is a screen printing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4892695A JP3135813B2 (en) | 1995-03-09 | 1995-03-09 | Image forming apparatus and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4892695A JP3135813B2 (en) | 1995-03-09 | 1995-03-09 | Image forming apparatus and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08250046A JPH08250046A (en) | 1996-09-27 |
JP3135813B2 true JP3135813B2 (en) | 2001-02-19 |
Family
ID=12816873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4892695A Expired - Fee Related JP3135813B2 (en) | 1995-03-09 | 1995-03-09 | Image forming apparatus and method of manufacturing the same |
Country Status (1)
Country | Link |
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JP (1) | JP3135813B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3450533B2 (en) | 1995-08-08 | 2003-09-29 | キヤノン株式会社 | Method of manufacturing electron source substrate and image forming apparatus |
JP3459705B2 (en) | 1995-07-24 | 2003-10-27 | キヤノン株式会社 | Method of manufacturing electron source substrate and method of manufacturing image forming apparatus |
-
1995
- 1995-03-09 JP JP4892695A patent/JP3135813B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3459705B2 (en) | 1995-07-24 | 2003-10-27 | キヤノン株式会社 | Method of manufacturing electron source substrate and method of manufacturing image forming apparatus |
JP3450533B2 (en) | 1995-08-08 | 2003-09-29 | キヤノン株式会社 | Method of manufacturing electron source substrate and image forming apparatus |
Also Published As
Publication number | Publication date |
---|---|
JPH08250046A (en) | 1996-09-27 |
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