JP3132583B2 - Phase detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase detection circuit.

[0002]

2. Description of the Related Art In a conventional phase detection circuit, a method of performing phase detection by means such as a phase synchronization method is generally used. In this phase synchronization system, an oscillation signal output from a voltage controlled oscillation circuit or a frequency-divided signal of the oscillation signal and a phase detection signal are compared in phase in a phase comparison circuit, and the delay and advance of both phases are determined. As a result, a phase difference signal is output as a voltage output, and the phase detection of the phase-detected signal is performed through a phase-locked loop formed by controlling the frequency of the voltage-controlled oscillation circuit with the phase difference signal. In this phase synchronization system, even if it is integrated into a semiconductor, circuits such as a voltage conversion portion and a voltage controlled oscillation circuit in the phase comparison circuit have to be configured using discrete circuit elements. It is the current situation. Therefore, the accuracy of the phase detection in the above-mentioned phase locked loop depends on the state of these discrete circuit elements.

[0003]

The above-described conventional phase detection circuit has a disadvantage that the phase detection accuracy depends on the discrete circuit element used.

[0004]

A phase detection circuit according to the present invention comprises a means for shaping the waveform of a phase-detected signal formed by phase-modulating a predetermined carrier and outputting the waveform-shaped phase-detected signal. The waveform-shaped phase-detected signal is input, and changes at a time T corresponding to a rising edge of the waveform-shaped phase-detected signal via a sampling clock having a frequency that is an integral multiple of the frequency of the carrier. Means for generating and outputting an edge pulse by detecting an edge to be generated, and a plurality of pulse signals having the same rising frequency and the same frequency as the carrier wave by dividing the frequency of the sampling clock. Means for generating a train, and a phase signal detecting a pulse signal which rises at a time closest to the time T before and after the time T from the plurality of pulse signal trains. Configured with a means for selecting a signal.

[0005]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a waveform shaping circuit 1, a frequency dividing counter 2, and a changing edge detecting circuit 3
And a phase selection circuit 4 and a phase comparison circuit 5. 2 (a), (b), (c), (d),
(E), (f), (g), (h), (i), (j),
(K) and (l) show timing diagrams of the phase detection signal and the internal signal.

In FIG. 1, a phase detection signal 101 (see FIG. 2A) formed by phase-modulating a predetermined carrier signal is subjected to waveform shaping by a waveform shaping circuit 1, and a shaped phase detection signal 103 after shaping. (See FIG. 2C) is input to the changing edge detection circuit 3. On the other hand, a sampling clock 102 (see FIG. 2B) having a frequency which is an integral multiple of the frequency of the carrier signal and which is sufficiently high is input to the frequency dividing counter 2 and the changing edge detecting circuit 3. In the changing edge detection circuit 3, the sampling clock 1
2, an up-edge pulse 104 (see FIG. 2D) corresponding to the rising phase of the detected signal 103 after shaping is generated and input to the phase comparison circuit 5. Also,
In the frequency dividing counter 2, the sampling clock 10
2 are frequency-divided and reduced to the same frequency as the carrier signal, and sequentially pulse signal groups 105 to 110 having a time delay of one cycle of the sampling clock 102 (FIG. 2).
(See (e) to (j)) and input to the phase selection circuit 4 and the phase comparison circuit 5. Phase comparison circuit 5
In, the phase comparison between the above-described up-edge pulse 104 input from the changing edge detection circuit 3 and these pulse signal groups 105 to 110 is performed.

In the phase comparison circuit 5, the pulse signal 10
Phase comparison result data corresponding to a pulse signal whose rising edge among the signals 5 to 110 has the same phase or is closest to the state of the same phase is output as the phase comparison result data 111. Now, the pulse signals 105, 106, 107, 108,
Assuming that the phase comparison result data when the rising edges of 109 and 110 have the same phase are A, B, C, D, E, and F, respectively, as apparent from FIGS. It can be seen that B corresponding to the signal 106 is output as the phase comparison result data 111 (see FIG. 2 (k)). The phase comparison result data 111 is input to the phase selection circuit 4, and the pulse signal groups 105 to 11 input from the frequency division counter 2 via the phase comparison result data 111
The pulse signal 106 is selected from 0 and output as the phase detection signal 112 (see FIG. 2 (l)).

[0009]

As described above, according to the present invention, it is possible to increase the phase detection accuracy by increasing the frequency of the sampling clock, eliminate any discrete circuit elements as circuit elements, and completely eliminate all circuit elements. Since it can be constituted by logic elements, semiconductor integration becomes possible, and there is an effect that low power consumption and space saving of the phase detection circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart of each signal in the present embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Waveform shaping circuit 2 Dividing counter 3 Change edge detection circuit 4 Phase selection output circuit 5 Phase comparison circuit

Claims (1)

(57) [Claims] 1. A means for waveform-shaping a phase-detected signal formed by phase-modulating a predetermined carrier and outputting a waveform-shaped phase-detected signal; and inputting the waveform-shaped phase-detected signal. Then, an edge pulse is generated by detecting an edge that changes at time T corresponding to a rising edge of the waveform-shaped phase-detected signal via a sampling clock having a frequency that is an integral multiple of the frequency of the carrier. Means for dividing the frequency of the sampling clock to generate a plurality of pulse signal trains having different rising phases and the same frequency as the frequency of the carrier wave; and the plurality of pulse signals. Means for selecting a pulse signal which rises at a time closest to the time T before and after the time T from the sequence as a phase detection signal. And a phase detection circuit.