JP3132023B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a bipolar integrated circuit.

[0002]

2. Description of the Related Art FIGS. 3 (a) to 3 (c) and FIG.
This will be described with reference to FIGS.

[0003] First, as shown in FIG. 3 (a), an N-type buried layer 2 in which arsenic or antimony is diffused is formed in a device planned region of a P-type semiconductor substrate 1, and then an N-type epitaxial layer 3 is grown. Next, a silicon oxide film 4 for insulation isolation is formed by LOCOS selective oxidation, and a collector lead layer 5 connected to the N-type buried layer 2 is formed by diffusing phosphorus or the like.

[0004] Next, as shown in FIG. 3 (b), using a resist (not shown) as a mask, a P-type impurity such as boron is accelerated at an energy of 10 to 30 keV and a dose (dose) of 1 ×.
After implanting 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² ions, the external base 6 is formed by annealing at 900 to 1000 ° C. for several tens of minutes in a nitrogen atmosphere.

At this time, the surface concentration of the external base 6 formed in the vicinity of the emitter becomes 1 × 10 ¹⁹ cm ⁻³ or more, and has a role of electrically drawing out from the intrinsic base immediately below the emitter onto the element surface with low resistance.

Next, as shown in FIG. 3C, a P-type impurity such as boron is ion-implanted at a low energy of 30 keV or less at a dose (dose) of 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ^-2 and is intrinsic. The base 7 is formed.

[0007] Next, as shown in FIG.
A polysilicon 11 is grown. Next, an N-type impurity such as arsenic is introduced into the polysilicon 11 by high-dose ion implantation of 1 × 10 ¹⁶ cm ⁻² or more.

Next, as shown in FIG. 4B, the polysilicon 11 is covered with a CVD silicon oxide film 12 and then heat-treated at 900 to 1000 ° C. for several tens of minutes in a nitrogen atmosphere to form N in the polysilicon 11. An emitter 14 is formed by introducing a mold impurity into the semiconductor substrate 1.

In the case where high performance is not required and the junction of the diffusion layer does not need to be made shallow, the emitter 14 is formed by ion-implanting an N-type impurity using a resist as a mask without growing the polysilicon 11. May be.

Next, as shown in FIG. 4C, the CVD silicon oxide film 12 is removed, and the polysilicon 11 is selectively etched to form an emitter electrode.

[0011]

In a conventional bipolar integrated circuit, an external base composed of a high-concentration P-type diffusion layer for electrically extracting the intrinsic base with low resistance is formed on the side surface of an N-type emitter.

Since the N-type emitter and the P-type external base are close to each other on the surface, the leakage current between the junctions caused by the reverse applied voltage between the emitter and the base is increased.

Therefore, the allowable limit of the reverse voltage applied to the emitter-base of the NPN-type bipolar integrated circuit must be kept low.

[0014] The method of manufacturing a semiconductor device of the present invention is less
Forming a first insulating film on one main surface of the semiconductor substrate on which the base layer and the collector extraction layer are formed ; and forming a second insulating film on the first insulating film. Forming an opening wider than the emitter by selectively etching a portion of the second insulating film located above the base layer ; and forming the second opening exposed in the opening of the second insulating film . A step of selectively etching the insulating film to open an emitter contact, a step of depositing polysilicon over the entire surface and embedding the emitter contact, and a step of selecting the polysilicon while leaving only the immediate vicinity of the emitter contact. Etching, and ion-implanting an N-type impurity to form the second
Immediately below the first insulating film exposed at the opening of the insulating film
At the same time introducing said N-type impurity into the semiconductor substrate and the polysilicon, the introduction of the N-type impurity in the polysilicon by thermal treatment from said emitter contact to said semiconductor substrate, the opening of the second insulating film Dew
By activating the N-type impurity introduced into the semiconductor substrate immediately below the first insulating film that issued the base
In the source layer, a high concentration N located immediately below the polysilicon is used.
Type impurity layer and both sides of the high concentration N-type impurity layer
Forming an emitter layer made of a low-concentration N-type impurity layer .

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to (c) and FIGS. 2 (a) to (c).

First, as shown in FIG. 1A, an N-type buried layer 2 is formed on a P-type semiconductor substrate 1, an N-type epitaxial layer 3 is grown, and a silicon oxide film 4 is formed by a LOCOS selective oxidation method. I do. Next, a collector extraction layer 5 connected to the N-type buried layer 2 is formed, and an external base 6 and an intrinsic base 7 are formed.

Next, as shown in FIG. 1B, a silicon oxide film 8 having a thickness of 500 to 1000 A is grown by a thermal oxidation method, and then a thickness of 1000 to 2000 A is formed by a CVD method.
A silicon nitride film 9 is grown.

Next, as shown in FIG. 1C, the silicon nitride film 9 is etched by chemical dry etching using CF ₄ gas to form an opening wider than the emitter contact.

Next, as shown in FIG. 2A, the silicon oxide film 8 is etched using buffered hydrofluoric acid using a resist (not shown) as a mask to open an emitter contact 10. Next, the thickness of 1000 to 1000
A 2000 A polysilicon 11 is grown and the emitter contact 10 is buried.

[0020] Then, as shown in FIG. 2 (b), the emitter contact 10 and wide rather remaining <br/> each side 0.2μm than the opening, anisotropically etching the polysilicon 11 by RIE or the like .

Here, an N-type impurity such as arsenic is added to 1 × 10 ¹⁶
By implanting a high dose ion of cm ⁻² or more, N-type impurities are introduced from the openings of the silicon nitride film 9 on both sides of the polysilicon 11 through the silicon oxide film 8 to form low concentration emitters 12 and 13.

Next, as shown in FIG. 2C, an N-type impurity is diffused from the polysilicon 11 by performing a heat treatment at 900 to 1000 ° C. in a nitrogen atmosphere to form a high concentration emitter 14. At the same time, low concentration emitters 12,1
The N-type impurity 3 is activated and diffuses in the substrate 1 to overlap with the high-concentration emitter 14.

At this time, the surface concentration of the low-concentration emitters 12 and 13 is set to be equal to the surface concentration of the intrinsic base 7.
1/10 to 1/100 of the surface concentration of the high concentration emitter 14
Adjust to

[0024]

By forming a low-concentration emitter on the periphery of a high-concentration emitter serving as an intrinsic emitter, a concentration gradient with an adjacent external base can be reduced.

As a result, the electric field intensity in the depletion layer at the emitter-base junction surface could be reduced. The leakage current due to the reverse applied voltage between the emitter and the base is reduced, and the allowable reverse applied voltage value can be increased.

The low-concentration N-type diffusion layer introduced into the outer periphery of the emitter only compensates for high-concentration P-type impurities near the surface of the base layer, and does not affect the forward characteristics of the emitter-base.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.

FIG. 2 is a sectional view showing one embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a bipolar integrated circuit according to a conventional technique in the order of steps.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a bipolar integrated circuit according to a conventional technique in the order of steps.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 N-type buried layer 3 N-type epitaxial layer 4 Silicon oxide film 5 Collector extraction layer 6 External base 7 Intrinsic base 8 Silicon oxide film 9 Silicon nitride film 10 Emitter contact 11 Polysilicon 12, 13 Low concentration emitter 14 High concentration emitter

Claims (1)

(57) [Claims] At least a base layer and a collector drawer
Forming a first insulating film on one main surface of the semiconductor substrate on which the layers have been formed, forming a second insulating film on the first insulating film, and forming the second insulating film on the first insulating film. On the base layer of
Forming an opening wider than the emitter by selectively etching a portion located in the portion ; and forming an opening in the second insulating film.
Selectively etching the exposed first insulating film to open an emitter contact, depositing polysilicon over the entire surface and embedding the emitter contact, and removing the emitter contact only in the immediate vicinity thereof. Selectively etching polysilicon, and introducing the N-type impurity into the semiconductor substrate and the polysilicon immediately below the first insulating film exposed to the opening of the second insulating film by ion-implanting an N-type impurity; And introducing the N-type impurity in the polysilicon from the emitter contact into the semiconductor substrate by heat treatment .
The N-type impurity introduced into the semiconductor substrate immediately below the first insulating film exposed to the opening of the second insulating film is activated, so that the polysilicon layer is formed in the base layer.
A high-concentration N-type impurity layer located below and the high-concentration N-type impurity
A low-concentration N-type impurity layer overlapping both sides of the layer
Method of manufacturing a semiconductor device forming a bipolar transistor and a step you form an emitter layer.